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Update regsiter to control the MatrixSpectral Module
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r320:0a6f2549f618 (MINI-LFR) WFP_MS-0-1-4 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench
2 -- LEON3 Demonstration design test bench
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 --
7 --
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 -- IN ADVANCE IN WRITING.
10 -- IN ADVANCE IN WRITING.
11 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
12
12
13 LIBRARY ieee;
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.ALL;
14 USE ieee.std_logic_1164.ALL;
15
15
16 --LIBRARY std;
16 --LIBRARY std;
17 --USE std.textio.ALL;
17 --USE std.textio.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
23 LIBRARY gaisler;
23 LIBRARY gaisler;
24 USE gaisler.memctrl.ALL;
24 USE gaisler.memctrl.ALL;
25 USE gaisler.leon3.ALL;
25 USE gaisler.leon3.ALL;
26 USE gaisler.uart.ALL;
26 USE gaisler.uart.ALL;
27 USE gaisler.misc.ALL;
27 USE gaisler.misc.ALL;
28 USE gaisler.libdcom.ALL;
28 USE gaisler.libdcom.ALL;
29 USE gaisler.sim.ALL;
29 USE gaisler.sim.ALL;
30 USE gaisler.jtagtst.ALL;
30 USE gaisler.jtagtst.ALL;
31 USE gaisler.misc.ALL;
31 USE gaisler.misc.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 --LIBRARY micron;
36 --LIBRARY micron;
37 --USE micron.components.ALL;
37 --USE micron.components.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.testbench_package.ALL;
42 USE lpp.testbench_package.ALL;
43 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.lpp_lfr_pkg.ALL;
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.CY7C1061DV33_pkg.ALL;
46 USE lpp.CY7C1061DV33_pkg.ALL;
47
47
48 ENTITY testbench IS
48 ENTITY testbench IS
49 END;
49 END;
50
50
51
52
53
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55
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60
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69
51 ARCHITECTURE behav OF testbench IS
70 ARCHITECTURE behav OF testbench IS
52 CONSTANT INDEX_LFR : INTEGER := 15;
71 CONSTANT INDEX_LFR : INTEGER := 15;
53 CONSTANT ADDR_LFR : INTEGER := 15;
72 CONSTANT ADDR_LFR : INTEGER := 15;
54 -- REG MS
73 -- REG MS
55 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
74 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
56 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
75 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
57 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
76 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
58 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
77 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
78
59 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
79 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
60 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
80 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
61 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
81 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
82 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C";
83
84 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
85 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
86 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
87 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
88
89 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
90 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
91 --X"00000F38";
92 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F";
93
62 -- REG WAVEFORM
94 -- REG WAVEFORM
63 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
95 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
64 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
96 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
65 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
97 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
66 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
98 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
67 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
99
68 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
100 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
69 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
101 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
70 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
102 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
71 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
103 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
72 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
104
73 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
105 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60";
74 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
106 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64";
75 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
107 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68";
76 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
108 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C";
77 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
109
78 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
110 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70";
111 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74";
112 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78";
113 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C";
79 -- RAM ADDRESS
114 -- RAM ADDRESS
80 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
115 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
81 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
116 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
82 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
117 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
83 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
118 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
84
119
85
120
86 -- Common signal
121 -- Common signal
87 SIGNAL clk49_152MHz : STD_LOGIC := '0';
122 SIGNAL clk49_152MHz : STD_LOGIC := '0';
88 SIGNAL clk25MHz : STD_LOGIC := '0';
123 SIGNAL clk25MHz : STD_LOGIC := '0';
89 SIGNAL rstn : STD_LOGIC := '0';
124 SIGNAL rstn : STD_LOGIC := '0';
90
125
91 -- ADC interface
126 -- ADC interface
92 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
127 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
93 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
128 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
94 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
129 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
95
130
96 -- AD Converter RHF1401
131 -- AD Converter RHF1401
97 SIGNAL sample : Samples14v(7 DOWNTO 0);
132 SIGNAL sample : Samples14v(7 DOWNTO 0);
98 SIGNAL sample_val : STD_LOGIC;
133 SIGNAL sample_val : STD_LOGIC;
99
134
100 -- AHB/APB SIGNAL
135 -- AHB/APB SIGNAL
101 SIGNAL apbi : apb_slv_in_type;
136 SIGNAL apbi : apb_slv_in_type;
102 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
137 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
103 SIGNAL ahbsi : ahb_slv_in_type;
138 SIGNAL ahbsi : ahb_slv_in_type;
104 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
139 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
105 SIGNAL ahbmi : ahb_mst_in_type;
140 SIGNAL ahbmi : ahb_mst_in_type;
106 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
141 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
107
142
108 SIGNAL bias_fail_bw : STD_LOGIC;
143 SIGNAL bias_fail_bw : STD_LOGIC;
109
144
110 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
111 -- LPP_WAVEFORM
146 -- LPP_WAVEFORM
112 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
113 CONSTANT data_size : INTEGER := 96;
148 CONSTANT data_size : INTEGER := 96;
114 CONSTANT nb_burst_available_size : INTEGER := 50;
149 CONSTANT nb_burst_available_size : INTEGER := 50;
115 CONSTANT nb_snapshot_param_size : INTEGER := 2;
150 CONSTANT nb_snapshot_param_size : INTEGER := 2;
116 CONSTANT delta_vector_size : INTEGER := 2;
151 CONSTANT delta_vector_size : INTEGER := 2;
117 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
152 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
118
153
119 SIGNAL reg_run : STD_LOGIC;
154 SIGNAL reg_run : STD_LOGIC;
120 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
155 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
121 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
156 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
157 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
158 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
124 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
159 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 SIGNAL enable_f0 : STD_LOGIC;
161 SIGNAL enable_f0 : STD_LOGIC;
127 SIGNAL enable_f1 : STD_LOGIC;
162 SIGNAL enable_f1 : STD_LOGIC;
128 SIGNAL enable_f2 : STD_LOGIC;
163 SIGNAL enable_f2 : STD_LOGIC;
129 SIGNAL enable_f3 : STD_LOGIC;
164 SIGNAL enable_f3 : STD_LOGIC;
130 SIGNAL burst_f0 : STD_LOGIC;
165 SIGNAL burst_f0 : STD_LOGIC;
131 SIGNAL burst_f1 : STD_LOGIC;
166 SIGNAL burst_f1 : STD_LOGIC;
132 SIGNAL burst_f2 : STD_LOGIC;
167 SIGNAL burst_f2 : STD_LOGIC;
133 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
168 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
134 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
135 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
136 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
137 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
138 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
139 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL data_f0_in_valid : STD_LOGIC;
177 SIGNAL data_f0_in_valid : STD_LOGIC;
143 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f1_in_valid : STD_LOGIC;
180 SIGNAL data_f1_in_valid : STD_LOGIC;
146 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
181 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL data_f2_in_valid : STD_LOGIC;
183 SIGNAL data_f2_in_valid : STD_LOGIC;
149 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
184 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f3_in_valid : STD_LOGIC;
186 SIGNAL data_f3_in_valid : STD_LOGIC;
152 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
187 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
190 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
191 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f0_data_out_ack : STD_LOGIC;
192 SIGNAL data_f0_data_out_ack : STD_LOGIC;
158 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out_valid : STD_LOGIC;
195 SIGNAL data_f1_data_out_valid : STD_LOGIC;
161 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
196 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
162 SIGNAL data_f1_data_out_ack : STD_LOGIC;
197 SIGNAL data_f1_data_out_ack : STD_LOGIC;
163 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid : STD_LOGIC;
166 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
167 SIGNAL data_f2_data_out_ack : STD_LOGIC;
202 SIGNAL data_f2_data_out_ack : STD_LOGIC;
168 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
171 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
172 SIGNAL data_f3_data_out_ack : STD_LOGIC;
207 SIGNAL data_f3_data_out_ack : STD_LOGIC;
173
208
174 --MEM CTRLR
209 --MEM CTRLR
175 SIGNAL memi : memory_in_type;
210 SIGNAL memi : memory_in_type;
176 SIGNAL memo : memory_out_type;
211 SIGNAL memo : memory_out_type;
177 SIGNAL wpo : wprot_out_type;
212 SIGNAL wpo : wprot_out_type;
178 SIGNAL sdo : sdram_out_type;
213 SIGNAL sdo : sdram_out_type;
179
214
180 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
215 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
181 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL nSRAM_BE0 : STD_LOGIC;
217 SIGNAL nSRAM_BE0 : STD_LOGIC;
183 SIGNAL nSRAM_BE1 : STD_LOGIC;
218 SIGNAL nSRAM_BE1 : STD_LOGIC;
184 SIGNAL nSRAM_BE2 : STD_LOGIC;
219 SIGNAL nSRAM_BE2 : STD_LOGIC;
185 SIGNAL nSRAM_BE3 : STD_LOGIC;
220 SIGNAL nSRAM_BE3 : STD_LOGIC;
186 SIGNAL nSRAM_WE : STD_LOGIC;
221 SIGNAL nSRAM_WE : STD_LOGIC;
187 SIGNAL nSRAM_CE : STD_LOGIC;
222 SIGNAL nSRAM_CE : STD_LOGIC;
188 SIGNAL nSRAM_OE : STD_LOGIC;
223 SIGNAL nSRAM_OE : STD_LOGIC;
189
224
190 CONSTANT padtech : INTEGER := inferred;
225 CONSTANT padtech : INTEGER := inferred;
191 SIGNAL not_ramsn_0 : STD_LOGIC;
226 SIGNAL not_ramsn_0 : STD_LOGIC;
192
227
193 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
194 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL read_buffer : STD_LOGIC;
230 SIGNAL read_buffer : STD_LOGIC;
196 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
197 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
232 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
198 SIGNAL state_read_buffer_on_going : STD_LOGIC;
233 SIGNAL state_read_buffer_on_going : STD_LOGIC;
199 CONSTANT hindex : INTEGER := 1;
234 CONSTANT hindex : INTEGER := 1;
200 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
235 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
236 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
202 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
237 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
238 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
204
239
205 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209
244
210 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
245 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
246 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
247 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
213
248
214 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
249 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
250 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
251 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
217
252
218 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
253 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
254 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
255 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
221
256
222 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
257 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
258 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
259 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
225
260
226 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
261 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
227 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
262 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
228 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
263 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
229
264
230 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
265 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
231 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
266 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
232 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
267 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
233 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
234
269
235 SIGNAL current_data : INTEGER;
270 SIGNAL current_data : INTEGER;
236 SIGNAL LIMIT_DATA : INTEGER := 64;
271 SIGNAL LIMIT_DATA : INTEGER := 64;
237
272
238 SIGNAL read_buffer_temp : STD_LOGIC;
273 SIGNAL read_buffer_temp : STD_LOGIC;
239 SIGNAL read_buffer_temp_2 : STD_LOGIC;
274 SIGNAL read_buffer_temp_2 : STD_LOGIC;
240
275
241
276
242 BEGIN
277 BEGIN
243
278
244 -----------------------------------------------------------------------------
279 -----------------------------------------------------------------------------
245
280
246 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
281 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
247 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
282 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
248
283
249 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
250
285
251 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
286 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
252 TestModule_RHF1401_1 : TestModule_RHF1401
287 TestModule_RHF1401_1 : TestModule_RHF1401
253 GENERIC MAP (
288 GENERIC MAP (
254 freq => 24*(I+1),
289 freq => 24*(I+1),
255 amplitude => 8000/(I+1),
290 amplitude => 8000/(I+1),
256 impulsion => 0)
291 impulsion => 0)
257 PORT MAP (
292 PORT MAP (
258 ADC_smpclk => ADC_smpclk,
293 ADC_smpclk => ADC_smpclk,
259 ADC_OEB_bar => ADC_OEB_bar_CH(I),
294 ADC_OEB_bar => ADC_OEB_bar_CH(I),
260 ADC_data => ADC_data);
295 ADC_data => ADC_data);
261 END GENERATE MODULE_RHF1401;
296 END GENERATE MODULE_RHF1401;
262
297
263 -----------------------------------------------------------------------------
298 -----------------------------------------------------------------------------
264
299
265 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
300 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
266 GENERIC MAP (
301 GENERIC MAP (
267 ChanelCount => 8,
302 ChanelCount => 8,
268 ncycle_cnv_high => 79,
303 ncycle_cnv_high => 79,
269 ncycle_cnv => 500)
304 ncycle_cnv => 500)
270 PORT MAP (
305 PORT MAP (
271 cnv_clk => clk49_152MHz,
306 cnv_clk => clk49_152MHz,
272 cnv_rstn => rstn,
307 cnv_rstn => rstn,
273 cnv => ADC_smpclk,
308 cnv => ADC_smpclk,
274 clk => clk25MHz,
309 clk => clk25MHz,
275 rstn => rstn,
310 rstn => rstn,
276 ADC_data => ADC_data,
311 ADC_data => ADC_data,
277 ADC_nOE => ADC_OEB_bar_CH,
312 ADC_nOE => ADC_OEB_bar_CH,
278 sample => sample,
313 sample => sample,
279 sample_val => sample_val);
314 sample_val => sample_val);
280
315
281 -----------------------------------------------------------------------------
316 -----------------------------------------------------------------------------
282
317
283 lpp_lfr_1 : lpp_lfr
318 lpp_lfr_1 : lpp_lfr
284 GENERIC MAP (
319 GENERIC MAP (
285 Mem_use => use_CEL, -- use_RAM
320 Mem_use => use_CEL, -- use_RAM
286 nb_data_by_buffer_size => 32,
321 nb_data_by_buffer_size => 32,
287 nb_word_by_buffer_size => 30,
322 nb_word_by_buffer_size => 30,
288 nb_snapshot_param_size => 32,
323 nb_snapshot_param_size => 32,
289 delta_vector_size => 32,
324 delta_vector_size => 32,
290 delta_vector_size_f0_2 => 32,
325 delta_vector_size_f0_2 => 32,
291 pindex => INDEX_LFR,
326 pindex => INDEX_LFR,
292 paddr => ADDR_LFR,
327 paddr => ADDR_LFR,
293 pmask => 16#fff#,
328 pmask => 16#fff#,
294 pirq_ms => 6,
329 pirq_ms => 6,
295 pirq_wfp => 14,
330 pirq_wfp => 14,
296 hindex => 0,
331 hindex => 0,
297 top_lfr_version => X"000001")
332 top_lfr_version => X"000001")
298 PORT MAP (
333 PORT MAP (
299 clk => clk25MHz,
334 clk => clk25MHz,
300 rstn => rstn,
335 rstn => rstn,
301 sample_B => sample(2 DOWNTO 0),
336 sample_B => sample(2 DOWNTO 0),
302 sample_E => sample(7 DOWNTO 3),
337 sample_E => sample(7 DOWNTO 3),
303 sample_val => sample_val,
338 sample_val => sample_val,
304 apbi => apbi,
339 apbi => apbi,
305 apbo => apbo(15),
340 apbo => apbo(15),
306 ahbi => ahbmi,
341 ahbi => ahbmi,
307 ahbo => ahbmo(0),
342 ahbo => ahbmo(0),
308 coarse_time => coarse_time,
343 coarse_time => coarse_time,
309 fine_time => fine_time,
344 fine_time => fine_time,
310 data_shaping_BW => bias_fail_bw);
345 data_shaping_BW => bias_fail_bw);
311
346
312 -----------------------------------------------------------------------------
347 -----------------------------------------------------------------------------
313 --- AHB CONTROLLER -------------------------------------------------
348 --- AHB CONTROLLER -------------------------------------------------
314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
349 ahb0 : ahbctrl -- AHB arbiter/multiplexer
315 GENERIC MAP (defmast => 0, split => 0,
350 GENERIC MAP (defmast => 0, split => 0,
316 rrobin => 1, ioaddr => 16#FFF#,
351 rrobin => 1, ioaddr => 16#FFF#,
317 ioen => 0, nahbm => 2, nahbs => 1)
352 ioen => 0, nahbm => 2, nahbs => 1)
318 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
353 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
319
354
320
355
321
356
322 --- AHB RAM ----------------------------------------------------------
357 --- AHB RAM ----------------------------------------------------------
323 --ahbram0 : ahbram
358 --ahbram0 : ahbram
324 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
359 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
325 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
360 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
326 --ahbram1 : ahbram
361 --ahbram1 : ahbram
327 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
362 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
328 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
363 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
329 --ahbram2 : ahbram
364 --ahbram2 : ahbram
330 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
365 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
331 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
366 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
332 --ahbram3 : ahbram
367 --ahbram3 : ahbram
333 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
368 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
334 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
369 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
335
370
336 -----------------------------------------------------------------------------
371 -----------------------------------------------------------------------------
337 ----------------------------------------------------------------------
372 ----------------------------------------------------------------------
338 --- Memory controllers ---------------------------------------------
373 --- Memory controllers ---------------------------------------------
339 ----------------------------------------------------------------------
374 ----------------------------------------------------------------------
340 memctrlr : mctrl GENERIC MAP (
375 memctrlr : mctrl GENERIC MAP (
341 hindex => 0,
376 hindex => 0,
342 pindex => 0,
377 pindex => 0,
343 paddr => 0,
378 paddr => 0,
344 srbanks => 1
379 srbanks => 1
345 )
380 )
346 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
381 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
347
382
348 memi.brdyn <= '1';
383 memi.brdyn <= '1';
349 memi.bexcn <= '1';
384 memi.bexcn <= '1';
350 memi.writen <= '1';
385 memi.writen <= '1';
351 memi.wrn <= "1111";
386 memi.wrn <= "1111";
352 memi.bwidth <= "10";
387 memi.bwidth <= "10";
353
388
354 bdr : FOR i IN 0 TO 3 GENERATE
389 bdr : FOR i IN 0 TO 3 GENERATE
355 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
390 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
356 PORT MAP (
391 PORT MAP (
357 data(31-i*8 DOWNTO 24-i*8),
392 data(31-i*8 DOWNTO 24-i*8),
358 memo.data(31-i*8 DOWNTO 24-i*8),
393 memo.data(31-i*8 DOWNTO 24-i*8),
359 memo.bdrive(i),
394 memo.bdrive(i),
360 memi.data(31-i*8 DOWNTO 24-i*8));
395 memi.data(31-i*8 DOWNTO 24-i*8));
361 END GENERATE;
396 END GENERATE;
362
397
363 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
398 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
364 PORT MAP (address, memo.address(21 DOWNTO 2));
399 PORT MAP (address, memo.address(21 DOWNTO 2));
365
400
366 not_ramsn_0 <= NOT(memo.ramsn(0));
401 not_ramsn_0 <= NOT(memo.ramsn(0));
367
402
368 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
403 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
369 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
404 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
370 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
405 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
371 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
406 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
372 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
407 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
373 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
408 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
374 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
409 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
375
410
376 async_1Mx16_0: CY7C1061DV33
411 async_1Mx16_0: CY7C1061DV33
377 GENERIC MAP (
412 GENERIC MAP (
378 ADDR_BITS => 20,
413 ADDR_BITS => 20,
379 DATA_BITS => 16,
414 DATA_BITS => 16,
380 depth => 1048576,
415 depth => 1048576,
381 MEM_ARRAY_DEBUG => 32,
416 MEM_ARRAY_DEBUG => 32,
382 TimingInfo => TRUE,
417 TimingInfo => TRUE,
383 TimingChecks => '1')
418 TimingChecks => '1')
384 PORT MAP (
419 PORT MAP (
385 CE1_b => '0',
420 CE1_b => '0',
386 CE2 => nSRAM_CE,
421 CE2 => nSRAM_CE,
387 WE_b => nSRAM_WE,
422 WE_b => nSRAM_WE,
388 OE_b => nSRAM_OE,
423 OE_b => nSRAM_OE,
389 BHE_b => nSRAM_BE1,
424 BHE_b => nSRAM_BE1,
390 BLE_b => nSRAM_BE0,
425 BLE_b => nSRAM_BE0,
391 A => address,
426 A => address,
392 DQ => data(15 DOWNTO 0));
427 DQ => data(15 DOWNTO 0));
393
428
394 async_1Mx16_1: CY7C1061DV33
429 async_1Mx16_1: CY7C1061DV33
395 GENERIC MAP (
430 GENERIC MAP (
396 ADDR_BITS => 20,
431 ADDR_BITS => 20,
397 DATA_BITS => 16,
432 DATA_BITS => 16,
398 depth => 1048576,
433 depth => 1048576,
399 MEM_ARRAY_DEBUG => 32,
434 MEM_ARRAY_DEBUG => 32,
400 TimingInfo => TRUE,
435 TimingInfo => TRUE,
401 TimingChecks => '1')
436 TimingChecks => '1')
402 PORT MAP (
437 PORT MAP (
403 CE1_b => '0',
438 CE1_b => '0',
404 CE2 => nSRAM_CE,
439 CE2 => nSRAM_CE,
405 WE_b => nSRAM_WE,
440 WE_b => nSRAM_WE,
406 OE_b => nSRAM_OE,
441 OE_b => nSRAM_OE,
407 BHE_b => nSRAM_BE3,
442 BHE_b => nSRAM_BE3,
408 BLE_b => nSRAM_BE2,
443 BLE_b => nSRAM_BE2,
409 A => address,
444 A => address,
410 DQ => data(31 DOWNTO 16));
445 DQ => data(31 DOWNTO 16));
411
446
412
447
413 -----------------------------------------------------------------------------
448 -----------------------------------------------------------------------------
414
449
415 WaveGen_Proc : PROCESS
450 WaveGen_Proc : PROCESS
416 BEGIN
451 BEGIN
417
452
418 -- insert signal assignments here
453 -- insert signal assignments here
419 WAIT UNTIL clk25MHz = '1';
454 WAIT UNTIL clk25MHz = '1';
420 rstn <= '0';
455 rstn <= '0';
421 apbi.psel(15) <= '0';
456 apbi.psel(15) <= '0';
422 apbi.pwrite <= '0';
457 apbi.pwrite <= '0';
423 apbi.penable <= '0';
458 apbi.penable <= '0';
424 apbi.paddr <= (OTHERS => '0');
459 apbi.paddr <= (OTHERS => '0');
425 apbi.pwdata <= (OTHERS => '0');
460 apbi.pwdata <= (OTHERS => '0');
426 fine_time <= (OTHERS => '0');
461 fine_time <= (OTHERS => '0');
427 coarse_time <= (OTHERS => '0');
462 coarse_time <= (OTHERS => '0');
428 WAIT UNTIL clk25MHz = '1';
463 WAIT UNTIL clk25MHz = '1';
429 -- ahbmi.HGRANT(2) <= '1';
464 -- ahbmi.HGRANT(2) <= '1';
430 -- ahbmi.HREADY <= '1';
465 -- ahbmi.HREADY <= '1';
431 -- ahbmi.HRESP <= HRESP_OKAY;
466 -- ahbmi.HRESP <= HRESP_OKAY;
432
467
433 WAIT UNTIL clk25MHz = '1';
468 WAIT UNTIL clk25MHz = '1';
434 WAIT UNTIL clk25MHz = '1';
469 WAIT UNTIL clk25MHz = '1';
435 rstn <= '1';
470 rstn <= '1';
436 WAIT UNTIL clk25MHz = '1';
471 WAIT UNTIL clk25MHz = '1';
437 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000");
472 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000");
438 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000");
473 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000");
439 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000");
474 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000");
440 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000");
475 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000");
441
476
442 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000");
477 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000");
443 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
478 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
444 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
479 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
445 WAIT UNTIL clk25MHz = '1';
480 WAIT UNTIL clk25MHz = '1';
446 ---------------------------------------------------------------------------
481 ---------------------------------------------------------------------------
447 -- CONFIGURATION STEP
482 -- CONFIGURATION STEP
448 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
483 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
449 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
484 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
450 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
485 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
451 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
486 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
452
487
453 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
488 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
454 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
489 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
455 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
490 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
456 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
491 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
457 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
492 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
458
493
459 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
494 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
460 --
495 --
461 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
496 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
462 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
497 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
463 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
498 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
464
499
465
500
466 WAIT UNTIL clk25MHz = '1';
501 WAIT UNTIL clk25MHz = '1';
467 WAIT UNTIL clk25MHz = '1';
502 WAIT UNTIL clk25MHz = '1';
468
503
469
504
470 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
505 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
471 WAIT UNTIL clk25MHz = '1';
506 WAIT UNTIL clk25MHz = '1';
472 WAIT UNTIL clk25MHz = '1';
507 WAIT UNTIL clk25MHz = '1';
473 WAIT UNTIL clk25MHz = '1';
508 WAIT UNTIL clk25MHz = '1';
474 WAIT UNTIL clk25MHz = '1';
509 WAIT UNTIL clk25MHz = '1';
475 WAIT UNTIL clk25MHz = '1';
510 WAIT UNTIL clk25MHz = '1';
476 WAIT UNTIL clk25MHz = '1';
511 WAIT UNTIL clk25MHz = '1';
477 WAIT FOR 1 us;
512 WAIT FOR 1 us;
478 coarse_time <= X"00000001";
513 coarse_time <= X"00000001";
479 ---------------------------------------------------------------------------
514 ---------------------------------------------------------------------------
480 -- RUN STEP
515 -- RUN STEP
481 WAIT FOR 200 ms;
516 WAIT FOR 200 ms;
482 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
517 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
483 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
518 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
484 WAIT FOR 10 us;
519 WAIT FOR 10 us;
485 WAIT UNTIL clk25MHz = '1';
520 WAIT UNTIL clk25MHz = '1';
486 WAIT UNTIL clk25MHz = '1';
521 WAIT UNTIL clk25MHz = '1';
487 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
522 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
488 WAIT UNTIL clk25MHz = '1';
523 WAIT UNTIL clk25MHz = '1';
489 coarse_time <= X"00000010";
524 coarse_time <= X"00000010";
490 WAIT FOR 100 ms;
525 WAIT FOR 100 ms;
491 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
526 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
492 WAIT FOR 10 us;
527 WAIT FOR 10 us;
493 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
528 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
494 WAIT FOR 200 ms;
529 WAIT FOR 200 ms;
495 REPORT "*** END simulation ***" SEVERITY failure;
530 REPORT "*** END simulation ***" SEVERITY failure;
496
531
497
532
498 WAIT;
533 WAIT;
499
534
500 END PROCESS WaveGen_Proc;
535 END PROCESS WaveGen_Proc;
501 -----------------------------------------------------------------------------
536 -----------------------------------------------------------------------------
502
537
503 -----------------------------------------------------------------------------
538 -----------------------------------------------------------------------------
504 -- IRQ
539 -- IRQ
505 -----------------------------------------------------------------------------
540 -----------------------------------------------------------------------------
506 PROCESS (clk25MHz, rstn)
541 PROCESS (clk25MHz, rstn)
507 BEGIN -- PROCESS
542 BEGIN -- PROCESS
508 IF rstn = '0' THEN -- asynchronous reset (active low)
543 IF rstn = '0' THEN -- asynchronous reset (active low)
509
544
510 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
545 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
511
546
512 END IF;
547 END IF;
513 END PROCESS;
548 END PROCESS;
514 -----------------------------------------------------------------------------
549 -----------------------------------------------------------------------------
515
550
516 END;
551 END;
Show file before | Show file after | Hide comments
@@ -1,580 +1,580
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
245 I00_s <= NOT I00_s ;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 pirq => 12,
313 pirq => 12,
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk49_152MHz => clk_24, -- 49.152MHz/2
317 clk49_152MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"000103") -- aa.bb.cc version
428 top_lfr_version => X"000104") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh; No newline at end of file
580 END beh;
Show file before | Show file after | Hide comments
@@ -1,769 +1,764
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr;
106 END lpp_lfr;
107
107
108 ARCHITECTURE beh OF lpp_lfr IS
108 ARCHITECTURE beh OF lpp_lfr IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- DEBUG
263 -- DEBUG
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 --
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 -- MS
281 -- MS
282 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
283
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
291 SIGNAL run_ms : STD_LOGIC;
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
290
299
291 BEGIN
300 BEGIN
292
301
293 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
294 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
295
304
296 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
297 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
298 END GENERATE all_channel;
307 END GENERATE all_channel;
299
308
300 -----------------------------------------------------------------------------
309 -----------------------------------------------------------------------------
301 lpp_lfr_filter_1 : lpp_lfr_filter
310 lpp_lfr_filter_1 : lpp_lfr_filter
302 GENERIC MAP (
311 GENERIC MAP (
303 Mem_use => Mem_use)
312 Mem_use => Mem_use)
304 PORT MAP (
313 PORT MAP (
305 sample => sample_s,
314 sample => sample_s,
306 sample_val => sample_val,
315 sample_val => sample_val,
307 clk => clk,
316 clk => clk,
308 rstn => rstn,
317 rstn => rstn,
309 data_shaping_SP0 => data_shaping_SP0,
318 data_shaping_SP0 => data_shaping_SP0,
310 data_shaping_SP1 => data_shaping_SP1,
319 data_shaping_SP1 => data_shaping_SP1,
311 data_shaping_R0 => data_shaping_R0,
320 data_shaping_R0 => data_shaping_R0,
312 data_shaping_R1 => data_shaping_R1,
321 data_shaping_R1 => data_shaping_R1,
313 sample_f0_val => sample_f0_val,
322 sample_f0_val => sample_f0_val,
314 sample_f1_val => sample_f1_val,
323 sample_f1_val => sample_f1_val,
315 sample_f2_val => sample_f2_val,
324 sample_f2_val => sample_f2_val,
316 sample_f3_val => sample_f3_val,
325 sample_f3_val => sample_f3_val,
317 sample_f0_wdata => sample_f0_data,
326 sample_f0_wdata => sample_f0_data,
318 sample_f1_wdata => sample_f1_data,
327 sample_f1_wdata => sample_f1_data,
319 sample_f2_wdata => sample_f2_data,
328 sample_f2_wdata => sample_f2_data,
320 sample_f3_wdata => sample_f3_data);
329 sample_f3_wdata => sample_f3_data);
321
330
322 -----------------------------------------------------------------------------
331 -----------------------------------------------------------------------------
323 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
324 GENERIC MAP (
333 GENERIC MAP (
325 nb_data_by_buffer_size => nb_data_by_buffer_size,
334 nb_data_by_buffer_size => nb_data_by_buffer_size,
326 nb_word_by_buffer_size => nb_word_by_buffer_size,
335 nb_word_by_buffer_size => nb_word_by_buffer_size,
327 nb_snapshot_param_size => nb_snapshot_param_size,
336 nb_snapshot_param_size => nb_snapshot_param_size,
328 delta_vector_size => delta_vector_size,
337 delta_vector_size => delta_vector_size,
329 delta_vector_size_f0_2 => delta_vector_size_f0_2,
338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
330 pindex => pindex,
339 pindex => pindex,
331 paddr => paddr,
340 paddr => paddr,
332 pmask => pmask,
341 pmask => pmask,
333 pirq_ms => pirq_ms,
342 pirq_ms => pirq_ms,
334 pirq_wfp => pirq_wfp,
343 pirq_wfp => pirq_wfp,
335 top_lfr_version => top_lfr_version)
344 top_lfr_version => top_lfr_version)
336 PORT MAP (
345 PORT MAP (
337 HCLK => clk,
346 HCLK => clk,
338 HRESETn => rstn,
347 HRESETn => rstn,
339 apbi => apbi,
348 apbi => apbi,
340 apbo => apbo,
349 apbo => apbo,
350
351 run_ms => run_ms,
352
341 ready_matrix_f0_0 => ready_matrix_f0_0,
353 ready_matrix_f0_0 => ready_matrix_f0_0,
342 ready_matrix_f0_1 => ready_matrix_f0_1,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
343 ready_matrix_f1 => ready_matrix_f1,
355 ready_matrix_f1 => ready_matrix_f1,
344 ready_matrix_f2 => ready_matrix_f2,
356 ready_matrix_f2 => ready_matrix_f2,
345 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
346 error_bad_component_error => error_bad_component_error,
358 error_bad_component_error => error_bad_component_error,
347 debug_reg => debug_reg,
359 debug_reg => debug_reg,
348 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
349 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
350 status_ready_matrix_f1 => status_ready_matrix_f1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
351 status_ready_matrix_f2 => status_ready_matrix_f2,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
352 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
353 status_error_bad_component_error => status_error_bad_component_error,
365 status_error_bad_component_error => status_error_bad_component_error,
354 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
355 config_active_interruption_onError => config_active_interruption_onError,
367 config_active_interruption_onError => config_active_interruption_onError,
356 addr_matrix_f0_0 => addr_matrix_f0_0,
368
357 addr_matrix_f0_1 => addr_matrix_f0_1,
369 matrix_time_f0_0 => matrix_time_f0_0,
358 addr_matrix_f1 => addr_matrix_f1,
370 matrix_time_f0_1 => matrix_time_f0_1,
359 addr_matrix_f2 => addr_matrix_f2,
371 matrix_time_f1 => matrix_time_f1,
360 status_full => status_full,
372 matrix_time_f2 => matrix_time_f2,
361 status_full_ack => status_full_ack,
373
362 status_full_err => status_full_err,
374 addr_matrix_f0_0 => addr_matrix_f0_0,
363 status_new_err => status_new_err,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
364 data_shaping_BW => data_shaping_BW,
376 addr_matrix_f1 => addr_matrix_f1,
365 data_shaping_SP0 => data_shaping_SP0,
377 addr_matrix_f2 => addr_matrix_f2,
366 data_shaping_SP1 => data_shaping_SP1,
378 status_full => status_full,
367 data_shaping_R0 => data_shaping_R0,
379 status_full_ack => status_full_ack,
368 data_shaping_R1 => data_shaping_R1,
380 status_full_err => status_full_err,
369 delta_snapshot => delta_snapshot,
381 status_new_err => status_new_err,
370 delta_f0 => delta_f0,
382 data_shaping_BW => data_shaping_BW,
371 delta_f0_2 => delta_f0_2,
383 data_shaping_SP0 => data_shaping_SP0,
372 delta_f1 => delta_f1,
384 data_shaping_SP1 => data_shaping_SP1,
373 delta_f2 => delta_f2,
385 data_shaping_R0 => data_shaping_R0,
374 nb_data_by_buffer => nb_data_by_buffer,
386 data_shaping_R1 => data_shaping_R1,
375 nb_word_by_buffer => nb_word_by_buffer,
387 delta_snapshot => delta_snapshot,
376 nb_snapshot_param => nb_snapshot_param,
388 delta_f0 => delta_f0,
377 enable_f0 => enable_f0,
389 delta_f0_2 => delta_f0_2,
378 enable_f1 => enable_f1,
390 delta_f1 => delta_f1,
379 enable_f2 => enable_f2,
391 delta_f2 => delta_f2,
380 enable_f3 => enable_f3,
392 nb_data_by_buffer => nb_data_by_buffer,
381 burst_f0 => burst_f0,
393 nb_word_by_buffer => nb_word_by_buffer,
382 burst_f1 => burst_f1,
394 nb_snapshot_param => nb_snapshot_param,
383 burst_f2 => burst_f2,
395 enable_f0 => enable_f0,
384 run => run,
396 enable_f1 => enable_f1,
385 addr_data_f0 => addr_data_f0,
397 enable_f2 => enable_f2,
386 addr_data_f1 => addr_data_f1,
398 enable_f3 => enable_f3,
387 addr_data_f2 => addr_data_f2,
399 burst_f0 => burst_f0,
388 addr_data_f3 => addr_data_f3,
400 burst_f1 => burst_f1,
389 start_date => start_date,
401 burst_f2 => burst_f2,
402 run => run,
403 addr_data_f0 => addr_data_f0,
404 addr_data_f1 => addr_data_f1,
405 addr_data_f2 => addr_data_f2,
406 addr_data_f3 => addr_data_f3,
407 start_date => start_date,
390 ---------------------------------------------------------------------------
408 ---------------------------------------------------------------------------
391 debug_reg0 => debug_reg0,
409 debug_reg0 => debug_reg0,
392 debug_reg1 => debug_reg1,
410 debug_reg1 => debug_reg1,
393 debug_reg2 => debug_reg2,
411 debug_reg2 => debug_reg2,
394 debug_reg3 => debug_reg3,
412 debug_reg3 => debug_reg3,
395 debug_reg4 => debug_reg4,
413 debug_reg4 => debug_reg4,
396 debug_reg5 => debug_reg5,
414 debug_reg5 => debug_reg5,
397 debug_reg6 => debug_reg6,
415 debug_reg6 => debug_reg6,
398 debug_reg7 => debug_reg7);
416 debug_reg7 => debug_reg7);
399
417
400 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
401 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
402 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
403 -----------------------------------------------------------------------------
421 -----------------------------------------------------------------------------
404 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
405 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
406 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
407 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
408
426
409
427
410 -----------------------------------------------------------------------------
428 -----------------------------------------------------------------------------
411 lpp_waveform_1 : lpp_waveform
429 lpp_waveform_1 : lpp_waveform
412 GENERIC MAP (
430 GENERIC MAP (
413 tech => inferred,
431 tech => inferred,
414 data_size => 6*16,
432 data_size => 6*16,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
433 nb_data_by_buffer_size => nb_data_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
434 nb_word_by_buffer_size => nb_word_by_buffer_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
435 nb_snapshot_param_size => nb_snapshot_param_size,
418 delta_vector_size => delta_vector_size,
436 delta_vector_size => delta_vector_size,
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
437 delta_vector_size_f0_2 => delta_vector_size_f0_2
420 )
438 )
421 PORT MAP (
439 PORT MAP (
422 clk => clk,
440 clk => clk,
423 rstn => rstn,
441 rstn => rstn,
424
442
425 reg_run => run,
443 reg_run => run,
426 reg_start_date => start_date,
444 reg_start_date => start_date,
427 reg_delta_snapshot => delta_snapshot,
445 reg_delta_snapshot => delta_snapshot,
428 reg_delta_f0 => delta_f0,
446 reg_delta_f0 => delta_f0,
429 reg_delta_f0_2 => delta_f0_2,
447 reg_delta_f0_2 => delta_f0_2,
430 reg_delta_f1 => delta_f1,
448 reg_delta_f1 => delta_f1,
431 reg_delta_f2 => delta_f2,
449 reg_delta_f2 => delta_f2,
432
450
433 enable_f0 => enable_f0,
451 enable_f0 => enable_f0,
434 enable_f1 => enable_f1,
452 enable_f1 => enable_f1,
435 enable_f2 => enable_f2,
453 enable_f2 => enable_f2,
436 enable_f3 => enable_f3,
454 enable_f3 => enable_f3,
437 burst_f0 => burst_f0,
455 burst_f0 => burst_f0,
438 burst_f1 => burst_f1,
456 burst_f1 => burst_f1,
439 burst_f2 => burst_f2,
457 burst_f2 => burst_f2,
440
458
441 nb_data_by_buffer => nb_data_by_buffer,
459 nb_data_by_buffer => nb_data_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
460 nb_word_by_buffer => nb_word_by_buffer,
443 nb_snapshot_param => nb_snapshot_param,
461 nb_snapshot_param => nb_snapshot_param,
444 status_full => status_full,
462 status_full => status_full,
445 status_full_ack => status_full_ack,
463 status_full_ack => status_full_ack,
446 status_full_err => status_full_err,
464 status_full_err => status_full_err,
447 status_new_err => status_new_err,
465 status_new_err => status_new_err,
448
466
449 coarse_time => coarse_time,
467 coarse_time => coarse_time,
450 fine_time => fine_time,
468 fine_time => fine_time,
451
469
452 --f0
470 --f0
453 addr_data_f0 => addr_data_f0,
471 addr_data_f0 => addr_data_f0,
454 data_f0_in_valid => sample_f0_val,
472 data_f0_in_valid => sample_f0_val,
455 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
456 --f1
474 --f1
457 addr_data_f1 => addr_data_f1,
475 addr_data_f1 => addr_data_f1,
458 data_f1_in_valid => sample_f1_val,
476 data_f1_in_valid => sample_f1_val,
459 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
460 --f2
478 --f2
461 addr_data_f2 => addr_data_f2,
479 addr_data_f2 => addr_data_f2,
462 data_f2_in_valid => sample_f2_val,
480 data_f2_in_valid => sample_f2_val,
463 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
464 --f3
482 --f3
465 addr_data_f3 => addr_data_f3,
483 addr_data_f3 => addr_data_f3,
466 data_f3_in_valid => sample_f3_val,
484 data_f3_in_valid => sample_f3_val,
467 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
468 -- OUTPUT -- DMA interface
486 -- OUTPUT -- DMA interface
469 --f0
487 --f0
470 data_f0_addr_out => data_f0_addr_out_s,
488 data_f0_addr_out => data_f0_addr_out_s,
471 data_f0_data_out => data_f0_data_out,
489 data_f0_data_out => data_f0_data_out,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
490 data_f0_data_out_valid => data_f0_data_out_valid_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
474 data_f0_data_out_ren => data_f0_data_out_ren,
492 data_f0_data_out_ren => data_f0_data_out_ren,
475 --f1
493 --f1
476 data_f1_addr_out => data_f1_addr_out_s,
494 data_f1_addr_out => data_f1_addr_out_s,
477 data_f1_data_out => data_f1_data_out,
495 data_f1_data_out => data_f1_data_out,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
496 data_f1_data_out_valid => data_f1_data_out_valid_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
480 data_f1_data_out_ren => data_f1_data_out_ren,
498 data_f1_data_out_ren => data_f1_data_out_ren,
481 --f2
499 --f2
482 data_f2_addr_out => data_f2_addr_out_s,
500 data_f2_addr_out => data_f2_addr_out_s,
483 data_f2_data_out => data_f2_data_out,
501 data_f2_data_out => data_f2_data_out,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
502 data_f2_data_out_valid => data_f2_data_out_valid_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
486 data_f2_data_out_ren => data_f2_data_out_ren,
504 data_f2_data_out_ren => data_f2_data_out_ren,
487 --f3
505 --f3
488 data_f3_addr_out => data_f3_addr_out_s,
506 data_f3_addr_out => data_f3_addr_out_s,
489 data_f3_data_out => data_f3_data_out,
507 data_f3_data_out => data_f3_data_out,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
508 data_f3_data_out_valid => data_f3_data_out_valid_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
510 data_f3_data_out_ren => data_f3_data_out_ren ,
493
511
494 -------------------------------------------------------------------------
512 -------------------------------------------------------------------------
495 observation_reg => OPEN --observation_reg
513 observation_reg => OPEN
496 ---- debug SNAPSHOT_OUT
497 --debug_f0_data => debug_f0_data,
498 --debug_f0_data_valid => debug_f0_data_valid ,
499 --debug_f1_data => debug_f1_data ,
500 --debug_f1_data_valid => debug_f1_data_valid,
501 --debug_f2_data => debug_f2_data ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
503 --debug_f3_data => debug_f3_data ,
504 --debug_f3_data_valid => debug_f3_data_valid,
505
506 ---- debug FIFO_IN
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
515
514
516 );
515 );
517
516
518
517
519 -----------------------------------------------------------------------------
518 -----------------------------------------------------------------------------
520 -- DEBUG -- WFP OUT
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
529 -----------------------------------------------------------------------------
530
531
532 -----------------------------------------------------------------------------
533 -- TEMP
519 -- TEMP
534 -----------------------------------------------------------------------------
520 -----------------------------------------------------------------------------
535
521
536 PROCESS (clk, rstn)
522 PROCESS (clk, rstn)
537 BEGIN -- PROCESS
523 BEGIN -- PROCESS
538 IF rstn = '0' THEN -- asynchronous reset (active low)
524 IF rstn = '0' THEN -- asynchronous reset (active low)
539 data_f0_data_out_valid <= '0';
525 data_f0_data_out_valid <= '0';
540 data_f0_data_out_valid_burst <= '0';
526 data_f0_data_out_valid_burst <= '0';
541 data_f1_data_out_valid <= '0';
527 data_f1_data_out_valid <= '0';
542 data_f1_data_out_valid_burst <= '0';
528 data_f1_data_out_valid_burst <= '0';
543 data_f2_data_out_valid <= '0';
529 data_f2_data_out_valid <= '0';
544 data_f2_data_out_valid_burst <= '0';
530 data_f2_data_out_valid_burst <= '0';
545 data_f3_data_out_valid <= '0';
531 data_f3_data_out_valid <= '0';
546 data_f3_data_out_valid_burst <= '0';
532 data_f3_data_out_valid_burst <= '0';
547 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
548 data_f0_data_out_valid <= data_f0_data_out_valid_s;
534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
549 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
550 data_f1_data_out_valid <= data_f1_data_out_valid_s;
536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
551 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
552 data_f2_data_out_valid <= data_f2_data_out_valid_s;
538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
553 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
554 data_f3_data_out_valid <= data_f3_data_out_valid_s;
540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
555 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
556 END IF;
542 END IF;
557 END PROCESS;
543 END PROCESS;
558
544
559 data_f0_addr_out <= data_f0_addr_out_s;
545 data_f0_addr_out <= data_f0_addr_out_s;
560 data_f1_addr_out <= data_f1_addr_out_s;
546 data_f1_addr_out <= data_f1_addr_out_s;
561 data_f2_addr_out <= data_f2_addr_out_s;
547 data_f2_addr_out <= data_f2_addr_out_s;
562 data_f3_addr_out <= data_f3_addr_out_s;
548 data_f3_addr_out <= data_f3_addr_out_s;
563
549
564 -----------------------------------------------------------------------------
550 -----------------------------------------------------------------------------
565 -- RoundRobin Selection For DMA
551 -- RoundRobin Selection For DMA
566 -----------------------------------------------------------------------------
552 -----------------------------------------------------------------------------
567
553
568 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
569 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
570 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
571 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
572
558
573 RR_Arbiter_4_1 : RR_Arbiter_4
559 RR_Arbiter_4_1 : RR_Arbiter_4
574 PORT MAP (
560 PORT MAP (
575 clk => clk,
561 clk => clk,
576 rstn => rstn,
562 rstn => rstn,
577 in_valid => dma_rr_valid,
563 in_valid => dma_rr_valid,
578 out_grant => dma_rr_grant_s);
564 out_grant => dma_rr_grant_s);
579
565
580 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
581 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
582 dma_rr_valid_ms(2) <= '0';
568 dma_rr_valid_ms(2) <= '0';
583 dma_rr_valid_ms(3) <= '0';
569 dma_rr_valid_ms(3) <= '0';
584
570
585 RR_Arbiter_4_2 : RR_Arbiter_4
571 RR_Arbiter_4_2 : RR_Arbiter_4
586 PORT MAP (
572 PORT MAP (
587 clk => clk,
573 clk => clk,
588 rstn => rstn,
574 rstn => rstn,
589 in_valid => dma_rr_valid_ms,
575 in_valid => dma_rr_valid_ms,
590 out_grant => dma_rr_grant_ms);
576 out_grant => dma_rr_grant_ms);
591
577
592 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
593
579
594
580
595 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
596 -- in : dma_rr_grant
582 -- in : dma_rr_grant
597 -- send
583 -- send
598 -- out : dma_sel
584 -- out : dma_sel
599 -- dma_valid_burst
585 -- dma_valid_burst
600 -- dma_sel_valid
586 -- dma_sel_valid
601 -----------------------------------------------------------------------------
587 -----------------------------------------------------------------------------
602 PROCESS (clk, rstn)
588 PROCESS (clk, rstn)
603 BEGIN -- PROCESS
589 BEGIN -- PROCESS
604 IF rstn = '0' THEN -- asynchronous reset (active low)
590 IF rstn = '0' THEN -- asynchronous reset (active low)
605 dma_sel <= (OTHERS => '0');
591 dma_sel <= (OTHERS => '0');
606 dma_send <= '0';
592 dma_send <= '0';
607 dma_valid_burst <= '0';
593 dma_valid_burst <= '0';
608 data_ms_done <= '0';
594 data_ms_done <= '0';
609 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
610 IF run = '1' THEN
596 IF run = '1' THEN
611 data_ms_done <= '0';
597 data_ms_done <= '0';
612 IF dma_sel = "00000" OR dma_done = '1' THEN
598 IF dma_sel = "00000" OR dma_done = '1' THEN
613 dma_sel <= dma_rr_grant;
599 dma_sel <= dma_rr_grant;
614 IF dma_rr_grant(0) = '1' THEN
600 IF dma_rr_grant(0) = '1' THEN
615 dma_send <= '1';
601 dma_send <= '1';
616 dma_valid_burst <= data_f0_data_out_valid_burst;
602 dma_valid_burst <= data_f0_data_out_valid_burst;
617 dma_sel_valid <= data_f0_data_out_valid;
603 dma_sel_valid <= data_f0_data_out_valid;
618 ELSIF dma_rr_grant(1) = '1' THEN
604 ELSIF dma_rr_grant(1) = '1' THEN
619 dma_send <= '1';
605 dma_send <= '1';
620 dma_valid_burst <= data_f1_data_out_valid_burst;
606 dma_valid_burst <= data_f1_data_out_valid_burst;
621 dma_sel_valid <= data_f1_data_out_valid;
607 dma_sel_valid <= data_f1_data_out_valid;
622 ELSIF dma_rr_grant(2) = '1' THEN
608 ELSIF dma_rr_grant(2) = '1' THEN
623 dma_send <= '1';
609 dma_send <= '1';
624 dma_valid_burst <= data_f2_data_out_valid_burst;
610 dma_valid_burst <= data_f2_data_out_valid_burst;
625 dma_sel_valid <= data_f2_data_out_valid;
611 dma_sel_valid <= data_f2_data_out_valid;
626 ELSIF dma_rr_grant(3) = '1' THEN
612 ELSIF dma_rr_grant(3) = '1' THEN
627 dma_send <= '1';
613 dma_send <= '1';
628 dma_valid_burst <= data_f3_data_out_valid_burst;
614 dma_valid_burst <= data_f3_data_out_valid_burst;
629 dma_sel_valid <= data_f3_data_out_valid;
615 dma_sel_valid <= data_f3_data_out_valid;
630 ELSIF dma_rr_grant(4) = '1' THEN
616 ELSIF dma_rr_grant(4) = '1' THEN
631 dma_send <= '1';
617 dma_send <= '1';
632 dma_valid_burst <= data_ms_valid_burst;
618 dma_valid_burst <= data_ms_valid_burst;
633 dma_sel_valid <= data_ms_valid;
619 dma_sel_valid <= data_ms_valid;
634 END IF;
620 END IF;
635
621
636 IF dma_sel(4) = '1' THEN
622 IF dma_sel(4) = '1' THEN
637 data_ms_done <= '1';
623 data_ms_done <= '1';
638 END IF;
624 END IF;
639 ELSE
625 ELSE
640 dma_sel <= dma_sel;
626 dma_sel <= dma_sel;
641 dma_send <= '0';
627 dma_send <= '0';
642 END IF;
628 END IF;
643 ELSE
629 ELSE
644 data_ms_done <= '0';
630 data_ms_done <= '0';
645 dma_sel <= (OTHERS => '0');
631 dma_sel <= (OTHERS => '0');
646 dma_send <= '0';
632 dma_send <= '0';
647 dma_valid_burst <= '0';
633 dma_valid_burst <= '0';
648 END IF;
634 END IF;
649 END IF;
635 END IF;
650 END PROCESS;
636 END PROCESS;
651
637
652
638
653 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
654 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
655 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
656 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
657 data_ms_addr;
643 data_ms_addr;
658
644
659 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
660 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
661 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
662 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
663 data_ms_data;
649 data_ms_data;
664
650
665 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
666 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
667 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
668 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
669 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
670
656
671 dma_data_2 <= dma_data;
657 dma_data_2 <= dma_data;
672
658
673
659
674
660
675
661
676
662
677 -----------------------------------------------------------------------------
663 -----------------------------------------------------------------------------
678 -- DEBUG -- DMA IN
664 -- DEBUG -- DMA IN
679 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
665 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
680 --debug_f0_data_dma_in <= dma_data;
666 --debug_f0_data_dma_in <= dma_data;
681 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
667 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
682 --debug_f1_data_dma_in <= dma_data;
668 --debug_f1_data_dma_in <= dma_data;
683 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
669 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
684 --debug_f2_data_dma_in <= dma_data;
670 --debug_f2_data_dma_in <= dma_data;
685 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
671 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
686 --debug_f3_data_dma_in <= dma_data;
672 --debug_f3_data_dma_in <= dma_data;
687 -----------------------------------------------------------------------------
673 -----------------------------------------------------------------------------
688
674
689 -----------------------------------------------------------------------------
675 -----------------------------------------------------------------------------
690 -- DMA
676 -- DMA
691 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
692 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
678 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
693 GENERIC MAP (
679 GENERIC MAP (
694 tech => inferred,
680 tech => inferred,
695 hindex => hindex)
681 hindex => hindex)
696 PORT MAP (
682 PORT MAP (
697 HCLK => clk,
683 HCLK => clk,
698 HRESETn => rstn,
684 HRESETn => rstn,
699 run => run,
685 run => run,
700 AHB_Master_In => ahbi,
686 AHB_Master_In => ahbi,
701 AHB_Master_Out => ahbo,
687 AHB_Master_Out => ahbo,
702
688
703 send => dma_send,
689 send => dma_send,
704 valid_burst => dma_valid_burst,
690 valid_burst => dma_valid_burst,
705 done => dma_done,
691 done => dma_done,
706 ren => dma_ren,
692 ren => dma_ren,
707 address => dma_address,
693 address => dma_address,
708 data => dma_data_2);
694 data => dma_data_2);
709
695
710 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
711 -- Matrix Spectral
697 -- Matrix Spectral
712 -----------------------------------------------------------------------------
698 -----------------------------------------------------------------------------
713 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
699 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
714 NOT(sample_f0_val) & NOT(sample_f0_val) ;
700 NOT(sample_f0_val) & NOT(sample_f0_val);
715 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
701 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
716 NOT(sample_f1_val) & NOT(sample_f1_val) ;
702 NOT(sample_f1_val) & NOT(sample_f1_val);
717 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
703 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
718 NOT(sample_f3_val) & NOT(sample_f3_val) ;
704 NOT(sample_f3_val) & NOT(sample_f3_val);
719
705
720 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
706 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
721 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
707 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
722 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
708 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
723
709
724 -------------------------------------------------------------------------------
710 -------------------------------------------------------------------------------
725 lpp_lfr_ms_1: lpp_lfr_ms
711
712 ms_softandhard_rstn <= rstn AND run_ms AND run;
713
714 -----------------------------------------------------------------------------
715 lpp_lfr_ms_1 : lpp_lfr_ms
726 GENERIC MAP (
716 GENERIC MAP (
727 Mem_use => Mem_use )
717 Mem_use => Mem_use)
728 PORT MAP (
718 PORT MAP (
729 clk => clk,
719 clk => clk,
730 rstn => rstn,
720 rstn => ms_softandhard_rstn, --rstn,
731
721
732 coarse_time => coarse_time,
722 coarse_time => coarse_time,
733 fine_time => fine_time,
723 fine_time => fine_time,
734
735 sample_f0_wen => sample_f0_wen,
736 sample_f0_wdata => sample_f0_wdata,
737 sample_f1_wen => sample_f1_wen,
738 sample_f1_wdata => sample_f1_wdata,
739 sample_f3_wen => sample_f3_wen,
740 sample_f3_wdata => sample_f3_wdata,
741
724
742 dma_addr => data_ms_addr, --
725 sample_f0_wen => sample_f0_wen,
743 dma_data => data_ms_data, --
726 sample_f0_wdata => sample_f0_wdata,
744 dma_valid => data_ms_valid, --
727 sample_f1_wen => sample_f1_wen,
745 dma_valid_burst => data_ms_valid_burst, --
728 sample_f1_wdata => sample_f1_wdata,
746 dma_ren => data_ms_ren, --
729 sample_f3_wen => sample_f3_wen,
747 dma_done => data_ms_done, --
730 sample_f3_wdata => sample_f3_wdata,
731
732 dma_addr => data_ms_addr, --
733 dma_data => data_ms_data, --
734 dma_valid => data_ms_valid, --
735 dma_valid_burst => data_ms_valid_burst, --
736 dma_ren => data_ms_ren, --
737 dma_done => data_ms_done, --
748
738
749 ready_matrix_f0_0 => ready_matrix_f0_0,
739 ready_matrix_f0_0 => ready_matrix_f0_0,
750 ready_matrix_f0_1 => ready_matrix_f0_1,
740 ready_matrix_f0_1 => ready_matrix_f0_1,
751 ready_matrix_f1 => ready_matrix_f1,
741 ready_matrix_f1 => ready_matrix_f1,
752 ready_matrix_f2 => ready_matrix_f2,
742 ready_matrix_f2 => ready_matrix_f2,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
743 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
754 error_bad_component_error => error_bad_component_error,
744 error_bad_component_error => error_bad_component_error,
755 debug_reg => observation_reg,--debug_reg,
745 debug_reg => observation_reg, --debug_reg,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
746 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
747 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
748 status_ready_matrix_f1 => status_ready_matrix_f1,
759 status_ready_matrix_f2 => status_ready_matrix_f2,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
760 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
750 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
761 status_error_bad_component_error => status_error_bad_component_error,
751 status_error_bad_component_error => status_error_bad_component_error,
762 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
763 config_active_interruption_onError => config_active_interruption_onError,
753 config_active_interruption_onError => config_active_interruption_onError,
764 addr_matrix_f0_0 => addr_matrix_f0_0,
754 addr_matrix_f0_0 => addr_matrix_f0_0,
765 addr_matrix_f0_1 => addr_matrix_f0_1,
755 addr_matrix_f0_1 => addr_matrix_f0_1,
766 addr_matrix_f1 => addr_matrix_f1,
756 addr_matrix_f1 => addr_matrix_f1,
767 addr_matrix_f2 => addr_matrix_f2);
757 addr_matrix_f2 => addr_matrix_f2,
768
758
759 matrix_time_f0_0 => matrix_time_f0_0,
760 matrix_time_f0_1 => matrix_time_f0_1,
761 matrix_time_f1 => matrix_time_f1,
762 matrix_time_f2 => matrix_time_f2);
763
769 END beh;
764 END beh;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 -- IN
62 run_ms : OUT STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
63 -- IN
64 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f0_0 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f0_1 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
68 error_anticipating_empty_fifo : IN STD_LOGIC;
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 error_bad_component_error : IN STD_LOGIC;
70
70 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 -- OUT
71
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 -- OUT
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_0 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f0_1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f1 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_ready_matrix_f2 : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
78
78 status_error_bad_component_error : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79
80 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 config_active_interruption_onError : OUT STD_LOGIC;
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 ---------------------------------------------------------------------------
86 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 -- WaveForm picker Reg
87
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92
92
93 -- OUT
93 ---------------------------------------------------------------------------
94 data_shaping_BW : OUT STD_LOGIC;
94 ---------------------------------------------------------------------------
95 data_shaping_SP0 : OUT STD_LOGIC;
95 -- WaveForm picker Reg
96 data_shaping_SP1 : OUT STD_LOGIC;
96 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 data_shaping_R0 : OUT STD_LOGIC;
97 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
98 data_shaping_R1 : OUT STD_LOGIC;
98 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99
99 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 -- OUT
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC;
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 data_shaping_SP0 : OUT STD_LOGIC;
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 data_shaping_SP1 : OUT STD_LOGIC;
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
105 data_shaping_R0 : OUT STD_LOGIC;
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
106 data_shaping_R1 : OUT STD_LOGIC;
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
107
108
108 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
109 enable_f0 : OUT STD_LOGIC;
109 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 enable_f1 : OUT STD_LOGIC;
110 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
111 enable_f2 : OUT STD_LOGIC;
111 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 enable_f3 : OUT STD_LOGIC;
112 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113
113 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
114 burst_f0 : OUT STD_LOGIC;
114 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
115 burst_f1 : OUT STD_LOGIC;
115 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
116 burst_f2 : OUT STD_LOGIC;
116
117
117 enable_f0 : OUT STD_LOGIC;
118 run : OUT STD_LOGIC;
118 enable_f1 : OUT STD_LOGIC;
119
119 enable_f2 : OUT STD_LOGIC;
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 enable_f3 : OUT STD_LOGIC;
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 burst_f0 : OUT STD_LOGIC;
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 burst_f1 : OUT STD_LOGIC;
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
124 burst_f2 : OUT STD_LOGIC;
125 ---------------------------------------------------------------------------
125
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 run : OUT STD_LOGIC;
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
133 ---------------------------------------------------------------------------
134
134 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 ---------------------------------------------------------------------------
135 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 );
136 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137
137 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 END lpp_lfr_apbreg;
138 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139
139 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141
141 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
142 CONSTANT REVISION : INTEGER := 1;
142
143
143 ---------------------------------------------------------------------------
144 CONSTANT pconfig : apb_config_type := (
144 );
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
145
146 1 => apb_iobar(paddr, pmask));
146 END lpp_lfr_apbreg;
147
147
148 TYPE lpp_SpectralMatrix_regs IS RECORD
148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
149 config_active_interruption_onNewMatrix : STD_LOGIC;
149
150 config_active_interruption_onError : STD_LOGIC;
150 CONSTANT REVISION : INTEGER := 1;
151 status_ready_matrix_f0_0 : STD_LOGIC;
151
152 status_ready_matrix_f0_1 : STD_LOGIC;
152 CONSTANT pconfig : apb_config_type := (
153 status_ready_matrix_f1 : STD_LOGIC;
153 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
154 status_ready_matrix_f2 : STD_LOGIC;
154 1 => apb_iobar(paddr, pmask));
155 status_error_anticipating_empty_fifo : STD_LOGIC;
155
156 status_error_bad_component_error : STD_LOGIC;
156 TYPE lpp_SpectralMatrix_regs IS RECORD
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 config_active_interruption_onNewMatrix : STD_LOGIC;
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 config_active_interruption_onError : STD_LOGIC;
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 config_ms_run : STD_LOGIC;
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 status_ready_matrix_f0_0 : STD_LOGIC;
161 END RECORD;
161 status_ready_matrix_f0_1 : STD_LOGIC;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
162 status_ready_matrix_f1 : STD_LOGIC;
163
163 status_ready_matrix_f2 : STD_LOGIC;
164 TYPE lpp_WaveformPicker_regs IS RECORD
164 status_error_anticipating_empty_fifo : STD_LOGIC;
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 status_error_bad_component_error : STD_LOGIC;
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 data_shaping_BW : STD_LOGIC;
168 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 data_shaping_SP0 : STD_LOGIC;
169 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 data_shaping_SP1 : STD_LOGIC;
170
171 data_shaping_R0 : STD_LOGIC;
171 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 data_shaping_R1 : STD_LOGIC;
172 coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
175
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
176 fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
178 fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
179 fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
180 END RECORD;
181 enable_f0 : STD_LOGIC;
181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 enable_f1 : STD_LOGIC;
182
183 enable_f2 : STD_LOGIC;
183 TYPE lpp_WaveformPicker_regs IS RECORD
184 enable_f3 : STD_LOGIC;
184 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 burst_f0 : STD_LOGIC;
185 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 burst_f1 : STD_LOGIC;
186 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 burst_f2 : STD_LOGIC;
187 data_shaping_BW : STD_LOGIC;
188 run : STD_LOGIC;
188 data_shaping_SP0 : STD_LOGIC;
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 data_shaping_SP1 : STD_LOGIC;
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 data_shaping_R0 : STD_LOGIC;
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 data_shaping_R1 : STD_LOGIC;
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
193 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 END RECORD;
194 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
195 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196
196 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
198
198 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
199 -----------------------------------------------------------------------------
199 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
200 -- IRQ
200 enable_f0 : STD_LOGIC;
201 -----------------------------------------------------------------------------
201 enable_f1 : STD_LOGIC;
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
202 enable_f2 : STD_LOGIC;
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
203 enable_f3 : STD_LOGIC;
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 burst_f0 : STD_LOGIC;
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 burst_f1 : STD_LOGIC;
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 burst_f2 : STD_LOGIC;
207 SIGNAL ored_irq_wfp : STD_LOGIC;
207 run : STD_LOGIC;
208
208 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 BEGIN -- beh
209 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
210
210 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
211 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
212 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
213 END RECORD;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
214 SIGNAL reg_wp : lpp_WaveformPicker_regs;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
215
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
216 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
217
217
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
218 -----------------------------------------------------------------------------
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
219 -- IRQ
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
220 -----------------------------------------------------------------------------
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
221 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
222 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
223 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
224
224 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225
225 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
226 SIGNAL ored_irq_wfp : STD_LOGIC;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
227
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
228 BEGIN -- beh
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
229
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
230 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
231
231 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
232 delta_snapshot <= reg_wp.delta_snapshot;
232 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
233 delta_f0 <= reg_wp.delta_f0;
233 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
234 delta_f0_2 <= reg_wp.delta_f0_2;
234 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
235 delta_f1 <= reg_wp.delta_f1;
235 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
236 delta_f2 <= reg_wp.delta_f2;
236
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
237 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
238 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
239 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
240
240 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
241 enable_f0 <= reg_wp.enable_f0;
241 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
242 enable_f1 <= reg_wp.enable_f1;
242 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
243 enable_f2 <= reg_wp.enable_f2;
243
244 enable_f3 <= reg_wp.enable_f3;
244
245
245 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
246 burst_f0 <= reg_wp.burst_f0;
246 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
247 burst_f1 <= reg_wp.burst_f1;
247 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
248 burst_f2 <= reg_wp.burst_f2;
248 data_shaping_R0 <= reg_wp.data_shaping_R0;
249
249 data_shaping_R1 <= reg_wp.data_shaping_R1;
250 run <= reg_wp.run;
250
251
251 delta_snapshot <= reg_wp.delta_snapshot;
252 addr_data_f0 <= reg_wp.addr_data_f0;
252 delta_f0 <= reg_wp.delta_f0;
253 addr_data_f1 <= reg_wp.addr_data_f1;
253 delta_f0_2 <= reg_wp.delta_f0_2;
254 addr_data_f2 <= reg_wp.addr_data_f2;
254 delta_f1 <= reg_wp.delta_f1;
255 addr_data_f3 <= reg_wp.addr_data_f3;
255 delta_f2 <= reg_wp.delta_f2;
256
256 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
257 start_date <= reg_wp.start_date;
257 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
258
258 nb_snapshot_param <= reg_wp.nb_snapshot_param;
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
259
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
260 enable_f0 <= reg_wp.enable_f0;
261 BEGIN -- PROCESS lpp_dma_top
261 enable_f1 <= reg_wp.enable_f1;
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
262 enable_f2 <= reg_wp.enable_f2;
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
263 enable_f3 <= reg_wp.enable_f3;
264 reg_sp.config_active_interruption_onError <= '0';
264
265 reg_sp.status_ready_matrix_f0_0 <= '0';
265 burst_f0 <= reg_wp.burst_f0;
266 reg_sp.status_ready_matrix_f0_1 <= '0';
266 burst_f1 <= reg_wp.burst_f1;
267 reg_sp.status_ready_matrix_f1 <= '0';
267 burst_f2 <= reg_wp.burst_f2;
268 reg_sp.status_ready_matrix_f2 <= '0';
268
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
269 run <= reg_wp.run;
270 reg_sp.status_error_bad_component_error <= '0';
270
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
271 addr_data_f0 <= reg_wp.addr_data_f0;
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
272 addr_data_f1 <= reg_wp.addr_data_f1;
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
273 addr_data_f2 <= reg_wp.addr_data_f2;
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
274 addr_data_f3 <= reg_wp.addr_data_f3;
275 prdata <= (OTHERS => '0');
275
276
276 start_date <= reg_wp.start_date;
277 apbo.pirq <= (OTHERS => '0');
277
278
278 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
279 status_full_ack <= (OTHERS => '0');
279 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
280
280 BEGIN -- PROCESS lpp_dma_top
281 reg_wp.data_shaping_BW <= '0';
281 IF HRESETn = '0' THEN -- asynchronous reset (active low)
282 reg_wp.data_shaping_SP0 <= '0';
282 reg_sp.config_active_interruption_onNewMatrix <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
283 reg_sp.config_active_interruption_onError <= '0';
284 reg_wp.data_shaping_R0 <= '0';
284 reg_sp.config_ms_run <= '1';
285 reg_wp.data_shaping_R1 <= '0';
285 reg_sp.status_ready_matrix_f0_0 <= '0';
286 reg_wp.enable_f0 <= '0';
286 reg_sp.status_ready_matrix_f0_1 <= '0';
287 reg_wp.enable_f1 <= '0';
287 reg_sp.status_ready_matrix_f1 <= '0';
288 reg_wp.enable_f2 <= '0';
288 reg_sp.status_ready_matrix_f2 <= '0';
289 reg_wp.enable_f3 <= '0';
289 reg_sp.status_error_anticipating_empty_fifo <= '0';
290 reg_wp.burst_f0 <= '0';
290 reg_sp.status_error_bad_component_error <= '0';
291 reg_wp.burst_f1 <= '0';
291 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
292 reg_wp.burst_f2 <= '0';
292 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
293 reg_wp.run <= '0';
293 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
294 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
295
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
296 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
300 reg_sp.fine_time_f0_0 <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
301 reg_sp.fine_time_f0_1 <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
302 reg_sp.fine_time_f1 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
303 reg_sp.fine_time_f2 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
304
305 reg_wp.delta_f2 <= (OTHERS => '0');
305 prdata <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
306
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
307 apbo.pirq <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
308
309
309 status_full_ack <= (OTHERS => '0');
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
310
311 status_full_ack <= (OTHERS => '0');
311 reg_wp.data_shaping_BW <= '0';
312
312 reg_wp.data_shaping_SP0 <= '0';
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
313 reg_wp.data_shaping_SP1 <= '0';
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
314 reg_wp.data_shaping_R0 <= '0';
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
315 reg_wp.data_shaping_R1 <= '0';
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
316 reg_wp.enable_f0 <= '0';
317
317 reg_wp.enable_f1 <= '0';
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
318 reg_wp.enable_f2 <= '0';
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
319 reg_wp.enable_f3 <= '0';
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
320 reg_wp.burst_f0 <= '0';
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
321 reg_wp.burst_f1 <= '0';
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
322 reg_wp.burst_f2 <= '0';
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
323 reg_wp.run <= '0';
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
324 reg_wp.addr_data_f0 <= (OTHERS => '0');
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
325 reg_wp.addr_data_f1 <= (OTHERS => '0');
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
326 reg_wp.addr_data_f2 <= (OTHERS => '0');
327 END LOOP all_status;
327 reg_wp.addr_data_f3 <= (OTHERS => '0');
328
328 reg_wp.status_full <= (OTHERS => '0');
329 paddr := "000000";
329 reg_wp.status_full_err <= (OTHERS => '0');
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
330 reg_wp.status_new_err <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
331 reg_wp.delta_snapshot <= (OTHERS => '0');
332 IF apbi.psel(pindex) = '1' THEN
332 reg_wp.delta_f0 <= (OTHERS => '0');
333 -- APB DMA READ --
333 reg_wp.delta_f0_2 <= (OTHERS => '0');
334 CASE paddr(7 DOWNTO 2) IS
334 reg_wp.delta_f1 <= (OTHERS => '0');
335 --
335 reg_wp.delta_f2 <= (OTHERS => '0');
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
336 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
337 prdata(1) <= reg_sp.config_active_interruption_onError;
337 reg_wp.nb_snapshot_param <= (OTHERS => '0');
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
338 reg_wp.start_date <= (OTHERS => '0');
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
339
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
340 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
341
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
342 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
343 prdata(5) <= reg_sp.status_error_bad_component_error;
343 reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
346
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
347 reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
348 WHEN "000110" => prdata <= debug_reg;
348 reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
349 --
349 reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
350 reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
351 prdata(1) <= reg_wp.data_shaping_SP0;
351
352 prdata(2) <= reg_wp.data_shaping_SP1;
352 status_full_ack <= (OTHERS => '0');
353 prdata(3) <= reg_wp.data_shaping_R0;
353
354 prdata(4) <= reg_wp.data_shaping_R1;
354 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
355 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
356 prdata(1) <= reg_wp.enable_f1;
356 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
357 prdata(2) <= reg_wp.enable_f2;
357 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
358 prdata(3) <= reg_wp.enable_f3;
358
359 prdata(4) <= reg_wp.burst_f0;
359 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
360 prdata(5) <= reg_wp.burst_f1;
360 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
361 prdata(6) <= reg_wp.burst_f2;
361 all_status: FOR I IN 3 DOWNTO 0 LOOP
362 prdata(7) <= reg_wp.run;
362 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
363 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
364 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
365 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
366 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
367 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
368 END LOOP all_status;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
369
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
370 paddr := "000000";
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
371 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
372 prdata <= (OTHERS => '0');
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
373 IF apbi.psel(pindex) = '1' THEN
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
374 -- APB DMA READ --
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
375 CASE paddr(7 DOWNTO 2) IS
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
376 --
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
377 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
378 prdata(1) <= reg_sp.config_active_interruption_onError;
379 ----------------------------------------------------
379 prdata(2) <= reg_sp.config_ms_run;
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
380 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
381 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
382 prdata(2) <= reg_sp.status_ready_matrix_f1;
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
383 prdata(3) <= reg_sp.status_ready_matrix_f2;
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
384 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
385 prdata(5) <= reg_sp.status_error_bad_component_error;
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
386 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
387 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
388 ----------------------------------------------------
388 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
389 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
389 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
390 WHEN OTHERS => NULL;
390
391 END CASE;
391 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
393 -- APB DMA WRITE --
393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
394 CASE paddr(7 DOWNTO 2) IS
394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
395 --
395 WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0;
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
396 WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1;
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
397 WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1;
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
398 WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2;
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
399
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
400 WHEN "001111" => prdata <= debug_reg;
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
401 ---------------------------------------------------------------------
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
402 WHEN "010000" => prdata(0) <= reg_wp.data_shaping_BW;
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
403 prdata(1) <= reg_wp.data_shaping_SP0;
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
404 prdata(2) <= reg_wp.data_shaping_SP1;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
405 prdata(3) <= reg_wp.data_shaping_R0;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
406 prdata(4) <= reg_wp.data_shaping_R1;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
407 WHEN "010001" => prdata(0) <= reg_wp.enable_f0;
408 --
408 prdata(1) <= reg_wp.enable_f1;
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
409 prdata(2) <= reg_wp.enable_f2;
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
410 prdata(3) <= reg_wp.enable_f3;
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
411 prdata(4) <= reg_wp.burst_f0;
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
412 prdata(5) <= reg_wp.burst_f1;
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
413 prdata(6) <= reg_wp.burst_f2;
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
414 prdata(7) <= reg_wp.run;
415 reg_wp.enable_f1 <= apbi.pwdata(1);
415 WHEN "010010" => prdata <= reg_wp.addr_data_f0;
416 reg_wp.enable_f2 <= apbi.pwdata(2);
416 WHEN "010011" => prdata <= reg_wp.addr_data_f1;
417 reg_wp.enable_f3 <= apbi.pwdata(3);
417 WHEN "010100" => prdata <= reg_wp.addr_data_f2;
418 reg_wp.burst_f0 <= apbi.pwdata(4);
418 WHEN "010101" => prdata <= reg_wp.addr_data_f3;
419 reg_wp.burst_f1 <= apbi.pwdata(5);
419 WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
420 reg_wp.burst_f2 <= apbi.pwdata(6);
420 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
421 reg_wp.run <= apbi.pwdata(7);
421 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
422 WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
423 WHEN "011000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
424 WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
425 WHEN "011010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
426 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
427 WHEN "011100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
428 WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
429 WHEN "011110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
430 WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
431 ----------------------------------------------------
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
432 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
433 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
435 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
436 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
438 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
439 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
440 ----------------------------------------------------
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
441 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
442 --
442 WHEN OTHERS => NULL;
443 WHEN OTHERS => NULL;
443
444 END CASE;
444 END CASE;
445 END IF;
445 IF (apbi.pwrite AND apbi.penable) = '1' THEN
446 END IF;
446 -- APB DMA WRITE --
447
447 CASE paddr(7 DOWNTO 2) IS
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
448 --
449 ready_matrix_f0_1 OR
449 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
450 ready_matrix_f1 OR
450 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
451 ready_matrix_f2)
451 reg_sp.config_ms_run <= apbi.pwdata(2);
452 )
452 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
453 OR
453 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
454 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
455 error_bad_component_error)
455 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
456 ));
456 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
457
457 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
458 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
459 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
460 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
461 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
462 -- );
462 --
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
463 WHEN "010000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
464
464 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
465 END IF;
465 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
466 END PROCESS lpp_lfr_apbreg;
466 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
467
467 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
468 apbo.pindex <= pindex;
468 WHEN "010001" => reg_wp.enable_f0 <= apbi.pwdata(0);
469 apbo.pconfig <= pconfig;
469 reg_wp.enable_f1 <= apbi.pwdata(1);
470 apbo.prdata <= prdata;
470 reg_wp.enable_f2 <= apbi.pwdata(2);
471
471 reg_wp.enable_f3 <= apbi.pwdata(3);
472 -----------------------------------------------------------------------------
472 reg_wp.burst_f0 <= apbi.pwdata(4);
473 -- IRQ
473 reg_wp.burst_f1 <= apbi.pwdata(5);
474 -----------------------------------------------------------------------------
474 reg_wp.burst_f2 <= apbi.pwdata(6);
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
475 reg_wp.run <= apbi.pwdata(7);
476
476 WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata;
477 PROCESS (HCLK, HRESETn)
477 WHEN "010011" => reg_wp.addr_data_f1 <= apbi.pwdata;
478 BEGIN -- PROCESS
478 WHEN "010100" => reg_wp.addr_data_f2 <= apbi.pwdata;
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
479 WHEN "010101" => reg_wp.addr_data_f3 <= apbi.pwdata;
480 irq_wfp_reg <= (OTHERS => '0');
480 WHEN "010110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
481 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
482 irq_wfp_reg <= irq_wfp_reg_s;
482 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
483 END IF;
483 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
484 END PROCESS;
484 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
485
485 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
486 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
487 WHEN "010111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
488 END GENERATE all_irq_wfp;
488 WHEN "011000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
489
489 WHEN "011001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
490 irq_wfp_ZERO <= (OTHERS => '0');
490 WHEN "011010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
491 WHEN "011011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
492
492 WHEN "011100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
493 END beh;
493 WHEN "011101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
494 WHEN "011110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
495 WHEN "011111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
496 --
497 WHEN OTHERS => NULL;
498 END CASE;
499 END IF;
500 END IF;
501
502 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
503 ready_matrix_f0_1 OR
504 ready_matrix_f1 OR
505 ready_matrix_f2)
506 )
507 OR
508 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
509 error_bad_component_error)
510 ));
511
512 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
513
514 END IF;
515 END PROCESS lpp_lfr_apbreg;
516
517 apbo.pindex <= pindex;
518 apbo.pconfig <= pconfig;
519 apbo.prdata <= prdata;
520
521 -----------------------------------------------------------------------------
522 -- IRQ
523 -----------------------------------------------------------------------------
524 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
525
526 PROCESS (HCLK, HRESETn)
527 BEGIN -- PROCESS
528 IF HRESETn = '0' THEN -- asynchronous reset (active low)
529 irq_wfp_reg <= (OTHERS => '0');
530 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
531 irq_wfp_reg <= irq_wfp_reg_s;
532 END IF;
533 END PROCESS;
534
535 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
536 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
537 END GENERATE all_irq_wfp;
538
539 irq_wfp_ZERO <= (OTHERS => '0');
540 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
541
542 run_ms <= reg_sp.config_ms_run;
543
544 END beh;
Show file before | Show file after | Hide comments
@@ -1,402 +1,414
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 --USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 --USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
21
21
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
27
27
28
28
29 ENTITY lpp_lfr_ms IS
29 ENTITY lpp_lfr_ms IS
30 GENERIC (
30 GENERIC (
31 Mem_use : INTEGER
31 Mem_use : INTEGER
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36
37 ---------------------------------------------------------------------------
37 ---------------------------------------------------------------------------
38 -- DATA INPUT
38 -- DATA INPUT
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 -- TIME
40 -- TIME
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
43 --
43 --
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
46 --
46 --
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 --
49 --
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52
52
53 ---------------------------------------------------------------------------
53 ---------------------------------------------------------------------------
54 -- DMA
54 -- DMA
55 ---------------------------------------------------------------------------
55 ---------------------------------------------------------------------------
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_valid : OUT STD_LOGIC;
58 dma_valid : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
62
62
63 -- Reg out
63 -- Reg out
64 ready_matrix_f0_0 : OUT STD_LOGIC;
64 ready_matrix_f0_0 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71
71
72 -- Reg In
72 -- Reg In
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
91
86 );
92 );
87 END;
93 END;
88
94
89 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
95 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
90 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
91 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
100 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
95 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
96 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
97
103
98 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
99 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
105 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
100 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
108 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
103
109
104 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
105 SIGNAL FFT_Load : STD_LOGIC;
111 SIGNAL FFT_Load : STD_LOGIC;
106 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
115 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
110
116
111 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
112 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
119 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
114
120
115 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
116 SIGNAL SM_FlagError : STD_LOGIC;
122 SIGNAL SM_FlagError : STD_LOGIC;
117 -- SIGNAL SM_Pong : STD_LOGIC;
123 -- SIGNAL SM_Pong : STD_LOGIC;
118 SIGNAL SM_Wen : STD_LOGIC;
124 SIGNAL SM_Wen : STD_LOGIC;
119 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
123 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
129 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
124
130
125 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
126 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
134 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
129
135
130 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
131 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL Head_Empty : STD_LOGIC;
139 SIGNAL Head_Empty : STD_LOGIC;
134 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL Head_Valid : STD_LOGIC;
141 SIGNAL Head_Valid : STD_LOGIC;
136 SIGNAL Head_Val : STD_LOGIC;
142 SIGNAL Head_Val : STD_LOGIC;
137
143
138 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
139 SIGNAL DMA_Read : STD_LOGIC;
145 SIGNAL DMA_Read : STD_LOGIC;
140 SIGNAL DMA_ack : STD_LOGIC;
146 SIGNAL DMA_ack : STD_LOGIC;
141
147
142 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
143 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
149 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
144
150
145 BEGIN
151 BEGIN
146
152
147 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
148 Memf0: lppFIFOxN
154 Memf0: lppFIFOxN
149 GENERIC MAP (
155 GENERIC MAP (
150 tech => 0, Mem_use => Mem_use, Data_sz => 16,
156 tech => 0, Mem_use => Mem_use, Data_sz => 16,
151 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
157 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
152 PORT MAP (
158 PORT MAP (
153 rstn => rstn, wclk => clk, rclk => clk,
159 rstn => rstn, wclk => clk, rclk => clk,
154 ReUse => (OTHERS => '0'),
160 ReUse => (OTHERS => '0'),
155 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
161 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
156 wdata => sample_f0_wdata, rdata => FifoF0_Data,
162 wdata => sample_f0_wdata, rdata => FifoF0_Data,
157 full => OPEN, empty => FifoF0_Empty);
163 full => OPEN, empty => FifoF0_Empty);
158
164
159 Memf1: lppFIFOxN
165 Memf1: lppFIFOxN
160 GENERIC MAP (
166 GENERIC MAP (
161 tech => 0, Mem_use => Mem_use, Data_sz => 16,
167 tech => 0, Mem_use => Mem_use, Data_sz => 16,
162 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
168 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
163 PORT MAP (
169 PORT MAP (
164 rstn => rstn, wclk => clk, rclk => clk,
170 rstn => rstn, wclk => clk, rclk => clk,
165 ReUse => (OTHERS => '0'),
171 ReUse => (OTHERS => '0'),
166 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
172 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
167 wdata => sample_f1_wdata, rdata => FifoF1_Data,
173 wdata => sample_f1_wdata, rdata => FifoF1_Data,
168 full => OPEN, empty => FifoF1_Empty);
174 full => OPEN, empty => FifoF1_Empty);
169
175
170
176
171 Memf2: lppFIFOxN
177 Memf2: lppFIFOxN
172 GENERIC MAP (
178 GENERIC MAP (
173 tech => 0, Mem_use => Mem_use, Data_sz => 16,
179 tech => 0, Mem_use => Mem_use, Data_sz => 16,
174 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
180 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
175 PORT MAP (
181 PORT MAP (
176 rstn => rstn, wclk => clk, rclk => clk,
182 rstn => rstn, wclk => clk, rclk => clk,
177 ReUse => (OTHERS => '0'),
183 ReUse => (OTHERS => '0'),
178 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
184 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
179 wdata => sample_f3_wdata, rdata => FifoF3_Data,
185 wdata => sample_f3_wdata, rdata => FifoF3_Data,
180 full => OPEN, empty => FifoF3_Empty);
186 full => OPEN, empty => FifoF3_Empty);
181 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
182
188
183
189
184 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
185 DMUX0 : DEMUX
191 DMUX0 : DEMUX
186 GENERIC MAP (
192 GENERIC MAP (
187 Data_sz => 16)
193 Data_sz => 16)
188 PORT MAP (
194 PORT MAP (
189 clk => clk,
195 clk => clk,
190 rstn => rstn,
196 rstn => rstn,
191 Read => FFT_Read,
197 Read => FFT_Read,
192 Load => FFT_Load,
198 Load => FFT_Load,
193 EmptyF0 => FifoF0_Empty,
199 EmptyF0 => FifoF0_Empty,
194 EmptyF1 => FifoF1_Empty,
200 EmptyF1 => FifoF1_Empty,
195 EmptyF2 => FifoF3_Empty,
201 EmptyF2 => FifoF3_Empty,
196 DataF0 => FifoF0_Data,
202 DataF0 => FifoF0_Data,
197 DataF1 => FifoF1_Data,
203 DataF1 => FifoF1_Data,
198 DataF2 => FifoF3_Data,
204 DataF2 => FifoF3_Data,
199 WorkFreq => DMUX_WorkFreq,
205 WorkFreq => DMUX_WorkFreq,
200 Read_DEMUX => DMUX_Read,
206 Read_DEMUX => DMUX_Read,
201 Empty => DMUX_Empty,
207 Empty => DMUX_Empty,
202 Data => DMUX_Data);
208 Data => DMUX_Data);
203 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
204
210
205
211
206 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
207 FFT0: FFT
213 FFT0: FFT
208 GENERIC MAP (
214 GENERIC MAP (
209 Data_sz => 16,
215 Data_sz => 16,
210 NbData => 256)
216 NbData => 256)
211 PORT MAP (
217 PORT MAP (
212 clkm => clk,
218 clkm => clk,
213 rstn => rstn,
219 rstn => rstn,
214 FifoIN_Empty => DMUX_Empty,
220 FifoIN_Empty => DMUX_Empty,
215 FifoIN_Data => DMUX_Data,
221 FifoIN_Data => DMUX_Data,
216 FifoOUT_Full => FifoINT_Full,
222 FifoOUT_Full => FifoINT_Full,
217 Load => FFT_Load,
223 Load => FFT_Load,
218 Read => FFT_Read,
224 Read => FFT_Read,
219 Write => FFT_Write,
225 Write => FFT_Write,
220 ReUse => FFT_ReUse,
226 ReUse => FFT_ReUse,
221 Data => FFT_Data);
227 Data => FFT_Data);
222 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
223
229
224
230
225 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
226 MemInt : lppFIFOxN
232 MemInt : lppFIFOxN
227 GENERIC MAP (
233 GENERIC MAP (
228 tech => 0,
234 tech => 0,
229 Mem_use => Mem_use,
235 Mem_use => Mem_use,
230 Data_sz => 16,
236 Data_sz => 16,
231 Addr_sz => 8,
237 Addr_sz => 8,
232 FifoCnt => 5,
238 FifoCnt => 5,
233 Enable_ReUse => '1')
239 Enable_ReUse => '1')
234 PORT MAP (
240 PORT MAP (
235 rstn => rstn,
241 rstn => rstn,
236 wclk => clk,
242 wclk => clk,
237 rclk => clk,
243 rclk => clk,
238 ReUse => SM_ReUse,
244 ReUse => SM_ReUse,
239 wen => FFT_Write,
245 wen => FFT_Write,
240 ren => SM_Read,
246 ren => SM_Read,
241 wdata => FFT_Data,
247 wdata => FFT_Data,
242 rdata => FifoINT_Data,
248 rdata => FifoINT_Data,
243 full => FifoINT_Full,
249 full => FifoINT_Full,
244 empty => OPEN);
250 empty => OPEN);
245 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
246
252
247 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
248 SM0 : MatriceSpectrale
254 SM0 : MatriceSpectrale
249 GENERIC MAP (
255 GENERIC MAP (
250 Input_SZ => 16,
256 Input_SZ => 16,
251 Result_SZ => 32)
257 Result_SZ => 32)
252 PORT MAP (
258 PORT MAP (
253 clkm => clk,
259 clkm => clk,
254 rstn => rstn,
260 rstn => rstn,
255 FifoIN_Full => FifoINT_Full,
261 FifoIN_Full => FifoINT_Full,
256 SetReUse => FFT_ReUse,
262 SetReUse => FFT_ReUse,
257 Valid => Head_Valid,
263 Valid => Head_Valid,
258 Data_IN => FifoINT_Data,
264 Data_IN => FifoINT_Data,
259 ACK => DMA_ack,
265 ACK => DMA_ack,
260 SM_Write => SM_Wen,
266 SM_Write => SM_Wen,
261 FlagError => SM_FlagError,
267 FlagError => SM_FlagError,
262 -- Pong => SM_Pong,
268 -- Pong => SM_Pong,
263 Statu => SM_Param,
269 Statu => SM_Param,
264 Write => SM_Write,
270 Write => SM_Write,
265 Read => SM_Read,
271 Read => SM_Read,
266 ReUse => SM_ReUse,
272 ReUse => SM_ReUse,
267 Data_OUT => SM_Data);
273 Data_OUT => SM_Data);
268 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
269
275
270 -----------------------------------------------------------------------------
276 -----------------------------------------------------------------------------
271 MemOut : lppFIFOxN
277 MemOut : lppFIFOxN
272 GENERIC MAP (
278 GENERIC MAP (
273 tech => 0,
279 tech => 0,
274 Mem_use => Mem_use,
280 Mem_use => Mem_use,
275 Data_sz => 32,
281 Data_sz => 32,
276 Addr_sz => 8,
282 Addr_sz => 8,
277 FifoCnt => 2,
283 FifoCnt => 2,
278 Enable_ReUse => '0')
284 Enable_ReUse => '0')
279 PORT MAP (
285 PORT MAP (
280 rstn => rstn,
286 rstn => rstn,
281 wclk => clk,
287 wclk => clk,
282 rclk => clk,
288 rclk => clk,
283 ReUse => (OTHERS => '0'),
289 ReUse => (OTHERS => '0'),
284 wen => SM_Write,
290 wen => SM_Write,
285 ren => Head_Read,
291 ren => Head_Read,
286 wdata => SM_Data,
292 wdata => SM_Data,
287 rdata => FifoOUT_Data,
293 rdata => FifoOUT_Data,
288 full => FifoOUT_Full,
294 full => FifoOUT_Full,
289 empty => FifoOUT_Empty);
295 empty => FifoOUT_Empty);
290 -----------------------------------------------------------------------------
296 -----------------------------------------------------------------------------
291
297
292 -----------------------------------------------------------------------------
298 -----------------------------------------------------------------------------
293 Head0 : HeaderBuilder
299 Head0 : HeaderBuilder
294 GENERIC MAP (
300 GENERIC MAP (
295 Data_sz => 32)
301 Data_sz => 32)
296 PORT MAP (
302 PORT MAP (
297 clkm => clk,
303 clkm => clk,
298 rstn => rstn,
304 rstn => rstn,
299 -- pong => SM_Pong,
305 -- pong => SM_Pong,
300 Statu => SM_Param,
306 Statu => SM_Param,
301 Matrix_Type => DMUX_WorkFreq,
307 Matrix_Type => DMUX_WorkFreq,
302 Matrix_Write => SM_Wen,
308 Matrix_Write => SM_Wen,
303 Valid => Head_Valid,
309 Valid => Head_Valid,
304 dataIN => FifoOUT_Data,
310 dataIN => FifoOUT_Data,
305 emptyIN => FifoOUT_Empty,
311 emptyIN => FifoOUT_Empty,
306 RenOUT => Head_Read,
312 RenOUT => Head_Read,
307 dataOUT => Head_Data,
313 dataOUT => Head_Data,
308 emptyOUT => Head_Empty,
314 emptyOUT => Head_Empty,
309 RenIN => DMA_Read,
315 RenIN => DMA_Read,
310 header => Head_Header,
316 header => Head_Header,
311 header_val => Head_Val,
317 header_val => Head_Val,
312 header_ack => DMA_ack );
318 header_ack => DMA_ack );
313 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
314 data_time(31 DOWNTO 0) <= coarse_time;
320 data_time(31 DOWNTO 0) <= coarse_time;
315 data_time(47 DOWNTO 32) <= fine_time;
321 data_time(47 DOWNTO 32) <= fine_time;
316
322
317 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
323 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
318 PORT MAP (
324 PORT MAP (
319 HCLK => clk,
325 HCLK => clk,
320 HRESETn => rstn,
326 HRESETn => rstn,
321
327
322 data_time => data_time,
328 data_time => data_time,
323
329
324 fifo_data => Head_Data,
330 fifo_data => Head_Data,
325 fifo_empty => Head_Empty,
331 fifo_empty => Head_Empty,
326 fifo_ren => DMA_Read,
332 fifo_ren => DMA_Read,
327
333
328 header => Head_Header,
334 header => Head_Header,
329 header_val => Head_Val,
335 header_val => Head_Val,
330 header_ack => DMA_ack,
336 header_ack => DMA_ack,
331
337
332 dma_addr => dma_addr,
338 dma_addr => dma_addr,
333 dma_data => dma_data,
339 dma_data => dma_data,
334 dma_valid => dma_valid,
340 dma_valid => dma_valid,
335 dma_valid_burst => dma_valid_burst,
341 dma_valid_burst => dma_valid_burst,
336 dma_ren => dma_ren,
342 dma_ren => dma_ren,
337 dma_done => dma_done,
343 dma_done => dma_done,
338
344
339 ready_matrix_f0_0 => ready_matrix_f0_0,
345 ready_matrix_f0_0 => ready_matrix_f0_0,
340 ready_matrix_f0_1 => ready_matrix_f0_1,
346 ready_matrix_f0_1 => ready_matrix_f0_1,
341 ready_matrix_f1 => ready_matrix_f1,
347 ready_matrix_f1 => ready_matrix_f1,
342 ready_matrix_f2 => ready_matrix_f2,
348 ready_matrix_f2 => ready_matrix_f2,
343 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
349 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
344 error_bad_component_error => error_bad_component_error,
350 error_bad_component_error => error_bad_component_error,
345 debug_reg => debug_reg,
351 debug_reg => debug_reg,
346 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
352 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
347 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
353 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
348 status_ready_matrix_f1 => status_ready_matrix_f1,
354 status_ready_matrix_f1 => status_ready_matrix_f1,
349 status_ready_matrix_f2 => status_ready_matrix_f2,
355 status_ready_matrix_f2 => status_ready_matrix_f2,
350 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
356 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
351 status_error_bad_component_error => status_error_bad_component_error,
357 status_error_bad_component_error => status_error_bad_component_error,
352 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
358 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
353 config_active_interruption_onError => config_active_interruption_onError,
359 config_active_interruption_onError => config_active_interruption_onError,
354 addr_matrix_f0_0 => addr_matrix_f0_0,
360 addr_matrix_f0_0 => addr_matrix_f0_0,
355 addr_matrix_f0_1 => addr_matrix_f0_1,
361 addr_matrix_f0_1 => addr_matrix_f0_1,
356 addr_matrix_f1 => addr_matrix_f1,
362 addr_matrix_f1 => addr_matrix_f1,
357 addr_matrix_f2 => addr_matrix_f2);
363 addr_matrix_f2 => addr_matrix_f2,
364
365 matrix_time_f0_0 => matrix_time_f0_0,
366 matrix_time_f0_1 => matrix_time_f0_1,
367 matrix_time_f1 => matrix_time_f1,
368 matrix_time_f2 => matrix_time_f2
369 );
358
370
359
371
360
372
361
373
362 -----------------------------------------------------------------------------
374 -----------------------------------------------------------------------------
363 --lpp_dma_ip_1: lpp_dma_ip
375 --lpp_dma_ip_1: lpp_dma_ip
364 -- GENERIC MAP (
376 -- GENERIC MAP (
365 -- tech => 0,
377 -- tech => 0,
366 -- hindex => hindex)
378 -- hindex => hindex)
367 -- PORT MAP (
379 -- PORT MAP (
368 -- HCLK => clk,
380 -- HCLK => clk,
369 -- HRESETn => rstn,
381 -- HRESETn => rstn,
370 -- AHB_Master_In => AHB_Master_In,
382 -- AHB_Master_In => AHB_Master_In,
371 -- AHB_Master_Out => AHB_Master_Out,
383 -- AHB_Master_Out => AHB_Master_Out,
372
384
373 -- fifo_data => Head_Data,
385 -- fifo_data => Head_Data,
374 -- fifo_empty => Head_Empty,
386 -- fifo_empty => Head_Empty,
375 -- fifo_ren => DMA_Read,
387 -- fifo_ren => DMA_Read,
376
388
377 -- header => Head_Header,
389 -- header => Head_Header,
378 -- header_val => Head_Val,
390 -- header_val => Head_Val,
379 -- header_ack => DMA_ack,
391 -- header_ack => DMA_ack,
380
392
381 -- ready_matrix_f0_0 => ready_matrix_f0_0,
393 -- ready_matrix_f0_0 => ready_matrix_f0_0,
382 -- ready_matrix_f0_1 => ready_matrix_f0_1,
394 -- ready_matrix_f0_1 => ready_matrix_f0_1,
383 -- ready_matrix_f1 => ready_matrix_f1,
395 -- ready_matrix_f1 => ready_matrix_f1,
384 -- ready_matrix_f2 => ready_matrix_f2,
396 -- ready_matrix_f2 => ready_matrix_f2,
385 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
397 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
386 -- error_bad_component_error => error_bad_component_error,
398 -- error_bad_component_error => error_bad_component_error,
387 -- debug_reg => debug_reg,
399 -- debug_reg => debug_reg,
388 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
400 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
389 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
401 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
390 -- status_ready_matrix_f1 => status_ready_matrix_f1,
402 -- status_ready_matrix_f1 => status_ready_matrix_f1,
391 -- status_ready_matrix_f2 => status_ready_matrix_f2,
403 -- status_ready_matrix_f2 => status_ready_matrix_f2,
392 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
404 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
393 -- status_error_bad_component_error => status_error_bad_component_error,
405 -- status_error_bad_component_error => status_error_bad_component_error,
394 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
406 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
395 -- config_active_interruption_onError => config_active_interruption_onError,
407 -- config_active_interruption_onError => config_active_interruption_onError,
396 -- addr_matrix_f0_0 => addr_matrix_f0_0,
408 -- addr_matrix_f0_0 => addr_matrix_f0_0,
397 -- addr_matrix_f0_1 => addr_matrix_f0_1,
409 -- addr_matrix_f0_1 => addr_matrix_f0_1,
398 -- addr_matrix_f1 => addr_matrix_f1,
410 -- addr_matrix_f1 => addr_matrix_f1,
399 -- addr_matrix_f2 => addr_matrix_f2);
411 -- addr_matrix_f2 => addr_matrix_f2);
400 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
401
413
402 END Behavioral;
414 END Behavioral;
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@@ -1,365 +1,383
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
40 USE techmap.gencomp.ALL;
41
41
42
42
43 ENTITY lpp_lfr_ms_fsmdma IS
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
44 PORT (
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 --TIME
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
51
52 -- fifo interface
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
56
57 -- header
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
61
62 -- DMA
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
69
70 -- Reg out
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
78
79 -- Reg In
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
93
98
94 );
99 );
95 END;
100 END;
96
101
97 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
98 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
99 -- SIGNAL DMAIn : DMA_In_Type;
104 -- SIGNAL DMAIn : DMA_In_Type;
100 -- SIGNAL header_dmai : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
101 -- SIGNAL component_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
102 -- SIGNAL DMAOut : DMA_OUt_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
103 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
104
109
105 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
107 TYPE state_DMAWriteBurst IS (IDLE,
112 TYPE state_DMAWriteBurst IS (IDLE,
108 CHECK_COMPONENT_TYPE,
113 CHECK_COMPONENT_TYPE,
109 WRITE_COARSE_TIME,
114 WRITE_COARSE_TIME,
110 WRITE_FINE_TIME,
115 WRITE_FINE_TIME,
111 TRASH_FIFO,
116 TRASH_FIFO,
112 SEND_DATA,
117 SEND_DATA,
113 WAIT_DATA_ACK,
118 WAIT_DATA_ACK,
114 CHECK_LENGTH
119 CHECK_LENGTH
115 );
120 );
116 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
121 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
117
122
118 -- SIGNAL nbSend : INTEGER;
123 -- SIGNAL nbSend : INTEGER;
119 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
122 SIGNAL header_check_ok : STD_LOGIC;
127 SIGNAL header_check_ok : STD_LOGIC;
123 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL send_matrix : STD_LOGIC;
129 SIGNAL send_matrix : STD_LOGIC;
125 -- SIGNAL request : STD_LOGIC;
130 -- SIGNAL request : STD_LOGIC;
126 -- SIGNAL remaining_data_request : INTEGER;
131 -- SIGNAL remaining_data_request : INTEGER;
127 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
130 SIGNAL header_select : STD_LOGIC;
135 SIGNAL header_select : STD_LOGIC;
131
136
132 SIGNAL header_send : STD_LOGIC;
137 SIGNAL header_send : STD_LOGIC;
133 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 SIGNAL header_send_ok : STD_LOGIC;
139 SIGNAL header_send_ok : STD_LOGIC;
135 SIGNAL header_send_ko : STD_LOGIC;
140 SIGNAL header_send_ko : STD_LOGIC;
136
141
137 SIGNAL component_send : STD_LOGIC;
142 SIGNAL component_send : STD_LOGIC;
138 SIGNAL component_send_ok : STD_LOGIC;
143 SIGNAL component_send_ok : STD_LOGIC;
139 SIGNAL component_send_ko : STD_LOGIC;
144 SIGNAL component_send_ko : STD_LOGIC;
140 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
141 SIGNAL fifo_ren_trash : STD_LOGIC;
146 SIGNAL fifo_ren_trash : STD_LOGIC;
142 SIGNAL component_fifo_ren : STD_LOGIC;
147 SIGNAL component_fifo_ren : STD_LOGIC;
143
148
144 -----------------------------------------------------------------------------
149 -----------------------------------------------------------------------------
145 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
147
152
148 BEGIN
153 BEGIN
149
154
150 debug_reg <= debug_reg_s;
155 debug_reg <= debug_reg_s;
151
156
152
157
153 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
158 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
154 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
159 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
155 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
160 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
156 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
161 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
157 '0';
162 '0';
158
163
159 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
164 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
160 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
165 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
161 '1' WHEN component_type = component_type_pre + "0001" ELSE
166 '1' WHEN component_type = component_type_pre + "0001" ELSE
162 '0';
167 '0';
163
168
164 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
169 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
165 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
170 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
166 addr_matrix_f1 WHEN matrix_type = "10" ELSE
171 addr_matrix_f1 WHEN matrix_type = "10" ELSE
167 addr_matrix_f2 WHEN matrix_type = "11" ELSE
172 addr_matrix_f2 WHEN matrix_type = "11" ELSE
168 (OTHERS => '0');
173 (OTHERS => '0');
169
174
170 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
171 -- DMA control
176 -- DMA control
172 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
173 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
178 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
174 BEGIN -- PROCESS DMAWriteBurst_p
179 BEGIN -- PROCESS DMAWriteBurst_p
175 IF HRESETn = '0' THEN -- asynchronous reset (active low)
180 IF HRESETn = '0' THEN -- asynchronous reset (active low)
176 matrix_type <= (OTHERS => '0');
181 matrix_type <= (OTHERS => '0');
177 component_type <= (OTHERS => '0');
182 component_type <= (OTHERS => '0');
178 state <= IDLE;
183 state <= IDLE;
179 header_ack <= '0';
184 header_ack <= '0';
180 ready_matrix_f0_0 <= '0';
185 ready_matrix_f0_0 <= '0';
181 ready_matrix_f0_1 <= '0';
186 ready_matrix_f0_1 <= '0';
182 ready_matrix_f1 <= '0';
187 ready_matrix_f1 <= '0';
183 ready_matrix_f2 <= '0';
188 ready_matrix_f2 <= '0';
184 error_anticipating_empty_fifo <= '0';
189 error_anticipating_empty_fifo <= '0';
185 error_bad_component_error <= '0';
190 error_bad_component_error <= '0';
186 component_type_pre <= "0000";
191 component_type_pre <= "0000";
187 fifo_ren_trash <= '1';
192 fifo_ren_trash <= '1';
188 component_send <= '0';
193 component_send <= '0';
189 address <= (OTHERS => '0');
194 address <= (OTHERS => '0');
190 header_select <= '0';
195 header_select <= '0';
191 header_send <= '0';
196 header_send <= '0';
192 header_data <= (OTHERS => '0');
197 header_data <= (OTHERS => '0');
193 fine_time_reg <= (OTHERS => '0');
198 fine_time_reg <= (OTHERS => '0');
194
199
195 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
200 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
196
201
197 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
202 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
198
203
199 CASE state IS
204 CASE state IS
200 WHEN IDLE =>
205 WHEN IDLE =>
201 debug_reg_s(2 DOWNTO 0) <= "000";
206 debug_reg_s(2 DOWNTO 0) <= "000";
202
207
203 matrix_type <= header(1 DOWNTO 0);
208 matrix_type <= header(1 DOWNTO 0);
204 --component_type <= header(5 DOWNTO 2);
209 --component_type <= header(5 DOWNTO 2);
205
210
206 ready_matrix_f0_0 <= '0';
211 ready_matrix_f0_0 <= '0';
207 ready_matrix_f0_1 <= '0';
212 ready_matrix_f0_1 <= '0';
208 ready_matrix_f1 <= '0';
213 ready_matrix_f1 <= '0';
209 ready_matrix_f2 <= '0';
214 ready_matrix_f2 <= '0';
210 error_bad_component_error <= '0';
215 error_bad_component_error <= '0';
211 header_select <= '1';
216 header_select <= '1';
212 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
217 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
213 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
218 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
214 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
219 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
215
220
216 matrix_type <= header(1 DOWNTO 0);
221 matrix_type <= header(1 DOWNTO 0);
217 component_type <= header(5 DOWNTO 2);
222 component_type <= header(5 DOWNTO 2);
218 component_type_pre <= component_type;
223 component_type_pre <= component_type;
219 state <= CHECK_COMPONENT_TYPE;
224 state <= CHECK_COMPONENT_TYPE;
220 END IF;
225 END IF;
221
226
222 WHEN CHECK_COMPONENT_TYPE =>
227 WHEN CHECK_COMPONENT_TYPE =>
223 debug_reg_s(2 DOWNTO 0) <= "001";
228 debug_reg_s(2 DOWNTO 0) <= "001";
224
229
225 IF header_check_ok = '1' THEN
230 IF header_check_ok = '1' THEN
226 header_ack <= '1';
231 header_ack <= '1';
227 header_send <= '0';
232 header_send <= '0';
228 --
233 --
229 IF component_type = "0000" THEN
234 IF component_type = "0000" THEN
230 address <= address_matrix;
235 address <= address_matrix;
231 state <= WRITE_COARSE_TIME;
236 CASE matrix_type IS
237 WHEN "00" => matrix_time_f0_0 <= data_time;
238 WHEN "01" => matrix_time_f0_1 <= data_time;
239 WHEN "10" => matrix_time_f1 <= data_time;
240 WHEN "11" => matrix_time_f2 <= data_time ;
241 WHEN OTHERS => NULL;
242 END CASE;
243
232 header_data <= data_time(31 DOWNTO 0);
244 header_data <= data_time(31 DOWNTO 0);
233 fine_time_reg <= data_time(47 DOWNTO 32);
245 fine_time_reg <= data_time(47 DOWNTO 32);
234 header_send <= '1';
246 --state <= WRITE_COARSE_TIME;
247 --header_send <= '1';
248 state <= SEND_DATA;
249 header_send <= '0';
250 component_send <= '1';
251 header_select <= '0';
235 ELSE
252 ELSE
236 state <= SEND_DATA;
253 state <= SEND_DATA;
237 END IF;
254 END IF;
238 --
255 --
239 ELSE
256 ELSE
240 error_bad_component_error <= '1';
257 error_bad_component_error <= '1';
241 component_type_pre <= "0000";
258 component_type_pre <= "0000";
242 header_ack <= '1';
259 header_ack <= '1';
243 state <= TRASH_FIFO;
260 state <= TRASH_FIFO;
244 END IF;
261 END IF;
245
262
246 WHEN WRITE_COARSE_TIME =>
263 WHEN WRITE_COARSE_TIME =>
247 debug_reg_s(2 DOWNTO 0) <= "010";
264 debug_reg_s(2 DOWNTO 0) <= "010";
248
265
249 header_ack <= '0';
266 header_ack <= '0';
250
267
251 IF dma_ren = '0' THEN
268 IF dma_ren = '0' THEN
252 header_send <= '0';
269 header_send <= '0';
253 ELSE
270 ELSE
254 header_send <= header_send;
271 header_send <= header_send;
255 END IF;
272 END IF;
256
273
257
274
258 IF header_send_ko = '1' THEN
275 IF header_send_ko = '1' THEN
259 header_send <= '0';
276 header_send <= '0';
260 state <= TRASH_FIFO;
277 state <= TRASH_FIFO;
261 error_anticipating_empty_fifo <= '1';
278 error_anticipating_empty_fifo <= '1';
262 -- TODO : error sending header
279 -- TODO : error sending header
263 ELSIF header_send_ok = '1' THEN
280 ELSIF header_send_ok = '1' THEN
264 header_send <= '1';
281 header_send <= '1';
265 header_select <= '1';
282 header_select <= '1';
266 header_data(15 DOWNTO 0) <= fine_time_reg;
283 header_data(15 DOWNTO 0) <= fine_time_reg;
267 header_data(31 DOWNTO 16) <= (OTHERS => '0');
284 header_data(31 DOWNTO 16) <= (OTHERS => '0');
268 state <= WRITE_FINE_TIME;
285 state <= WRITE_FINE_TIME;
269 address <= address + 4;
286 address <= address + 4;
270 END IF;
287 END IF;
271
288
272
289
273 WHEN WRITE_FINE_TIME =>
290 WHEN WRITE_FINE_TIME =>
274 debug_reg_s(2 DOWNTO 0) <= "011";
291 debug_reg_s(2 DOWNTO 0) <= "011";
275
292
276 header_ack <= '0';
293 header_ack <= '0';
277 header_ack <= '0';
278
294
279 IF dma_ren = '0' THEN
295 IF dma_ren = '0' THEN
280 header_send <= '0';
296 header_send <= '0';
281 ELSE
297 ELSE
282 header_send <= header_send;
298 header_send <= header_send;
283 END IF;
299 END IF;
284
300
285 IF header_send_ko = '1' THEN
301 IF header_send_ko = '1' THEN
286 header_send <= '0';
302 header_send <= '0';
287 state <= TRASH_FIFO;
303 state <= TRASH_FIFO;
288 error_anticipating_empty_fifo <= '1';
304 error_anticipating_empty_fifo <= '1';
289 -- TODO : error sending header
305 -- TODO : error sending header
290 ELSIF header_send_ok = '1' THEN
306 ELSIF header_send_ok = '1' THEN
291 header_send <= '0';
307 header_send <= '0';
292 header_select <= '0';
308 header_select <= '0';
293 state <= SEND_DATA;
309 state <= SEND_DATA;
294 address <= address + 4;
310 address <= address + 4;
295 END IF;
311 END IF;
296
312
297 WHEN TRASH_FIFO =>
313 WHEN TRASH_FIFO =>
298 debug_reg_s(2 DOWNTO 0) <= "100";
314 debug_reg_s(2 DOWNTO 0) <= "100";
299
315
300 header_ack <= '0';
316 header_ack <= '0';
301 error_bad_component_error <= '0';
317 error_bad_component_error <= '0';
302 error_anticipating_empty_fifo <= '0';
318 error_anticipating_empty_fifo <= '0';
303 IF fifo_empty = '1' THEN
319 IF fifo_empty = '1' THEN
304 state <= IDLE;
320 state <= IDLE;
305 fifo_ren_trash <= '1';
321 fifo_ren_trash <= '1';
306 ELSE
322 ELSE
307 fifo_ren_trash <= '0';
323 fifo_ren_trash <= '0';
308 END IF;
324 END IF;
309
325
310 WHEN SEND_DATA =>
326 WHEN SEND_DATA =>
327 header_ack <= '0';
311 debug_reg_s(2 DOWNTO 0) <= "101";
328 debug_reg_s(2 DOWNTO 0) <= "101";
312
329
313 IF fifo_empty = '1' THEN
330 IF fifo_empty = '1' THEN
314 state <= IDLE;
331 state <= IDLE;
315 IF component_type = "1110" THEN --"1110" -- JC
332 IF component_type = "1110" THEN --"1110" -- JC
316 CASE matrix_type IS
333 CASE matrix_type IS
317 WHEN "00" => ready_matrix_f0_0 <= '1';
334 WHEN "00" => ready_matrix_f0_0 <= '1';
318 WHEN "01" => ready_matrix_f0_1 <= '1';
335 WHEN "01" => ready_matrix_f0_1 <= '1';
319 WHEN "10" => ready_matrix_f1 <= '1';
336 WHEN "10" => ready_matrix_f1 <= '1';
320 WHEN "11" => ready_matrix_f2 <= '1';
337 WHEN "11" => ready_matrix_f2 <= '1';
321 WHEN OTHERS => NULL;
338 WHEN OTHERS => NULL;
322 END CASE;
339 END CASE;
323
340
324 END IF;
341 END IF;
325 ELSE
342 ELSE
326 component_send <= '1';
343 component_send <= '1';
327 address <= address;
344 address <= address;
328 state <= WAIT_DATA_ACK;
345 state <= WAIT_DATA_ACK;
329 END IF;
346 END IF;
330
347
331 WHEN WAIT_DATA_ACK =>
348 WHEN WAIT_DATA_ACK =>
332 debug_reg_s(2 DOWNTO 0) <= "110";
349 debug_reg_s(2 DOWNTO 0) <= "110";
333
350
334 component_send <= '0';
351 component_send <= '0';
335 IF component_send_ok = '1' THEN
352 IF component_send_ok = '1' THEN
336 address <= address + 64;
353 address <= address + 64;
337 state <= SEND_DATA;
354 state <= SEND_DATA;
338 ELSIF component_send_ko = '1' THEN
355 ELSIF component_send_ko = '1' THEN
339 error_anticipating_empty_fifo <= '0';
356 error_anticipating_empty_fifo <= '0';
340 state <= TRASH_FIFO;
357 state <= TRASH_FIFO;
341 END IF;
358 END IF;
342
359
343 WHEN CHECK_LENGTH =>
360 WHEN CHECK_LENGTH =>
361 component_send <= '0';
344 debug_reg_s(2 DOWNTO 0) <= "111";
362 debug_reg_s(2 DOWNTO 0) <= "111";
345 state <= IDLE;
363 state <= IDLE;
346
364
347 WHEN OTHERS => NULL;
365 WHEN OTHERS => NULL;
348 END CASE;
366 END CASE;
349
367
350 END IF;
368 END IF;
351 END PROCESS DMAWriteFSM_p;
369 END PROCESS DMAWriteFSM_p;
352
370
353 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
371 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
354 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
372 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
355 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
373 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
356 dma_addr <= address;
374 dma_addr <= address;
357 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
375 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
358
376
359 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
377 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
360 component_send_ko <= '0';
378 component_send_ko <= '0';
361
379
362 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
380 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
363 header_send_ko <= '0';
381 header_send_ko <= '0';
364
382
365 END Behavioral;
383 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,263 +1,287
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER
19 Mem_use : INTEGER
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27
27
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34
34
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 dma_valid : OUT STD_LOGIC;
37 dma_valid : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
41
41
42 ready_matrix_f0_0 : OUT STD_LOGIC;
42 ready_matrix_f0_0 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61
62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
61 END COMPONENT;
66 END COMPONENT;
62
67
63 COMPONENT lpp_lfr_ms_fsmdma
68 COMPONENT lpp_lfr_ms_fsmdma
64 PORT (
69 PORT (
65 HCLK : IN STD_ULOGIC;
70 HCLK : IN STD_ULOGIC;
66 HRESETn : IN STD_ULOGIC;
71 HRESETn : IN STD_ULOGIC;
67 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
72 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
68 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 fifo_empty : IN STD_LOGIC;
74 fifo_empty : IN STD_LOGIC;
70 fifo_ren : OUT STD_LOGIC;
75 fifo_ren : OUT STD_LOGIC;
71 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 header_val : IN STD_LOGIC;
77 header_val : IN STD_LOGIC;
73 header_ack : OUT STD_LOGIC;
78 header_ack : OUT STD_LOGIC;
74 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 dma_valid : OUT STD_LOGIC;
81 dma_valid : OUT STD_LOGIC;
77 dma_valid_burst : OUT STD_LOGIC;
82 dma_valid_burst : OUT STD_LOGIC;
78 dma_ren : IN STD_LOGIC;
83 dma_ren : IN STD_LOGIC;
79 dma_done : IN STD_LOGIC;
84 dma_done : IN STD_LOGIC;
80 ready_matrix_f0_0 : OUT STD_LOGIC;
85 ready_matrix_f0_0 : OUT STD_LOGIC;
81 ready_matrix_f0_1 : OUT STD_LOGIC;
86 ready_matrix_f0_1 : OUT STD_LOGIC;
82 ready_matrix_f1 : OUT STD_LOGIC;
87 ready_matrix_f1 : OUT STD_LOGIC;
83 ready_matrix_f2 : OUT STD_LOGIC;
88 ready_matrix_f2 : OUT STD_LOGIC;
84 error_anticipating_empty_fifo : OUT STD_LOGIC;
89 error_anticipating_empty_fifo : OUT STD_LOGIC;
85 error_bad_component_error : OUT STD_LOGIC;
90 error_bad_component_error : OUT STD_LOGIC;
86 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 status_ready_matrix_f0_0 : IN STD_LOGIC;
92 status_ready_matrix_f0_0 : IN STD_LOGIC;
88 status_ready_matrix_f0_1 : IN STD_LOGIC;
93 status_ready_matrix_f0_1 : IN STD_LOGIC;
89 status_ready_matrix_f1 : IN STD_LOGIC;
94 status_ready_matrix_f1 : IN STD_LOGIC;
90 status_ready_matrix_f2 : IN STD_LOGIC;
95 status_ready_matrix_f2 : IN STD_LOGIC;
91 status_error_anticipating_empty_fifo : IN STD_LOGIC;
96 status_error_anticipating_empty_fifo : IN STD_LOGIC;
92 status_error_bad_component_error : IN STD_LOGIC;
97 status_error_bad_component_error : IN STD_LOGIC;
93 config_active_interruption_onNewMatrix : IN STD_LOGIC;
98 config_active_interruption_onNewMatrix : IN STD_LOGIC;
94 config_active_interruption_onError : IN STD_LOGIC;
99 config_active_interruption_onError : IN STD_LOGIC;
95 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104
105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
109 );
99 END COMPONENT;
110 END COMPONENT;
100
111
101
112
102 COMPONENT lpp_lfr_filter
113 COMPONENT lpp_lfr_filter
103 GENERIC (
114 GENERIC (
104 Mem_use : INTEGER);
115 Mem_use : INTEGER);
105 PORT (
116 PORT (
106 sample : IN Samples(7 DOWNTO 0);
117 sample : IN Samples(7 DOWNTO 0);
107 sample_val : IN STD_LOGIC;
118 sample_val : IN STD_LOGIC;
108 clk : IN STD_LOGIC;
119 clk : IN STD_LOGIC;
109 rstn : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
110 data_shaping_SP0 : IN STD_LOGIC;
121 data_shaping_SP0 : IN STD_LOGIC;
111 data_shaping_SP1 : IN STD_LOGIC;
122 data_shaping_SP1 : IN STD_LOGIC;
112 data_shaping_R0 : IN STD_LOGIC;
123 data_shaping_R0 : IN STD_LOGIC;
113 data_shaping_R1 : IN STD_LOGIC;
124 data_shaping_R1 : IN STD_LOGIC;
114 sample_f0_val : OUT STD_LOGIC;
125 sample_f0_val : OUT STD_LOGIC;
115 sample_f1_val : OUT STD_LOGIC;
126 sample_f1_val : OUT STD_LOGIC;
116 sample_f2_val : OUT STD_LOGIC;
127 sample_f2_val : OUT STD_LOGIC;
117 sample_f3_val : OUT STD_LOGIC;
128 sample_f3_val : OUT STD_LOGIC;
118 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
132 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
122 END COMPONENT;
133 END COMPONENT;
123
134
124 COMPONENT lpp_lfr
135 COMPONENT lpp_lfr
125 GENERIC (
136 GENERIC (
126 Mem_use : INTEGER;
137 Mem_use : INTEGER;
127 nb_data_by_buffer_size : INTEGER;
138 nb_data_by_buffer_size : INTEGER;
128 nb_word_by_buffer_size : INTEGER;
139 nb_word_by_buffer_size : INTEGER;
129 nb_snapshot_param_size : INTEGER;
140 nb_snapshot_param_size : INTEGER;
130 delta_vector_size : INTEGER;
141 delta_vector_size : INTEGER;
131 delta_vector_size_f0_2 : INTEGER;
142 delta_vector_size_f0_2 : INTEGER;
132 pindex : INTEGER;
143 pindex : INTEGER;
133 paddr : INTEGER;
144 paddr : INTEGER;
134 pmask : INTEGER;
145 pmask : INTEGER;
135 pirq_ms : INTEGER;
146 pirq_ms : INTEGER;
136 pirq_wfp : INTEGER;
147 pirq_wfp : INTEGER;
137 hindex : INTEGER;
148 hindex : INTEGER;
138 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
149 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
139 );
150 );
140 PORT (
151 PORT (
141 clk : IN STD_LOGIC;
152 clk : IN STD_LOGIC;
142 rstn : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
143 sample_B : IN Samples14v(2 DOWNTO 0);
154 sample_B : IN Samples14v(2 DOWNTO 0);
144 sample_E : IN Samples14v(4 DOWNTO 0);
155 sample_E : IN Samples14v(4 DOWNTO 0);
145 sample_val : IN STD_LOGIC;
156 sample_val : IN STD_LOGIC;
146 apbi : IN apb_slv_in_type;
157 apbi : IN apb_slv_in_type;
147 apbo : OUT apb_slv_out_type;
158 apbo : OUT apb_slv_out_type;
148 ahbi : IN AHB_Mst_In_Type;
159 ahbi : IN AHB_Mst_In_Type;
149 ahbo : OUT AHB_Mst_Out_Type;
160 ahbo : OUT AHB_Mst_Out_Type;
150 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
161 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
151 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
162 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
152 data_shaping_BW : OUT STD_LOGIC;
163 data_shaping_BW : OUT STD_LOGIC;
153 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
164 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
154 );
165 );
155 END COMPONENT;
166 END COMPONENT;
156
167
157 COMPONENT lpp_lfr_apbreg
168 COMPONENT lpp_lfr_apbreg
158 GENERIC (
169 GENERIC (
159 nb_data_by_buffer_size : INTEGER;
170 nb_data_by_buffer_size : INTEGER;
160 nb_word_by_buffer_size : INTEGER;
171 nb_word_by_buffer_size : INTEGER;
161 nb_snapshot_param_size : INTEGER;
172 nb_snapshot_param_size : INTEGER;
162 delta_vector_size : INTEGER;
173 delta_vector_size : INTEGER;
163 delta_vector_size_f0_2 : INTEGER;
174 delta_vector_size_f0_2 : INTEGER;
164 pindex : INTEGER;
175 pindex : INTEGER;
165 paddr : INTEGER;
176 paddr : INTEGER;
166 pmask : INTEGER;
177 pmask : INTEGER;
167 pirq_ms : INTEGER;
178 pirq_ms : INTEGER;
168 pirq_wfp : INTEGER;
179 pirq_wfp : INTEGER;
169 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
180 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
170 PORT (
181 PORT (
171 HCLK : IN STD_ULOGIC;
182 HCLK : IN STD_ULOGIC;
172 HRESETn : IN STD_ULOGIC;
183 HRESETn : IN STD_ULOGIC;
173 apbi : IN apb_slv_in_type;
184 apbi : IN apb_slv_in_type;
174 apbo : OUT apb_slv_out_type;
185 apbo : OUT apb_slv_out_type;
186 run_ms : OUT STD_LOGIC;
175 ready_matrix_f0_0 : IN STD_LOGIC;
187 ready_matrix_f0_0 : IN STD_LOGIC;
176 ready_matrix_f0_1 : IN STD_LOGIC;
188 ready_matrix_f0_1 : IN STD_LOGIC;
177 ready_matrix_f1 : IN STD_LOGIC;
189 ready_matrix_f1 : IN STD_LOGIC;
178 ready_matrix_f2 : IN STD_LOGIC;
190 ready_matrix_f2 : IN STD_LOGIC;
179 error_anticipating_empty_fifo : IN STD_LOGIC;
191 error_anticipating_empty_fifo : IN STD_LOGIC;
180 error_bad_component_error : IN STD_LOGIC;
192 error_bad_component_error : IN STD_LOGIC;
181 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
193 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
182 status_ready_matrix_f0_0 : OUT STD_LOGIC;
194 status_ready_matrix_f0_0 : OUT STD_LOGIC;
183 status_ready_matrix_f0_1 : OUT STD_LOGIC;
195 status_ready_matrix_f0_1 : OUT STD_LOGIC;
184 status_ready_matrix_f1 : OUT STD_LOGIC;
196 status_ready_matrix_f1 : OUT STD_LOGIC;
185 status_ready_matrix_f2 : OUT STD_LOGIC;
197 status_ready_matrix_f2 : OUT STD_LOGIC;
186 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
198 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
187 status_error_bad_component_error : OUT STD_LOGIC;
199 status_error_bad_component_error : OUT STD_LOGIC;
188 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
200 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
189 config_active_interruption_onError : OUT STD_LOGIC;
201 config_active_interruption_onError : OUT STD_LOGIC;
190 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
202 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
203 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
204 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
193 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
205 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
206
207 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
208 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
209 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
210 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
211
194 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
212 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
195 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
213 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
196 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
214 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
197 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
215 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
198 data_shaping_BW : OUT STD_LOGIC;
216 data_shaping_BW : OUT STD_LOGIC;
199 data_shaping_SP0 : OUT STD_LOGIC;
217 data_shaping_SP0 : OUT STD_LOGIC;
200 data_shaping_SP1 : OUT STD_LOGIC;
218 data_shaping_SP1 : OUT STD_LOGIC;
201 data_shaping_R0 : OUT STD_LOGIC;
219 data_shaping_R0 : OUT STD_LOGIC;
202 data_shaping_R1 : OUT STD_LOGIC;
220 data_shaping_R1 : OUT STD_LOGIC;
203 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
221 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
222 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
205 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
223 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
206 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
224 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
225 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
226 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
209 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
227 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
210 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
228 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
211 enable_f0 : OUT STD_LOGIC;
229 enable_f0 : OUT STD_LOGIC;
212 enable_f1 : OUT STD_LOGIC;
230 enable_f1 : OUT STD_LOGIC;
213 enable_f2 : OUT STD_LOGIC;
231 enable_f2 : OUT STD_LOGIC;
214 enable_f3 : OUT STD_LOGIC;
232 enable_f3 : OUT STD_LOGIC;
215 burst_f0 : OUT STD_LOGIC;
233 burst_f0 : OUT STD_LOGIC;
216 burst_f1 : OUT STD_LOGIC;
234 burst_f1 : OUT STD_LOGIC;
217 burst_f2 : OUT STD_LOGIC;
235 burst_f2 : OUT STD_LOGIC;
218 run : OUT STD_LOGIC;
236 run : OUT STD_LOGIC;
219 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
237 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
220 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
238 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
221 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
222 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
240 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
223 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
241 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
224 ---------------------------------------------------------------------------
242 ---------------------------------------------------------------------------
225 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
226 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
227 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
228 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
229 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
247 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
248 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
231 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
232 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
250 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
233 END COMPONENT;
251 END COMPONENT;
234
252
235 COMPONENT lpp_top_ms
253 COMPONENT lpp_top_ms
236 GENERIC (
254 GENERIC (
237 Mem_use : INTEGER;
255 Mem_use : INTEGER;
238 nb_burst_available_size : INTEGER;
256 nb_burst_available_size : INTEGER;
239 nb_snapshot_param_size : INTEGER;
257 nb_snapshot_param_size : INTEGER;
240 delta_snapshot_size : INTEGER;
258 delta_snapshot_size : INTEGER;
241 delta_f2_f0_size : INTEGER;
259 delta_f2_f0_size : INTEGER;
242 delta_f2_f1_size : INTEGER;
260 delta_f2_f1_size : INTEGER;
243 pindex : INTEGER;
261 pindex : INTEGER;
244 paddr : INTEGER;
262 paddr : INTEGER;
245 pmask : INTEGER;
263 pmask : INTEGER;
246 pirq_ms : INTEGER;
264 pirq_ms : INTEGER;
247 pirq_wfp : INTEGER;
265 pirq_wfp : INTEGER;
248 hindex_wfp : INTEGER;
266 hindex_wfp : INTEGER;
249 hindex_ms : INTEGER);
267 hindex_ms : INTEGER);
250 PORT (
268 PORT (
251 clk : IN STD_LOGIC;
269 clk : IN STD_LOGIC;
252 rstn : IN STD_LOGIC;
270 rstn : IN STD_LOGIC;
253 sample_B : IN Samples14v(2 DOWNTO 0);
271 sample_B : IN Samples14v(2 DOWNTO 0);
254 sample_E : IN Samples14v(4 DOWNTO 0);
272 sample_E : IN Samples14v(4 DOWNTO 0);
255 sample_val : IN STD_LOGIC;
273 sample_val : IN STD_LOGIC;
256 apbi : IN apb_slv_in_type;
274 apbi : IN apb_slv_in_type;
257 apbo : OUT apb_slv_out_type;
275 apbo : OUT apb_slv_out_type;
258 ahbi_ms : IN AHB_Mst_In_Type;
276 ahbi_ms : IN AHB_Mst_In_Type;
259 ahbo_ms : OUT AHB_Mst_Out_Type;
277 ahbo_ms : OUT AHB_Mst_Out_Type;
260 data_shaping_BW : OUT STD_LOGIC);
278 data_shaping_BW : OUT STD_LOGIC;
279 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
280 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
281 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
282 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
283
284 );
261 END COMPONENT;
285 END COMPONENT;
262
286
263 END lpp_lfr_pkg;
287 END lpp_lfr_pkg;
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