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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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PACKAGE lpp_lfr_pkg IS
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COMPONENT lpp_lfr_ms
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GENERIC (
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Mem_use : INTEGER
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
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fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
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sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_valid : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_lfr_ms_fsmdma
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_valid : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_lfr_filter
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GENERIC (
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Mem_use : INTEGER);
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PORT (
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sample : IN Samples(7 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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data_shaping_SP0 : IN STD_LOGIC;
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data_shaping_SP1 : IN STD_LOGIC;
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data_shaping_R0 : IN STD_LOGIC;
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data_shaping_R1 : IN STD_LOGIC;
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sample_f0_val : OUT STD_LOGIC;
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sample_f1_val : OUT STD_LOGIC;
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sample_f2_val : OUT STD_LOGIC;
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sample_f3_val : OUT STD_LOGIC;
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sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_lfr
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GENERIC (
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Mem_use : INTEGER;
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nb_data_by_buffer_size : INTEGER;
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nb_word_by_buffer_size : INTEGER;
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nb_snapshot_param_size : INTEGER;
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delta_vector_size : INTEGER;
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delta_vector_size_f0_2 : INTEGER;
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER;
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pirq_ms : INTEGER;
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pirq_wfp : INTEGER;
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hindex : INTEGER;
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top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_B : IN Samples14v(2 DOWNTO 0);
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sample_E : IN Samples14v(4 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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ahbi : IN AHB_Mst_In_Type;
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ahbo : OUT AHB_Mst_Out_Type;
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coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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data_shaping_BW : OUT STD_LOGIC;
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observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT lpp_lfr_apbreg
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GENERIC (
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nb_data_by_buffer_size : INTEGER;
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nb_word_by_buffer_size : INTEGER;
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nb_snapshot_param_size : INTEGER;
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delta_vector_size : INTEGER;
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delta_vector_size_f0_2 : INTEGER;
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER;
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pirq_ms : INTEGER;
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pirq_wfp : INTEGER;
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top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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ready_matrix_f0_0 : IN STD_LOGIC;
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ready_matrix_f0_1 : IN STD_LOGIC;
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ready_matrix_f1 : IN STD_LOGIC;
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ready_matrix_f2 : IN STD_LOGIC;
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error_anticipating_empty_fifo : IN STD_LOGIC;
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error_bad_component_error : IN STD_LOGIC;
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debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_ready_matrix_f0_0 : OUT STD_LOGIC;
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status_ready_matrix_f0_1 : OUT STD_LOGIC;
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status_ready_matrix_f1 : OUT STD_LOGIC;
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status_ready_matrix_f2 : OUT STD_LOGIC;
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status_error_anticipating_empty_fifo : OUT STD_LOGIC;
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status_error_bad_component_error : OUT STD_LOGIC;
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config_active_interruption_onNewMatrix : OUT STD_LOGIC;
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config_active_interruption_onError : OUT STD_LOGIC;
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addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_shaping_BW : OUT STD_LOGIC;
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data_shaping_SP0 : OUT STD_LOGIC;
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data_shaping_SP1 : OUT STD_LOGIC;
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data_shaping_R0 : OUT STD_LOGIC;
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data_shaping_R1 : OUT STD_LOGIC;
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delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
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delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
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nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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enable_f0 : OUT STD_LOGIC;
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enable_f1 : OUT STD_LOGIC;
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enable_f2 : OUT STD_LOGIC;
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enable_f3 : OUT STD_LOGIC;
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burst_f0 : OUT STD_LOGIC;
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burst_f1 : OUT STD_LOGIC;
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burst_f2 : OUT STD_LOGIC;
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run : OUT STD_LOGIC;
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addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
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---------------------------------------------------------------------------
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debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_top_ms
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GENERIC (
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Mem_use : INTEGER;
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nb_burst_available_size : INTEGER;
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nb_snapshot_param_size : INTEGER;
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delta_snapshot_size : INTEGER;
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delta_f2_f0_size : INTEGER;
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delta_f2_f1_size : INTEGER;
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER;
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pirq_ms : INTEGER;
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pirq_wfp : INTEGER;
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hindex_wfp : INTEGER;
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hindex_ms : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_B : IN Samples14v(2 DOWNTO 0);
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sample_E : IN Samples14v(4 DOWNTO 0);
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sample_val : IN STD_LOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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ahbi_ms : IN AHB_Mst_In_Type;
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ahbo_ms : OUT AHB_Mst_Out_Type;
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data_shaping_BW : OUT STD_LOGIC);
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END COMPONENT;
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END lpp_lfr_pkg;
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