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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 --! Programme qui va permettre de "pipeliner" la FIFO, donn�e disponible en sortie d� son �criture en entr�e de la FIFO
27
28 entity Pipeline is
29 generic(Data_sz : integer := 16);
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en entr�e de la FIFO, cot� �criture
33 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donn�e en sortie de la FIFO, cot� lecture
34 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
36 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
37 empty : in std_logic; --! Flag, M�moire vide
38 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donn�e en sortie, pipelin�e
39 );
40 end Pipeline;
41
42 architecture ar_Pipeline of Pipeline is
43
44 type etat is (e0,e1,e2,eX);
45 signal ect : etat;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Data_out <= (others => 'X');
52 ect <= e0;
53
54 elsif(clk' event and clk='1')then
55 case ect is
56 when e0 =>
57 if(flag_WR='1')then
58 Data_out <= Data_one;
59 ect <= e1;
60 -- elsif(ReUse='1')then
61 -- ect <= e1;
62 end if;
63
64 when e1 =>
65 if(flag_RE='1')then
66 --Data_out <= Data_two;
67 ect <= eX;
68 end if;
69
70 when eX =>
71 --Data_out <= Data_two;
72 ect <= e2;
73
74 when e2 =>
75 Data_out <= Data_two;
76 if(empty='1')then
77 ect <= e0;
78 else
79 --Data_out <= Data_two;
80 ect <= e2;
81 end if;
82
83
84
85 end case;
86 end if;
87 end process;
88
89 end ar_Pipeline;
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1 #------------------------------------------------------------------------------
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
8 #-- (at your option) any later version.
9 #--
9 #--
10 #-- This program is distributed in the hope that it will be useful,
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
13 #-- GNU General Public License for more details.
14 #--
14 #--
15 #-- You should have received a copy of the GNU General Public License
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
18 #------------------------------------------------------------------------------
19
19
20
20
21
21
22 all:
22 all:
23 make all -C ScanAPB
23 make all -C ScanAPB
24 make all -C APB_lcd_ctrlr
24 make all -C APB_lcd_ctrlr
25 make all -C BenchFIFO
25 make all -C BenchFIFO
26 make all -C BenchUART
26 make all -C BenchUART
27 make all -C BenchFFT
27 make all -C BenchFFT
28 make all -C BenchGPIO
28 make all -C BenchGPIO
29 make all -C BenchMatrix
29 make all -C BenchMatrix No newline at end of file
30
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@@ -1,131 +1,131
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_matrix.all;
31 use lpp.lpp_matrix.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
34
35 entity APB_Matrix is
35 entity APB_Matrix is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Input_SZ : integer := 16;
42 Input_SZ : integer := 16;
43 Result_SZ : integer := 32);
43 Result_SZ : integer := 32);
44 port (
44 port (
45 clk : in std_logic; --! Horloge du composant
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
46 rst : in std_logic; --! Reset general du composant
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 -- Start : out std_logic;
54 Start : out std_logic;
55 -- Read : out std_logic;
55 -- Read : out std_logic;
56 -- Take : out std_logic;
56 -- Take : out std_logic;
57 -- Valid : out std_logic;
57 -- Valid : out std_logic;
58 -- Received : out std_logic;
58 -- Received : out std_logic;
59 -- Conjugate : out std_logic;
59 -- Conjugate : out std_logic;
60 -- OP1 : out std_logic_vector(3 downto 0);
60 -- OP1 : out std_logic_vector(3 downto 0);
61 -- OP2 : out std_logic_vector(3 downto 0);
61 -- OP2 : out std_logic_vector(3 downto 0);
62 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
62 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
64 );
64 );
65 end APB_Matrix;
65 end APB_Matrix;
66
66
67
67
68 architecture ar_APB_Matrix of APB_Matrix is
68 architecture ar_APB_Matrix of APB_Matrix is
69
69
70 constant REVISION : integer := 1;
70 constant REVISION : integer := 1;
71
71
72 constant pconfig : apb_config_type := (
72 constant pconfig : apb_config_type := (
73 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
73 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
74 1 => apb_iobar(paddr, pmask));
74 1 => apb_iobar(paddr, pmask));
75
75
76 type MATRIX_ctrlr_Reg is record
76 type MATRIX_ctrlr_Reg is record
77 MATRIX_Statu : std_logic_vector(3 downto 0);
77 MATRIX_Statu : std_logic_vector(3 downto 0);
78 end record;
78 end record;
79
79
80 signal Rec : MATRIX_ctrlr_Reg;
80 signal Rec : MATRIX_ctrlr_Reg;
81 signal Rdata : std_logic_vector(31 downto 0);
81 signal Rdata : std_logic_vector(31 downto 0);
82
82
83 begin
83 begin
84
84
85 Mspec0 : SpectralMatrix
85 Mspec0 : SpectralMatrix
86 generic map (Input_SZ,Result_SZ)
86 generic map (Input_SZ,Result_SZ)
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88
88
89 process(rst,clk)
89 process(rst,clk)
90 begin
90 begin
91 if(rst='0')then
91 if(rst='0')then
92 Rec.MATRIX_Statu <= (others => '0');
92 Rec.MATRIX_Statu <= (others => '0');
93
93
94 elsif(clk'event and clk='1')then
94 elsif(clk'event and clk='1')then
95
95
96 --APB Write OP
96 --APB Write OP
97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 case apbi.paddr(abits-1 downto 2) is
98 case apbi.paddr(abits-1 downto 2) is
99 when "000000" =>
99 when "000000" =>
100 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
100 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
101 when others =>
101 when others =>
102 null;
102 null;
103 end case;
103 end case;
104 end if;
104 end if;
105
105
106 --APB READ OP
106 --APB READ OP
107 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
107 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 case apbi.paddr(abits-1 downto 2) is
108 case apbi.paddr(abits-1 downto 2) is
109 when "000000" =>
109 when "000000" =>
110 Rdata(31 downto 4) <= (others => '0');
110 Rdata(31 downto 4) <= (others => '0');
111 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
111 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
112 --when "000001" =>
112 --when "000001" =>
113 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
113 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
114 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
114 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
115 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
115 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
116 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
116 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
117 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
117 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
118 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
118 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
119 -- Rdata(31 downto 24) <= X"CC";
119 -- Rdata(31 downto 24) <= X"CC";
120 when others =>
120 when others =>
121 Rdata <= (others => '0');
121 Rdata <= (others => '0');
122 end case;
122 end case;
123 end if;
123 end if;
124
124
125 end if;
125 end if;
126 apbo.pconfig <= pconfig;
126 apbo.pconfig <= pconfig;
127 end process;
127 end process;
128
128
129 apbo.prdata <= Rdata when apbi.penable = '1';
129 apbo.prdata <= Rdata when apbi.penable = '1';
130
130
131 end ar_APB_MATRIX; No newline at end of file
131 end ar_APB_MATRIX;
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@@ -1,108 +1,108
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25 use lpp.lpp_matrix.all;
26
26
27 entity SpectralMatrix is
27 entity SpectralMatrix is
28 generic(
28 generic(
29 Input_SZ : integer := 16;
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
30 Result_SZ : integer := 32);
31 port(
31 port(
32 clk : in std_logic;
32 clk : in std_logic;
33 reset : in std_logic;
33 reset : in std_logic;
34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
36 Full : in std_logic_vector(1 downto 0);
36 Full : in std_logic_vector(1 downto 0);
37 Empty : in std_logic_vector(1 downto 0);
37 Empty : in std_logic_vector(1 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
40 WriteFIFO : out std_logic;
41 -- Start : out std_logic;
41 Start : out std_logic;
42 -- Read : out std_logic;
42 -- Read : out std_logic;
43 -- Take : out std_logic;
43 -- Take : out std_logic;
44 -- Valid : out std_logic;
44 -- Valid : out std_logic;
45 -- Received : out std_logic;
45 -- Received : out std_logic;
46 -- Conjugate : out std_logic;
46 -- Conjugate : out std_logic;
47 -- OP1 : out std_logic_vector(3 downto 0);
47 -- OP1 : out std_logic_vector(3 downto 0);
48 -- OP2 : out std_logic_vector(3 downto 0);
48 -- OP2 : out std_logic_vector(3 downto 0);
49 Result : out std_logic_vector(Result_SZ-1 downto 0)
49 Result : out std_logic_vector(Result_SZ-1 downto 0)
50 );
50 );
51 end SpectralMatrix;
51 end SpectralMatrix;
52
52
53
53
54 architecture ar_SpectralMatrix of SpectralMatrix is
54 architecture ar_SpectralMatrix of SpectralMatrix is
55
55
56 signal Start_int : std_logic;
56 signal Start_int : std_logic;
57 signal Read_int : std_logic;
57 signal Read_int : std_logic;
58 signal Take_int : std_logic;
58 signal Take_int : std_logic;
59 signal Received_int : std_logic;
59 signal Received_int : std_logic;
60 signal Valid_int : std_logic;
60 signal Valid_int : std_logic;
61 signal Conjugate_int : std_logic;
61 signal Conjugate_int : std_logic;
62
62
63 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
63 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
64 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
64 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
65 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
65 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
66 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
66 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
67
67
68
68
69 begin
69 begin
70
70
71 ST0 : Starter
71 ST0 : Starter
72 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
72 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
73
73
74 --IN0 : SelectInputs
74 --IN0 : SelectInputs
75 -- generic map(Input_SZ)
75 -- generic map(Input_SZ)
76 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
76 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
77
77
78 IN1 : DriveInputs
78 IN1 : DriveInputs
79 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
79 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
80
80
81
81
82 CALC0 : Matrix
82 CALC0 : Matrix
83 generic map(Input_SZ)
83 generic map(Input_SZ)
84 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
84 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
85
85
86
86
87 RES0 : GetResult
87 RES0 : GetResult
88 generic map(Result_SZ)
88 generic map(Result_SZ)
89 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
89 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
90
90
91
91
92 With Statu select
92 With Statu select
93 Conjugate_int <= '1' when "0001",
93 Conjugate_int <= '1' when "0001",
94 '1' when "0011",
94 '1' when "0011",
95 '1' when "0110",
95 '1' when "0110",
96 '1' when "1010",
96 '1' when "1010",
97 '1' when "1111",
97 '1' when "1111",
98 '0' when others;
98 '0' when others;
99
99
100 --Start <= Start_int;
100 Start <= Start_int;
101 --Read <= Read_int;
101 --Read <= Read_int;
102 --Take <= Take_int;
102 --Take <= Take_int;
103 --Received <= Received_int;
103 --Received <= Received_int;
104 --Valid <= Valid_int;
104 --Valid <= Valid_int;
105 --Conjugate <= Conjugate_int;
105 --Conjugate <= Conjugate_int;
106 --Result <= Resultat;
106 --Result <= Resultat;
107
107
108 end ar_SpectralMatrix; No newline at end of file
108 end ar_SpectralMatrix;
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@@ -1,229 +1,231
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic; --! Horloge du composant
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
45 rst : in std_logic; --! Reset general du composant
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 WriteFIFO : out std_logic;
51 WriteFIFO : out std_logic;
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Start : out std_logic;
53 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 );
56 );
56 end component;
57 end component;
57
58
58
59
59 component SpectralMatrix is
60 component SpectralMatrix is
60 generic(
61 generic(
61 Input_SZ : integer := 16;
62 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 Result_SZ : integer := 32);
63 port(
64 port(
64 clk : in std_logic;
65 clk : in std_logic;
65 reset : in std_logic;
66 reset : in std_logic;
66 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
67 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
68 Full : in std_logic_vector(1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
69 Empty : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
70 Statu : in std_logic_vector(3 downto 0);
71 Statu : in std_logic_vector(3 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
72 ReadFIFO : out std_logic_vector(1 downto 0);
72 WriteFIFO : out std_logic;
73 WriteFIFO : out std_logic;
74 Start : out std_logic;
73 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 Result : out std_logic_vector(Result_SZ-1 downto 0)
74 );
76 );
75 end component;
77 end component;
76
78
77
79
78 component Matrix is
80 component Matrix is
79 generic(
81 generic(
80 Input_SZ : integer := 16);
82 Input_SZ : integer := 16);
81 port(
83 port(
82 clk : in std_logic;
84 clk : in std_logic;
83 raz : in std_logic;
85 raz : in std_logic;
84 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
86 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
85 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
87 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
86 Take : in std_logic;
88 Take : in std_logic;
87 Received : in std_logic;
89 Received : in std_logic;
88 Conjugate : in std_logic;
90 Conjugate : in std_logic;
89 Valid : out std_logic;
91 Valid : out std_logic;
90 Read : out std_logic;
92 Read : out std_logic;
91 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
93 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
92 );
94 );
93 end component;
95 end component;
94
96
95
97
96 component ALU_Driver is
98 component ALU_Driver is
97 generic(
99 generic(
98 Input_SZ_1 : integer := 16;
100 Input_SZ_1 : integer := 16;
99 Input_SZ_2 : integer := 16);
101 Input_SZ_2 : integer := 16);
100 port(
102 port(
101 clk : in std_logic;
103 clk : in std_logic;
102 reset : in std_logic;
104 reset : in std_logic;
103 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
105 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
104 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
106 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
105 Take : in std_logic;
107 Take : in std_logic;
106 Received : in std_logic;
108 Received : in std_logic;
107 Conjugate : in std_logic;
109 Conjugate : in std_logic;
108 Valid : out std_logic;
110 Valid : out std_logic;
109 Read : out std_logic;
111 Read : out std_logic;
110 CTRL : out std_logic_vector(4 downto 0);
112 CTRL : out std_logic_vector(4 downto 0);
111 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
113 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
112 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
114 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
113 );
115 );
114 end component;
116 end component;
115
117
116
118
117 component ALU_v2 is
119 component ALU_v2 is
118 generic(
120 generic(
119 Arith_en : integer := 1;
121 Arith_en : integer := 1;
120 Logic_en : integer := 1;
122 Logic_en : integer := 1;
121 Input_SZ_1 : integer := 16;
123 Input_SZ_1 : integer := 16;
122 Input_SZ_2 : integer := 9);
124 Input_SZ_2 : integer := 9);
123 port(
125 port(
124 clk : in std_logic;
126 clk : in std_logic;
125 reset : in std_logic;
127 reset : in std_logic;
126 ctrl : in std_logic_vector(4 downto 0);
128 ctrl : in std_logic_vector(4 downto 0);
127 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
129 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
128 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
130 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
129 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
131 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
130 );
132 );
131 end component;
133 end component;
132
134
133
135
134 component MAC_v2 is
136 component MAC_v2 is
135 generic(
137 generic(
136 Input_SZ_A : integer := 8;
138 Input_SZ_A : integer := 8;
137 Input_SZ_B : integer := 8);
139 Input_SZ_B : integer := 8);
138 port(
140 port(
139 clk : in std_logic;
141 clk : in std_logic;
140 reset : in std_logic;
142 reset : in std_logic;
141 clr_MAC : in std_logic;
143 clr_MAC : in std_logic;
142 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
144 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
143 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
145 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
144 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
146 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
145 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
147 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
146 );
148 );
147 end component;
149 end component;
148
150
149
151
150 component TwoComplementer is
152 component TwoComplementer is
151 generic(
153 generic(
152 Input_SZ : integer := 16);
154 Input_SZ : integer := 16);
153 port(
155 port(
154 clk : in std_logic;
156 clk : in std_logic;
155 reset : in std_logic;
157 reset : in std_logic;
156 clr : in std_logic;
158 clr : in std_logic;
157 TwoComp : in std_logic;
159 TwoComp : in std_logic;
158 OP : in std_logic_vector(Input_SZ-1 downto 0);
160 OP : in std_logic_vector(Input_SZ-1 downto 0);
159 RES : out std_logic_vector(Input_SZ-1 downto 0)
161 RES : out std_logic_vector(Input_SZ-1 downto 0)
160 );
162 );
161 end component;
163 end component;
162
164
163
165
164 component GetResult is
166 component GetResult is
165 generic(
167 generic(
166 Result_SZ : integer := 32);
168 Result_SZ : integer := 32);
167 port(
169 port(
168 clk : in std_logic;
170 clk : in std_logic;
169 raz : in std_logic;
171 raz : in std_logic;
170 Valid : in std_logic;
172 Valid : in std_logic;
171 Conjugate : in std_logic;
173 Conjugate : in std_logic;
172 Res : in std_logic_vector(Result_SZ-1 downto 0);
174 Res : in std_logic_vector(Result_SZ-1 downto 0);
173 WriteFIFO : out std_logic;
175 WriteFIFO : out std_logic;
174 Received : out std_logic;
176 Received : out std_logic;
175 Result : out std_logic_vector(Result_SZ-1 downto 0)
177 Result : out std_logic_vector(Result_SZ-1 downto 0)
176 );
178 );
177 end component;
179 end component;
178
180
179
181
180 component SelectInputs is
182 component SelectInputs is
181 generic(
183 generic(
182 Input_SZ : integer := 16);
184 Input_SZ : integer := 16);
183 port(
185 port(
184 clk : in std_logic;
186 clk : in std_logic;
185 raz : in std_logic;
187 raz : in std_logic;
186 Read : in std_logic;
188 Read : in std_logic;
187 B1 : in std_logic_vector(Input_SZ-1 downto 0);
189 B1 : in std_logic_vector(Input_SZ-1 downto 0);
188 B2 : in std_logic_vector(Input_SZ-1 downto 0);
190 B2 : in std_logic_vector(Input_SZ-1 downto 0);
189 B3 : in std_logic_vector(Input_SZ-1 downto 0);
191 B3 : in std_logic_vector(Input_SZ-1 downto 0);
190 E1 : in std_logic_vector(Input_SZ-1 downto 0);
192 E1 : in std_logic_vector(Input_SZ-1 downto 0);
191 E2 : in std_logic_vector(Input_SZ-1 downto 0);
193 E2 : in std_logic_vector(Input_SZ-1 downto 0);
192 Conjugate : out std_logic;
194 Conjugate : out std_logic;
193 Take : out std_logic;
195 Take : out std_logic;
194 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
196 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
195 Statu : out std_logic_vector(3 downto 0);
197 Statu : out std_logic_vector(3 downto 0);
196 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
198 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
197 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
199 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
198 );
200 );
199 end component;
201 end component;
200 ---------------------------------------------------------------------------
202 ---------------------------------------------------------------------------
201 component DriveInputs is
203 component DriveInputs is
202 port(
204 port(
203 clk : in std_logic;
205 clk : in std_logic;
204 raz : in std_logic;
206 raz : in std_logic;
205 Read : in std_logic;
207 Read : in std_logic;
206 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
208 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
207 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
209 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
208 -- Statu : in std_logic_vector(3 downto 0);
210 -- Statu : in std_logic_vector(3 downto 0);
209 Conjugate : in std_logic;
211 Conjugate : in std_logic;
210 Take : out std_logic;
212 Take : out std_logic;
211 ReadFIFO : out std_logic_vector(1 downto 0)
213 ReadFIFO : out std_logic_vector(1 downto 0)
212 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
214 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
213 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
215 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
214 );
216 );
215 end component;
217 end component;
216
218
217 component Starter is
219 component Starter is
218 port(
220 port(
219 clk : in std_logic;
221 clk : in std_logic;
220 raz : in std_logic;
222 raz : in std_logic;
221 Full : in std_logic_vector(1 downto 0);
223 Full : in std_logic_vector(1 downto 0);
222 Empty : in std_logic_vector(1 downto 0);
224 Empty : in std_logic_vector(1 downto 0);
223 Conjugate : in std_logic;
225 Conjugate : in std_logic;
224 received : in std_logic;
226 received : in std_logic;
225 Start : out std_logic
227 Start : out std_logic
226 );
228 );
227 end component;
229 end component;
228
230
229 end; No newline at end of file
231 end;
Show file before | Show file after | Hide comments
@@ -1,87 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FIFO is
35 entity APB_FIFO is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Full : out std_logic;
49 Full : out std_logic;
50 Empty : out std_logic;
50 Empty : out std_logic;
51 WR : out std_logic;
51 WR : out std_logic;
52 RE : out std_logic;
52 RE : out std_logic;
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 );
54 );
55 end APB_FIFO;
55 end APB_FIFO;
56
56
57
57
58 architecture ar_APB_FIFO of APB_FIFO is
58 architecture ar_APB_FIFO of APB_FIFO is
59
59
60 signal ReadEnable : std_logic;
60 signal ReadEnable : std_logic;
61 signal WriteEnable : std_logic;
61 signal WriteEnable : std_logic;
62 signal FlagEmpty : std_logic;
62 signal FlagEmpty : std_logic;
63 signal FlagFull : std_logic;
63 signal FlagFull : std_logic;
64 signal ReUse : std_logic;
64 --signal ReUse : std_logic;
65 signal Lock : std_logic;
65 --signal Lock : std_logic;
66 --signal RstMem : std_logic;
66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
70
71
71 begin
72 begin
72
73
73 APB : ApbDriver
74 APB : ApbDriver
74 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
75 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
76 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
76
77
77
78
78 DEVICE : Top_FIFO
79 DEVICE : Top_FIFO
79 generic map(Data_sz,Addr_sz,addr_max_int)
80 generic map(Data_sz,Addr_sz,addr_max_int)
80 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
81 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
81
82
82 Empty <= FlagEmpty;
83 Empty <= FlagEmpty;
83 Full <= FlagFull;
84 Full <= FlagFull;
84 WR <= WriteEnable;
85 WR <= WriteEnable;
85 RE <= ReadEnable;
86 RE <= ReadEnable;
86
87
87 end ar_APB_FIFO; No newline at end of file
88 end ar_APB_FIFO;
Show file before | Show file after | Hide comments
@@ -1,86 +1,87
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoRead is
35 entity APB_FifoRead is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 WriteEnable : in std_logic; --! Demande d'�criture dans la m�moire, g�r� hors de l'IP
49 WriteEnable : in std_logic; --! Demande d'�criture dans la m�moire, g�r� hors de l'IP
50 Full : out std_logic; --! Flag, Memoire pleine
50 Full : out std_logic; --! Flag, Memoire pleine
51 Empty : out std_logic; --! Flag, Memoire vide
51 Empty : out std_logic; --! Flag, Memoire vide
52 DATA : in std_logic_vector(Data_sz-1 downto 0); --! Donn�es en entr�e de la m�moire
52 DATA : in std_logic_vector(Data_sz-1 downto 0); --! Donn�es en entr�e de la m�moire
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 );
54 );
55 end APB_FifoRead;
55 end APB_FifoRead;
56
56
57 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
57 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
58
58
59 architecture ar_APB_FifoRead of APB_FifoRead is
59 architecture ar_APB_FifoRead of APB_FifoRead is
60
60
61 signal Low : std_logic:='0';
61 signal Low : std_logic:='0';
62 signal ReadEnable : std_logic;
62 signal ReadEnable : std_logic;
63 signal FlagEmpty : std_logic;
63 signal FlagEmpty : std_logic;
64 signal FlagFull : std_logic;
64 signal FlagFull : std_logic;
65 signal ReUse : std_logic;
65 --signal ReUse : std_logic;
66 signal Lock : std_logic;
66 --signal Lock : std_logic;
67 --signal RstMem : std_logic;
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71
72
72 begin
73 begin
73
74
74 APB : ApbDriver
75 APB : ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
78
79
79 FIFO : Top_FIFO
80 FIFO : Top_FIFO
80 generic map(Data_sz,Addr_sz,addr_max_int)
81 generic map(Data_sz,Addr_sz,addr_max_int)
81 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82 port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82
83
83 Empty <= FlagEmpty;
84 Empty <= FlagEmpty;
84 Full <= FlagFull;
85 Full <= FlagFull;
85
86
86 end ar_APB_FifoRead; No newline at end of file
87 end ar_APB_FifoRead;
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@@ -1,87 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_memory.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoWrite is
35 entity APB_FifoWrite is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Empty : out std_logic; --! Flag, Memoire vide
50 Empty : out std_logic; --! Flag, Memoire vide
51 Full : out std_logic; --! Flag, Memoire pleine
51 Full : out std_logic; --! Flag, Memoire pleine
52 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
52 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 );
54 );
55 end APB_FifoWrite;
55 end APB_FifoWrite;
56
56
57 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
57 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
58
58
59 architecture ar_APB_FifoWrite of APB_FifoWrite is
59 architecture ar_APB_FifoWrite of APB_FifoWrite is
60
60
61 signal Low : std_logic:='0';
61 signal Low : std_logic:='0';
62 signal WriteEnable : std_logic;
62 signal WriteEnable : std_logic;
63 signal FlagEmpty : std_logic;
63 signal FlagEmpty : std_logic;
64 signal FlagFull : std_logic;
64 signal FlagFull : std_logic;
65 signal ReUse : std_logic;
65 --signal ReUse : std_logic;
66 signal Lock : std_logic;
66 --signal Lock : std_logic;
67 --signal RstMem : std_logic;
67 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
68 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
69 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
70 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
71
72
72 begin
73 begin
73
74
74 APB : ApbDriver
75 APB : ApbDriver
75 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
76 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
78
79
79 FIFO : Top_FIFO
80 FIFO : Top_FIFO
80 generic map(Data_sz,Addr_sz,addr_max_int)
81 generic map(Data_sz,Addr_sz,addr_max_int)
81 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
82
83
83 DATA <= DataOut;
84 DATA <= DataOut;
84 Empty <= FlagEmpty;
85 Empty <= FlagEmpty;
85 Full <= FlagFull;
86 Full <= FlagFull;
86
87
87 end ar_APB_FifoWrite; No newline at end of file
88 end ar_APB_FifoWrite;
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@@ -1,165 +1,171
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31
31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
33
33
34 entity ApbDriver is
34 entity ApbDriver is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
41 LPP_DEVICE : integer;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
52 -- ReUse : out std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
53 Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
53 -- Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
54 -- RstMem : out std_logic; --! Flag, Reset "manuel" sp�cifique au composant
54 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
55 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
55 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
56 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
56 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
57 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
57 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
58 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
58 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
59 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
59 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
60 );
61 );
61 end ApbDriver;
62 end ApbDriver;
62
63
63 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
64
65
65 architecture ar_ApbDriver of ApbDriver is
66 architecture ar_ApbDriver of ApbDriver is
66
67
67 constant REVISION : integer := 1;
68 constant REVISION : integer := 1;
68
69
69 constant pconfig : apb_config_type := (
70 constant pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
71 1 => apb_iobar(paddr, pmask));
72 1 => apb_iobar(paddr, pmask));
72
73
73 type DEVICE_ctrlr_Reg is record
74 type DEVICE_ctrlr_Reg is record
74 DEVICE_Cfg : std_logic_vector(5 downto 0);
75 DEVICE_Cfg : std_logic_vector(3 downto 0);
75 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
78 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
79 end record;
80 end record;
80
81
81 signal Rec : DEVICE_ctrlr_Reg;
82 signal Rec : DEVICE_ctrlr_Reg;
82 signal Rdata : std_logic_vector(31 downto 0);
83 signal Rdata : std_logic_vector(31 downto 0);
83
84
84 signal FlagRE : std_logic;
85 signal FlagRE : std_logic;
85 signal FlagWR : std_logic;
86 signal FlagWR : std_logic;
86
87
87 begin
88 begin
88
89
89 Rec.DEVICE_Cfg(0) <= FlagRE;
90 Rec.DEVICE_Cfg(0) <= FlagRE;
90 Rec.DEVICE_Cfg(1) <= FlagWR;
91 Rec.DEVICE_Cfg(1) <= FlagWR;
91 Rec.DEVICE_Cfg(2) <= FlagEmpty;
92 Rec.DEVICE_Cfg(2) <= FlagEmpty;
92 Rec.DEVICE_Cfg(3) <= FlagFull;
93 Rec.DEVICE_Cfg(3) <= FlagFull;
93 ReUse <= Rec.DEVICE_Cfg(4);
94 --ReUse <= Rec.DEVICE_Cfg(4);
94 Lock <= Rec.DEVICE_Cfg(5);
95 --Lock <= Rec.DEVICE_Cfg(5);
96 --RstMem <= Rec.DEVICE_Cfg(7);
95
97
96 DataIn <= Rec.DEVICE_DataW;
98 DataIn <= Rec.DEVICE_DataW;
97 Rec.DEVICE_DataR <= DataOut;
99 Rec.DEVICE_DataR <= DataOut;
98 Rec.DEVICE_AddrW <= AddrIn;
100 Rec.DEVICE_AddrW <= AddrIn;
99 Rec.DEVICE_AddrR <= AddrOut;
101 Rec.DEVICE_AddrR <= AddrOut;
100
102
101
103
102
104
103 process(rst,clk)
105 process(rst,clk)
104 begin
106 begin
105 if(rst='0')then
107 if(rst='0')then
106 Rec.DEVICE_DataW <= (others => '0');
108 Rec.DEVICE_DataW <= (others => '0');
107 FlagWR <= '0';
109 FlagWR <= '0';
108 FlagRE <= '0';
110 FlagRE <= '0';
109 Rec.DEVICE_Cfg(4) <= '0';
111 -- Rec.DEVICE_Cfg(4) <= '0';
110 Rec.DEVICE_Cfg(5) <= '0';
112 -- Rec.DEVICE_Cfg(5) <= '0';
113 -- Rec.DEVICE_Cfg(7) <= '0';
111
114
112 elsif(clk'event and clk='1')then
115 elsif(clk'event and clk='1')then
113
116
114 --APB Write OP
117 --APB Write OP
115 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
118 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
116 case apbi.paddr(abits-1 downto 2) is
119 case apbi.paddr(abits-1 downto 2) is
117 when "000000" =>
120 when "000000" =>
118 FlagWR <= '1';
121 FlagWR <= '1';
119 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
122 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
120 when "000010" =>
123 -- when "000010" =>
121 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
124 -- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28);
122 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
125 -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
126 -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
123 when others =>
127 when others =>
124 null;
128 null;
125 end case;
129 end case;
126 else
130 else
127 FlagWR <= '0';
131 FlagWR <= '0';
128 end if;
132 end if;
129
133
130 --APB Read OP
134 --APB Read OP
131 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
135 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
132 case apbi.paddr(abits-1 downto 2) is
136 case apbi.paddr(abits-1 downto 2) is
133 when "000000" =>
137 when "000000" =>
134 FlagRE <= '1';
138 FlagRE <= '1';
135 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
139 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
136 when "000001" =>
140 when "000001" =>
137 Rdata(31 downto 8) <= X"AAAAAA";
141 -- Rdata(31 downto 8) <= X"AAAAAA";
138 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
142 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR;
139 when "000101" =>
143 when "000101" =>
140 Rdata(31 downto 8) <= X"AAAAAA";
144 -- Rdata(31 downto 8) <= X"AAAAAA";
141 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
145 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW;
142 when "000010" =>
146 when "000010" =>
143 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
147 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
144 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
148 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
145 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
149 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
146 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
150 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
147 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
151 -- Rdata(27 downto 16) <= X"000";
148 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
152 -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
149 Rdata(31 downto 24) <= X"CC";
153 -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
154 -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
155 Rdata(31 downto 16) <= X"CCCC";
150 when others =>
156 when others =>
151 Rdata <= (others => '0');
157 Rdata <= (others => '0');
152 end case;
158 end case;
153 else
159 else
154 FlagRE <= '0';
160 FlagRE <= '0';
155 end if;
161 end if;
156
162
157 end if;
163 end if;
158 apbo.pconfig <= pconfig;
164 apbo.pconfig <= pconfig;
159 end process;
165 end process;
160
166
161 apbo.prdata <= Rdata when apbi.penable = '1';
167 apbo.prdata <= Rdata when apbi.penable = '1';
162 WriteEnable <= FlagWR;
168 WriteEnable <= FlagWR;
163 ReadEnable <= FlagRE;
169 ReadEnable <= FlagRE;
164
170
165 end ar_ApbDriver; No newline at end of file
171 end ar_ApbDriver;
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@@ -1,93 +1,94
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 --! Programme de la FIFO de lecture
26 --! Programme de la FIFO de lecture
27
27
28 entity Fifo_Read is
28 entity Fifo_Read is
29 generic(
29 generic(
30 Addr_sz : integer := 8;
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
31 addr_max_int : integer := 256);
32 port(
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
34 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
35 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
35 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
37 empty : out std_logic; --! Flag, M�moire vide
37 empty : out std_logic; --! Flag, M�moire vide
38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire
38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire
39 );
39 );
40 end Fifo_Read;
40 end Fifo_Read;
41
41
42 --! @details En aval de la SRAM Gaisler
42 --! @details En aval de la SRAM Gaisler
43
43
44 architecture ar_Fifo_Read of Fifo_Read is
44 architecture ar_Fifo_Read of Fifo_Read is
45
45
46 signal Rad_int : integer range 0 to addr_max_int;
46 signal Rad_int : integer range 0 to addr_max_int;
47 signal Rad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int_reg : integer range 0 to addr_max_int;
48 signal Wad_int : integer range 0 to addr_max_int;
48 signal Wad_int : integer range 0 to addr_max_int;
49 signal Wad_int_reg : integer range 0 to addr_max_int;
49 signal Wad_int_reg : integer range 0 to addr_max_int;
50 signal flag_reg : std_logic;
50 signal flag_reg : std_logic;
51
51
52 begin
52 begin
53 process (clk,raz)
53 process (clk,raz)
54 begin
54 begin
55 if(raz='0')then
55 if(raz='0')then
56 Rad_int <= 0;
56 Rad_int <= 0;
57 empty <= '1';
57 empty <= '1';
58 flag_reg <= '0';
58
59
59 elsif(clk' event and clk='1')then
60 elsif(clk' event and clk='1')then
60 Wad_int_reg <= Wad_int;
61 Wad_int_reg <= Wad_int;
61 Rad_int_reg <= Rad_int;
62 Rad_int_reg <= Rad_int;
62 flag_reg <= flag_RE;
63 flag_reg <= flag_RE;
63
64
64
65
65 if(flag_reg ='0' and flag_RE='1')then
66 if(flag_reg ='0' and flag_RE='1')then
66 if(Rad_int=addr_max_int-1)then
67 if(Rad_int=addr_max_int-1)then
67 Rad_int <= 0;
68 Rad_int <= 0;
68 else
69 else
69 Rad_int <= Rad_int+1;
70 Rad_int <= Rad_int+1;
70 end if;
71 end if;
71 end if;
72 end if;
72
73
73 if(ReUse='1')then
74 -- if(ReUse='1')then
74 empty <= '0';
75 -- empty <= '0';
75 else
76 -- else
76 if(Rad_int_reg /= Rad_int)then
77 if(Rad_int_reg /= Rad_int)then
77 if(Rad_int=Wad_int)then
78 if(Rad_int=Wad_int)then
78 empty <= '1';
79 empty <= '1';
79 else
80 else
80 empty <= '0';
81 empty <= '0';
81 end if;
82 end if;
82 elsif(Wad_int_reg /= Wad_int)then
83 elsif(Wad_int_reg /= Wad_int)then
83 empty <= '0';
84 empty <= '0';
84 end if;
85 end if;
85 end if;
86 end if;
86
87
87 end if;
88 -- end if;
88 end process;
89 end process;
89
90
90 Wad_int <= to_integer(unsigned(Waddr));
91 Wad_int <= to_integer(unsigned(Waddr));
91 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
92 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
92
93
93 end ar_Fifo_Read; No newline at end of file
94 end ar_Fifo_Read;
Show file before | Show file after | Hide comments
@@ -1,86 +1,89
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 --! Programme de la FIFO d'�criture
26 --! Programme de la FIFO d'�criture
27
27
28 entity Fifo_Write is
28 entity Fifo_Write is
29 generic(
29 generic(
30 Addr_sz : integer := 8;
30 Addr_sz : integer := 8;
31 addr_max_int : integer := 256);
31 addr_max_int : integer := 256);
32 port(
32 port(
33 clk,raz : in std_logic; --! Horloge et reset general du composant
33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
34 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
35 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
35 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
36 full : out std_logic; --! Flag, M�moire pleine
36 full : out std_logic; --! Flag, M�moire pleine
37 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire
37 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'�criture dans la m�moire
38 );
38 );
39 end Fifo_Write;
39 end Fifo_Write;
40
40
41 --! @details En amont de la SRAM Gaisler
41 --! @details En amont de la SRAM Gaisler
42
42
43 architecture ar_Fifo_Write of Fifo_Write is
43 architecture ar_Fifo_Write of Fifo_Write is
44
44
45 signal Wad_int : integer range 0 to addr_max_int;
45 signal Wad_int : integer range 0 to addr_max_int;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
46 signal Wad_int_reg : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
47 signal Rad_int : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
48 signal Rad_int_reg : integer range 0 to addr_max_int;
49 signal flag_reg : std_logic;
49
50
50 begin
51 begin
51 process (clk,raz)
52 process (clk,raz)
52 begin
53 begin
53 if(raz='0')then
54 if(raz='0')then
54 Wad_int <= 0;
55 Wad_int <= 0;
55 full <= '0';
56 full <= '0';
57 flag_reg <= '0';
56
58
57 elsif(clk' event and clk='1')then
59 elsif(clk' event and clk='1')then
58 Wad_int_reg <= Wad_int;
60 Wad_int_reg <= Wad_int;
59 Rad_int_reg <= Rad_int;
61 Rad_int_reg <= Rad_int;
62 flag_reg <= flag_WR;
60
63
61
64
62 if(flag_WR='1')then
65 if(flag_reg ='0' and flag_WR='1')then
63 if(Wad_int=addr_max_int-1)then
66 if(Wad_int=addr_max_int-1)then
64 Wad_int <= 0;
67 Wad_int <= 0;
65 else
68 else
66 Wad_int <= Wad_int+1;
69 Wad_int <= Wad_int+1;
67 end if;
70 end if;
68 end if;
71 end if;
69
72
70 if(Wad_int_reg /= Wad_int)then
73 if(Wad_int_reg /= Wad_int)then
71 if(Wad_int=Rad_int)then
74 if(Wad_int=Rad_int)then
72 full <= '1';
75 full <= '1';
73 else
76 else
74 full <= '0';
77 full <= '0';
75 end if;
78 end if;
76 elsif(Rad_int_reg /= Rad_int)then
79 elsif(Rad_int_reg /= Rad_int)then
77 full <= '0';
80 full <= '0';
78 end if;
81 end if;
79
82
80 end if;
83 end if;
81 end process;
84 end process;
82
85
83 Rad_int <= to_integer(unsigned(Raddr));
86 Rad_int <= to_integer(unsigned(Raddr));
84 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
87 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
85
88
86 end ar_Fifo_Write; No newline at end of file
89 end ar_Fifo_Write;
Show file before | Show file after | Hide comments
@@ -1,135 +1,149
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library techmap;
25 library techmap;
26 use techmap.gencomp.all;
26 use techmap.gencomp.all;
27 use work.config.all;
27 use work.config.all;
28 use lpp.lpp_memory.all;
28 use lpp.lpp_memory.all;
29
29
30 --! Programme de la FIFO
30 --! Programme de la FIFO
31
31
32 entity Top_FIFO is
32 entity Top_FIFO is
33 generic(
33 generic(
34 Data_sz : integer := 16;
34 Data_sz : integer := 16;
35 Addr_sz : integer := 8;
35 Addr_sz : integer := 8;
36 addr_max_int : integer := 256
36 addr_max_int : integer := 256
37 );
37 );
38 port(
38 port(
39 clk,raz : in std_logic; --! Horloge et reset general du composant
39 clk,raz : in std_logic; --! Horloge et reset general du composant
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
42 ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but
42 -- ReUse : in std_logic; --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
43 Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire
43 -- Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire
44 -- RstMem : in std_logic; --! Flag, Reset "manuel" sp�cifique au composant
44 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
45 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
45 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
46 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
46 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
47 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
47 full : out std_logic; --! Flag, M�moire pleine
48 full : out std_logic; --! Flag, M�moire pleine
48 empty : out std_logic; --! Flag, M�moire vide
49 empty : out std_logic; --! Flag, M�moire vide
49 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
50 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
50 );
51 );
51 end Top_FIFO;
52 end Top_FIFO;
52
53
53 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
54 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
54 --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire
55 --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire
55
56
56 architecture ar_Top_FIFO of Top_FIFO is
57 architecture ar_Top_FIFO of Top_FIFO is
57
58
58 component syncram_2p
59 component syncram_2p
59 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
60 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
60 port (
61 port (
61 rclk : in std_ulogic;
62 rclk : in std_ulogic;
62 renable : in std_ulogic;
63 renable : in std_ulogic;
63 raddress : in std_logic_vector((abits -1) downto 0);
64 raddress : in std_logic_vector((abits -1) downto 0);
64 dataout : out std_logic_vector((dbits -1) downto 0);
65 dataout : out std_logic_vector((dbits -1) downto 0);
65 wclk : in std_ulogic;
66 wclk : in std_ulogic;
66 write : in std_ulogic;
67 write : in std_ulogic;
67 waddress : in std_logic_vector((abits -1) downto 0);
68 waddress : in std_logic_vector((abits -1) downto 0);
68 datain : in std_logic_vector((dbits -1) downto 0));
69 datain : in std_logic_vector((dbits -1) downto 0));
69 end component;
70 end component;
70
71
71 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
72 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
72 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
73 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
73 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 signal s_empty : std_logic;
75 signal s_empty : std_logic;
75 signal s_full : std_logic;
76 signal s_full : std_logic;
76 signal s_full2 : std_logic;
77 --signal s_full2 : std_logic;
77 signal s_flag_RE : std_logic;
78 signal s_flag_RE : std_logic;
78 signal s_flag_WR : std_logic;
79 signal s_flag_WR : std_logic;
80 signal Flag_WR_reg : std_logic;
81 --signal rst : std_logic;
82 --signal RstMem_inv : std_logic;
79
83
80 begin
84 begin
81
85
86 --RstMem_inv <= not RstMem;
87 --rst <= raz and RstMem_inv;
88
82 WR : Fifo_Write
89 WR : Fifo_Write
83 generic map(Addr_sz,addr_max_int)
90 generic map(Addr_sz,addr_max_int)
84 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
91 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
85
92
86
93
87 SRAM : syncram_2p
94 SRAM : syncram_2p
88 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
95 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
89 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
96 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
90
97
91
98
92 -- link : Link_Reg
99 -- Pipe : Pipeline
93 -- generic map(Data_sz)
100 -- generic map(Data_sz)
94 -- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out);
101 -- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
95
102
96
103
97 RE : Fifo_Read
104 RE : Fifo_Read
98 generic map(Addr_sz,addr_max_int)
105 generic map(Addr_sz,addr_max_int)
99 port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr);
106 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
100
107
101 process(clk,raz)
108 process(clk,raz)
102 begin
109 begin
103 if(raz='0')then
110 if(raz='0')then
104 s_flag_RE <= '0';
111 s_flag_RE <= '0';
105 s_flag_WR <= '0';
112 s_flag_WR <= '0';
106 s_full2 <= s_full;
113 -- s_full2 <= s_full;
114 Flag_WR_reg <= '0';
107
115
108 elsif(clk'event and clk='1')then
116 elsif(clk'event and clk='1')then
109 if(s_full2='0')then
117 Flag_WR_reg <= Flag_WR;
118
119 if(s_full='0')then --2
120 if(s_empty='1')then
121 s_flag_WR <= Flag_WR_reg;
122 else
110 s_flag_WR <= Flag_WR;
123 s_flag_WR <= Flag_WR;
124 end if;
111 else
125 else
112 s_flag_WR <= '0';
126 s_flag_WR <= '0';
113 end if;
127 end if;
114
128
115 if(s_empty='0')then
129 if(s_empty='0')then
116 s_flag_RE <= Flag_RE;
130 s_flag_RE <= Flag_RE;
117 else
131 else
118 s_flag_RE <= '0';
132 s_flag_RE <= '0';
119 end if;
133 end if;
120
134
121 if(Lock='1')then
135 -- if(Lock='1')then
122 s_full2 <= '1';
136 -- s_full2 <= '1';
123 else
137 -- else
124 s_full2 <= s_full;
138 -- s_full2 <= s_full;
125 end if;
139 -- end if;
126
140
127 end if;
141 end if;
128 end process;
142 end process;
129
143
130 full <= s_full2;
144 full <= s_full; --2
131 empty <= s_empty;
145 empty <= s_empty;
132 Addr_RE <= Raddr;
146 Addr_RE <= Raddr;
133 Addr_WR <= Waddr;
147 Addr_WR <= Waddr;
134
148
135 end ar_Top_FIFO; No newline at end of file
149 end ar_Top_FIFO;
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@@ -1,250 +1,252
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_memory is
32 package lpp_memory is
33
33
34 --===========================================================|
34 --===========================================================|
35 --=================== FIFO Compl�te =========================|
35 --=================== FIFO Compl�te =========================|
36 --===========================================================|
36 --===========================================================|
37
37
38 component APB_FIFO is
38 component APB_FIFO is
39 generic (
39 generic (
40 pindex : integer := 0;
40 pindex : integer := 0;
41 paddr : integer := 0;
41 paddr : integer := 0;
42 pmask : integer := 16#fff#;
42 pmask : integer := 16#fff#;
43 pirq : integer := 0;
43 pirq : integer := 0;
44 abits : integer := 8;
44 abits : integer := 8;
45 Data_sz : integer := 16;
45 Data_sz : integer := 16;
46 Addr_sz : integer := 8;
46 Addr_sz : integer := 8;
47 addr_max_int : integer := 256);
47 addr_max_int : integer := 256);
48 port (
48 port (
49 clk : in std_logic;
49 clk : in std_logic;
50 rst : in std_logic;
50 rst : in std_logic;
51 apbi : in apb_slv_in_type;
51 apbi : in apb_slv_in_type;
52 Full : out std_logic;
52 Full : out std_logic;
53 Empty : out std_logic;
53 Empty : out std_logic;
54 WR : out std_logic;
54 WR : out std_logic;
55 RE : out std_logic;
55 RE : out std_logic;
56 apbo : out apb_slv_out_type
56 apbo : out apb_slv_out_type
57 );
57 );
58 end component;
58 end component;
59
59
60
60
61 component ApbDriver is
61 component ApbDriver is
62 generic (
62 generic (
63 pindex : integer := 0;
63 pindex : integer := 0;
64 paddr : integer := 0;
64 paddr : integer := 0;
65 pmask : integer := 16#fff#;
65 pmask : integer := 16#fff#;
66 pirq : integer := 0;
66 pirq : integer := 0;
67 abits : integer := 8;
67 abits : integer := 8;
68 LPP_DEVICE : integer;
68 LPP_DEVICE : integer;
69 Data_sz : integer := 16;
69 Data_sz : integer := 16;
70 Addr_sz : integer := 8;
70 Addr_sz : integer := 8;
71 addr_max_int : integer := 256);
71 addr_max_int : integer := 256);
72 port (
72 port (
73 clk : in std_logic;
73 clk : in std_logic;
74 rst : in std_logic;
74 rst : in std_logic;
75 ReadEnable : out std_logic;
75 ReadEnable : out std_logic;
76 WriteEnable : out std_logic;
76 WriteEnable : out std_logic;
77 FlagEmpty : in std_logic;
77 FlagEmpty : in std_logic;
78 FlagFull : in std_logic;
78 FlagFull : in std_logic;
79 ReUse : out std_logic;
79 -- ReUse : out std_logic;
80 Lock : out std_logic;
80 -- Lock : out std_logic;
81 -- RstMem : out std_logic;
81 DataIn : out std_logic_vector(Data_sz-1 downto 0);
82 DataIn : out std_logic_vector(Data_sz-1 downto 0);
82 DataOut : in std_logic_vector(Data_sz-1 downto 0);
83 DataOut : in std_logic_vector(Data_sz-1 downto 0);
83 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
84 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
84 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
85 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
85 apbi : in apb_slv_in_type;
86 apbi : in apb_slv_in_type;
86 apbo : out apb_slv_out_type
87 apbo : out apb_slv_out_type
87 );
88 );
88 end component;
89 end component;
89
90
90
91
91 component Top_FIFO is
92 component Top_FIFO is
92 generic(
93 generic(
93 Data_sz : integer := 16;
94 Data_sz : integer := 16;
94 Addr_sz : integer := 8;
95 Addr_sz : integer := 8;
95 addr_max_int : integer := 256
96 addr_max_int : integer := 256
96 );
97 );
97 port(
98 port(
98 clk,raz : in std_logic;
99 clk,raz : in std_logic;
99 flag_RE : in std_logic;
100 flag_RE : in std_logic;
100 flag_WR : in std_logic;
101 flag_WR : in std_logic;
101 ReUse : in std_logic;
102 -- ReUse : in std_logic;
102 Lock : in std_logic;
103 -- Lock : in std_logic;
104 -- RstMem : in std_logic;
103 Data_in : in std_logic_vector(Data_sz-1 downto 0);
105 Data_in : in std_logic_vector(Data_sz-1 downto 0);
104 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
106 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
105 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
107 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
106 full : out std_logic;
108 full : out std_logic;
107 empty : out std_logic;
109 empty : out std_logic;
108 Data_out : out std_logic_vector(Data_sz-1 downto 0)
110 Data_out : out std_logic_vector(Data_sz-1 downto 0)
109 );
111 );
110 end component;
112 end component;
111
113
112
114
113 component Fifo_Read is
115 component Fifo_Read is
114 generic(
116 generic(
115 Addr_sz : integer := 8;
117 Addr_sz : integer := 8;
116 addr_max_int : integer := 256);
118 addr_max_int : integer := 256);
117 port(
119 port(
118 clk : in std_logic;
120 clk : in std_logic;
119 raz : in std_logic;
121 raz : in std_logic;
120 flag_RE : in std_logic;
122 flag_RE : in std_logic;
121 ReUse : in std_logic;
123 -- ReUse : in std_logic;
122 Waddr : in std_logic_vector(addr_sz-1 downto 0);
124 Waddr : in std_logic_vector(addr_sz-1 downto 0);
123 empty : out std_logic;
125 empty : out std_logic;
124 Raddr : out std_logic_vector(addr_sz-1 downto 0)
126 Raddr : out std_logic_vector(addr_sz-1 downto 0)
125 );
127 );
126 end component;
128 end component;
127
129
128
130
129 component Fifo_Write is
131 component Fifo_Write is
130 generic(
132 generic(
131 Addr_sz : integer := 8;
133 Addr_sz : integer := 8;
132 addr_max_int : integer := 256);
134 addr_max_int : integer := 256);
133 port(
135 port(
134 clk : in std_logic;
136 clk : in std_logic;
135 raz : in std_logic;
137 raz : in std_logic;
136 flag_WR : in std_logic;
138 flag_WR : in std_logic;
137 Raddr : in std_logic_vector(addr_sz-1 downto 0);
139 Raddr : in std_logic_vector(addr_sz-1 downto 0);
138 full : out std_logic;
140 full : out std_logic;
139 Waddr : out std_logic_vector(addr_sz-1 downto 0)
141 Waddr : out std_logic_vector(addr_sz-1 downto 0)
140 );
142 );
141 end component;
143 end component;
142
144
143
145
144 component Link_Reg is
146 component Pipeline is
145 generic(Data_sz : integer := 16);
147 generic(Data_sz : integer := 16);
146 port(
148 port(
147 clk,raz : in std_logic;
149 clk,raz : in std_logic;
148 Data_one : in std_logic_vector(Data_sz-1 downto 0);
150 Data_one : in std_logic_vector(Data_sz-1 downto 0);
149 Data_two : in std_logic_vector(Data_sz-1 downto 0);
151 Data_two : in std_logic_vector(Data_sz-1 downto 0);
150 ReUse : in std_logic;
152 -- ReUse : in std_logic;
151 flag_RE : in std_logic;
153 flag_RE : in std_logic;
152 flag_WR : in std_logic;
154 flag_WR : in std_logic;
153 empty : in std_logic;
155 empty : in std_logic;
154 Data_out : out std_logic_vector(Data_sz-1 downto 0)
156 Data_out : out std_logic_vector(Data_sz-1 downto 0)
155 );
157 );
156 end component;
158 end component;
157
159
158 --===========================================================|
160 --===========================================================|
159 --================= Demi FIFO Ecriture ======================|
161 --================= Demi FIFO Ecriture ======================|
160 --===========================================================|
162 --===========================================================|
161
163
162 component APB_FifoWrite is
164 component APB_FifoWrite is
163 generic (
165 generic (
164 pindex : integer := 0;
166 pindex : integer := 0;
165 paddr : integer := 0;
167 paddr : integer := 0;
166 pmask : integer := 16#fff#;
168 pmask : integer := 16#fff#;
167 pirq : integer := 0;
169 pirq : integer := 0;
168 abits : integer := 8;
170 abits : integer := 8;
169 Data_sz : integer := 16;
171 Data_sz : integer := 16;
170 Addr_sz : integer := 8;
172 Addr_sz : integer := 8;
171 addr_max_int : integer := 256);
173 addr_max_int : integer := 256);
172 port (
174 port (
173 clk : in std_logic;
175 clk : in std_logic;
174 rst : in std_logic;
176 rst : in std_logic;
175 apbi : in apb_slv_in_type;
177 apbi : in apb_slv_in_type;
176 ReadEnable : in std_logic;
178 ReadEnable : in std_logic;
177 Empty : out std_logic;
179 Empty : out std_logic;
178 Full : out std_logic;
180 Full : out std_logic;
179 DATA : out std_logic_vector(Data_sz-1 downto 0);
181 DATA : out std_logic_vector(Data_sz-1 downto 0);
180 apbo : out apb_slv_out_type
182 apbo : out apb_slv_out_type
181 );
183 );
182 end component;
184 end component;
183
185
184
186
185 --component Top_FifoWrite is
187 --component Top_FifoWrite is
186 -- generic(
188 -- generic(
187 -- Data_sz : integer := 16;
189 -- Data_sz : integer := 16;
188 -- Addr_sz : integer := 8;
190 -- Addr_sz : integer := 8;
189 -- addr_max_int : integer := 256);
191 -- addr_max_int : integer := 256);
190 -- port(
192 -- port(
191 -- clk : in std_logic;
193 -- clk : in std_logic;
192 -- raz : in std_logic;
194 -- raz : in std_logic;
193 -- flag_RE : in std_logic;
195 -- flag_RE : in std_logic;
194 -- flag_WR : in std_logic;
196 -- flag_WR : in std_logic;
195 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
197 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
196 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
198 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
197 -- full : out std_logic;
199 -- full : out std_logic;
198 -- empty : out std_logic;
200 -- empty : out std_logic;
199 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
201 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
200 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
202 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
201 -- );
203 -- );
202 --end component;
204 --end component;
203
205
204 --===========================================================|
206 --===========================================================|
205 --================== Demi FIFO Lecture ======================|
207 --================== Demi FIFO Lecture ======================|
206 --===========================================================|
208 --===========================================================|
207
209
208 component APB_FifoRead is
210 component APB_FifoRead is
209 generic (
211 generic (
210 pindex : integer := 0;
212 pindex : integer := 0;
211 paddr : integer := 0;
213 paddr : integer := 0;
212 pmask : integer := 16#fff#;
214 pmask : integer := 16#fff#;
213 pirq : integer := 0;
215 pirq : integer := 0;
214 abits : integer := 8;
216 abits : integer := 8;
215 Data_sz : integer := 16;
217 Data_sz : integer := 16;
216 Addr_sz : integer := 8;
218 Addr_sz : integer := 8;
217 addr_max_int : integer := 256);
219 addr_max_int : integer := 256);
218 port (
220 port (
219 clk : in std_logic;
221 clk : in std_logic;
220 rst : in std_logic;
222 rst : in std_logic;
221 apbi : in apb_slv_in_type;
223 apbi : in apb_slv_in_type;
222 WriteEnable : in std_logic;
224 WriteEnable : in std_logic;
223 Full : out std_logic;
225 Full : out std_logic;
224 Empty : out std_logic;
226 Empty : out std_logic;
225 DATA : in std_logic_vector(Data_sz-1 downto 0);
227 DATA : in std_logic_vector(Data_sz-1 downto 0);
226 apbo : out apb_slv_out_type
228 apbo : out apb_slv_out_type
227 );
229 );
228 end component;
230 end component;
229
231
230
232
231 --component Top_FifoRead is
233 --component Top_FifoRead is
232 -- generic(
234 -- generic(
233 -- Data_sz : integer := 16;
235 -- Data_sz : integer := 16;
234 -- Addr_sz : integer := 8;
236 -- Addr_sz : integer := 8;
235 -- addr_max_int : integer := 256);
237 -- addr_max_int : integer := 256);
236 -- port(
238 -- port(
237 -- clk : in std_logic;
239 -- clk : in std_logic;
238 -- raz : in std_logic;
240 -- raz : in std_logic;
239 -- flag_RE : in std_logic;
241 -- flag_RE : in std_logic;
240 -- flag_WR : in std_logic;
242 -- flag_WR : in std_logic;
241 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
243 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
242 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
244 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
243 -- full : out std_logic;
245 -- full : out std_logic;
244 -- empty : out std_logic;
246 -- empty : out std_logic;
245 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
247 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
246 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
248 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
247 -- );
249 -- );
248 --end component;
250 --end component;
249
251
250 end;
252 end;
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