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WaveFormPicker :...
pellion -
r276:05c1cc175dfc LPP-LFR-em-WaveFormPicker-0-0-8 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_waveform_fifo_headreg IS
34 GENERIC(
35 tech : INTEGER := 0
36 );
37 PORT(
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
42 ---------------------------------------------------------------------------
43 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
44 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
47 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
48 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
49 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
50 ---------------------------------------------------------------------------
51 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
54 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 );
56 END ENTITY;
57
58
59 ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS
60 SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL one_ren_and_notEmpty : STD_LOGIC;
64 SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
66 SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 BEGIN
71
72 -----------------------------------------------------------------------------
73 -- DATA_REN_FIFO
74 -----------------------------------------------------------------------------
75 i_data_ren <= s_ren;
76 PROCESS (clk, rstn)
77 BEGIN
78 IF rstn = '0' THEN
79 s_ren_reg <= (OTHERS => '1');
80 ELSIF clk'EVENT AND clk = '1' THEN
81 s_ren_reg <= s_ren;
82 END IF;
83 END PROCESS;
84
85 s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
86 NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
87 s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
88 '1' WHEN s_ren(0) = '0' ELSE
89 NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
90 s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
91 '1' WHEN s_ren(0) = '0' ELSE
92 '1' WHEN s_ren(1) = '0' ELSE
93 NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
94 s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
95 '1' WHEN s_ren(0) = '0' ELSE
96 '1' WHEN s_ren(1) = '0' ELSE
97 '1' WHEN s_ren(2) = '0' ELSE
98 NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
99 -----------------------------------------------------------------------------
100 all_ren : FOR I IN 3 DOWNTO 0 GENERATE
101 ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
102 END GENERATE all_ren;
103 one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
104
105 -----------------------------------------------------------------------------
106 -- DATA
107 -----------------------------------------------------------------------------
108 o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
109 o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
110 o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
111 o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
112
113 PROCESS (clk, rstn)
114 BEGIN
115 IF rstn = '0' THEN
116 s_rdata_0 <= (OTHERS => '0');
117 s_rdata_1 <= (OTHERS => '0');
118 s_rdata_2 <= (OTHERS => '0');
119 s_rdata_3 <= (OTHERS => '0');
120 ELSIF clk'EVENT AND clk = '1' THEN
121 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
122 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
123 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
124 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
125 END IF;
126 END PROCESS;
127
128 all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
129 PROCESS (clk, rstn)
130 BEGIN
131 IF rstn = '0' THEN
132 reg_full(I) <= '0';
133 ELSIF clk'EVENT AND clk = '1' THEN
134 -- IF s_ren_reg(I) = '0' THEN
135 IF s_ren(I) = '0' THEN
136 reg_full(I) <= '1';
137 ELSIF o_data_ren(I) = '0' THEN
138 reg_full(I) <= '0';
139 END IF;
140 END IF;
141 END PROCESS;
142 END GENERATE all_reg_full;
143
144 -----------------------------------------------------------------------------
145 -- EMPTY
146 -----------------------------------------------------------------------------
147 o_empty <= NOT reg_full;
148
149 -----------------------------------------------------------------------------
150 -- EMPTY_ALMOST
151 -----------------------------------------------------------------------------
152 o_empty_almost <= s_empty_almost;
153
154 all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
155 PROCESS (clk, rstn)
156 BEGIN -- PROCESS
157 IF rstn = '0' THEN -- asynchronous reset (active low)
158 s_empty_almost(I) <= '1';
159 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
160 -- IF s_ren_reg(I) = '0' THEN
161 IF s_ren(I) = '0' THEN
162 s_empty_almost(I) <= i_empty_almost(I);
163 ELSIF o_data_ren(I) = '0' THEN
164 s_empty_almost(I) <= '1';
165 ELSE
166 IF i_empty_almost(I) = '0' THEN
167 s_empty_almost(I) <= '0';
168 END IF;
169 END IF;
170 END IF;
171 END PROCESS;
172 END GENERATE all_empty_almost;
173
174 END ARCHITECTURE;
175
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@@ -499,7 +499,7 BEGIN
499 pirq_ms => 6,
499 pirq_ms => 6,
500 pirq_wfp => 14,
500 pirq_wfp => 14,
501 hindex => 2,
501 hindex => 2,
502 top_lfr_version => X"00000007")
502 top_lfr_version => X"00000008")
503 PORT MAP (
503 PORT MAP (
504 clk => clkm,
504 clk => clkm,
505 rstn => rstn,
505 rstn => rstn,
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@@ -176,25 +176,19 BEGIN -- beh
176 IO5 <= '0';
176 IO5 <= '0';
177 IO6 <= '0';
177 IO6 <= '0';
178 IO7 <= '0';
178 IO7 <= '0';
179 IO8 <= '0';
179 IO8 <= '1';
180 IO9 <= '0';
181 IO10 <= '0';
182 IO11 <= '0';
183 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
180 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
184 LED0 <= '0';
181 LED0 <= '0';
185 LED1 <= '1';
182 LED1 <= '1';
186 LED2 <= BP0;
183 LED2 <= BP0;
187 IO1 <= '1';
184 IO1 <= '1';
188 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
185 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
189 IO3 <= ADC_SDO(0);
186 IO3 <= ADC_SDO(0) OR ADC_SDO(1);
190 IO4 <= ADC_SDO(1);
187 IO4 <= ADC_SDO(2) OR ADC_SDO(1);
191 IO5 <= ADC_SDO(2);
188 IO5 <= ADC_SDO(3) OR ADC_SDO(4);
192 IO6 <= ADC_SDO(3);
189 IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
193 IO7 <= ADC_SDO(4);
190 IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
194 IO8 <= ADC_SDO(5);
191 IO8 <= '0';
195 IO9 <= ADC_SDO(6);
196 IO10 <= ADC_SDO(7);
197 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
198 END IF;
192 END IF;
199 END PROCESS;
193 END PROCESS;
200
194
@@ -239,7 +233,11 BEGIN -- beh
239 ahbmi => ahbi_m_ext ,
233 ahbmi => ahbi_m_ext ,
240 ahbmo => ahbo_m_ext(1),
234 ahbmo => ahbo_m_ext(1),
241 apbi => apbi_ext,
235 apbi => apbi_ext,
242 apbo => apbo_ext(5));
236 apbo => apbo_ext(5),
237 out_ren => IO11,
238 out_send => IO10,
239 out_done => IO9
240 );
243
241
244 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
245
243
@@ -289,4 +287,4 BEGIN -- beh
289 ahbi_m_ext => ahbi_m_ext,
287 ahbi_m_ext => ahbi_m_ext,
290 ahbo_m_ext => ahbo_m_ext);
288 ahbo_m_ext => ahbo_m_ext);
291
289
292 END beh; No newline at end of file
290 END beh;
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@@ -59,7 +59,11 ENTITY lpp_debug_dma_singleOrBurst IS
59 ahbmo : OUT AHB_Mst_Out_Type;
59 ahbmo : OUT AHB_Mst_Out_Type;
60 -- AMBA AHB Master Interface
60 -- AMBA AHB Master Interface
61 apbi : IN apb_slv_in_type;
61 apbi : IN apb_slv_in_type;
62 apbo : OUT apb_slv_out_type
62 apbo : OUT apb_slv_out_type;
63 -- observation SIGNAL
64 out_ren : OUT STD_LOGIC;
65 out_send : OUT STD_LOGIC;
66 out_done : OUT STD_LOGIC
63 );
67 );
64 END;
68 END;
65
69
@@ -94,6 +98,9 ARCHITECTURE Behavioral OF lpp_debug_dma
94 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
95
99
96 BEGIN
100 BEGIN
101 out_ren <= ren;
102 out_send <= send;
103 out_done <= done;
97
104
98 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
105 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
99 GENERIC MAP (
106 GENERIC MAP (
@@ -174,7 +181,7 BEGIN
174 reg.ren <= apbi.pwdata(4);
181 reg.ren <= apbi.pwdata(4);
175 WHEN "000001" => reg.addr <= apbi.pwdata;
182 WHEN "000001" => reg.addr <= apbi.pwdata;
176 WHEN "000010" => reg.data <= apbi.pwdata;
183 WHEN "000010" => reg.data <= apbi.pwdata;
177 WHEN "000011" => reg.nb_ren <= apbi.pwdata;
184 --WHEN "000011" => reg.nb_ren <= apbi.pwdata;
178 WHEN OTHERS => NULL;
185 WHEN OTHERS => NULL;
179 END CASE;
186 END CASE;
180 END IF;
187 END IF;
@@ -189,4 +196,4 BEGIN
189
196
190
197
191
198
192 END Behavioral; No newline at end of file
199 END Behavioral;
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@@ -40,7 +40,10 PACKAGE lpp_debug_lfr_pkg IS
40 ahbmi : IN AHB_Mst_In_Type;
40 ahbmi : IN AHB_Mst_In_Type;
41 ahbmo : OUT AHB_Mst_Out_Type;
41 ahbmo : OUT AHB_Mst_Out_Type;
42 apbi : IN apb_slv_in_type;
42 apbi : IN apb_slv_in_type;
43 apbo : OUT apb_slv_out_type);
43 apbo : OUT apb_slv_out_type;
44 out_ren : OUT STD_LOGIC;
45 out_send : OUT STD_LOGIC;
46 out_done : OUT STD_LOGIC );
44 END COMPONENT;
47 END COMPONENT;
45
48
46 END;
49 END;
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@@ -167,10 +167,17 BEGIN -- beh
167
167
168 DMAIn.Data <= data;
168 DMAIn.Data <= data;
169
169
170 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
171 '1';
172 -- \/ JC - 10/12/2013 \/
170 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
173 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
171 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
174 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
172 -- '1';
175 -- '1';
173 ren <= '0' WHEN state = SEND_DATA ELSE
176 -- /\ JC - 10/12/2013 /\
174 '1';
177
178 -- \/ JC - 09/12/2013 \/
179 --ren <= '0' WHEN state = SEND_DATA ELSE
180 -- '1';
181 -- /\ JC - 09/12/2013 /\
175
182
176 END beh;
183 END beh;
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@@ -39,7 +39,7 ENTITY lpp_lfr IS
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
@@ -354,10 +354,10 BEGIN
354 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
354 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
355 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
355 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
356 -----------------------------------------------------------------------------
356 -----------------------------------------------------------------------------
357 sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
357 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
358 sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
358 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
359 sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
359 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
360 sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
360 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
361
361
362
362
363 -----------------------------------------------------------------------------
363 -----------------------------------------------------------------------------
@@ -405,19 +405,19 BEGIN
405 --f0
405 --f0
406 addr_data_f0 => addr_data_f0,
406 addr_data_f0 => addr_data_f0,
407 data_f0_in_valid => sample_f0_val,
407 data_f0_in_valid => sample_f0_val,
408 data_f0_in => sample_f0_data_debug, -- TODO : debug
408 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
409 --f1
409 --f1
410 addr_data_f1 => addr_data_f1,
410 addr_data_f1 => addr_data_f1,
411 data_f1_in_valid => sample_f1_val,
411 data_f1_in_valid => sample_f1_val,
412 data_f1_in => sample_f1_data_debug, -- TODO : debug,
412 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
413 --f2
413 --f2
414 addr_data_f2 => addr_data_f2,
414 addr_data_f2 => addr_data_f2,
415 data_f2_in_valid => sample_f2_val,
415 data_f2_in_valid => sample_f2_val,
416 data_f2_in => sample_f2_data_debug, -- TODO : debug,
416 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
417 --f3
417 --f3
418 addr_data_f3 => addr_data_f3,
418 addr_data_f3 => addr_data_f3,
419 data_f3_in_valid => sample_f3_val,
419 data_f3_in_valid => sample_f3_val,
420 data_f3_in => sample_f3_data_debug, -- TODO : debug,
420 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
421 -- OUTPUT -- DMA interface
421 -- OUTPUT -- DMA interface
422 --f0
422 --f0
423 data_f0_addr_out => data_f0_addr_out_s,
423 data_f0_addr_out => data_f0_addr_out_s,
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@@ -180,14 +180,14 PACKAGE lpp_lfr_pkg IS
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 ---------------------------------------------------------------------------
182 ---------------------------------------------------------------------------
183 debug_reg0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
190 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
191 END COMPONENT;
191 END COMPONENT;
192
192
193 COMPONENT lpp_top_ms
193 COMPONENT lpp_top_ms
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@@ -186,6 +186,12 ARCHITECTURE beh OF lpp_waveform IS
186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 --
190
191 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
192 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
189
195
190 BEGIN -- beh
196 BEGIN -- beh
191
197
@@ -295,7 +301,7 BEGIN -- beh
295 IF rstn = '0' THEN -- asynchronous reset (active low)
301 IF rstn = '0' THEN -- asynchronous reset (active low)
296 time_reg1 <= (OTHERS => '0');
302 time_reg1 <= (OTHERS => '0');
297 time_reg2 <= (OTHERS => '0');
303 time_reg2 <= (OTHERS => '0');
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
304 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
299 time_reg1 <= fine_time & coarse_time;
305 time_reg1 <= fine_time & coarse_time;
300 time_reg2 <= time_reg1;
306 time_reg2 <= time_reg1;
301 END IF;
307 END IF;
@@ -326,22 +332,24 BEGIN -- beh
326 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
327 -- TODO : debug
333 -- TODO : debug
328 -----------------------------------------------------------------------------
334 -----------------------------------------------------------------------------
335 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
336 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
337 time_out_2(J,I) <= time_out(J)(I);
338 END GENERATE all_sample_of_time_out;
339 END GENERATE all_bit_of_time_out;
340
341 -- DEBUG --
342 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
343 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
344 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
345 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
346
329 --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
347 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
330 -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
348 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
331 -- time_out_2(J,I) <= time_out(J)(I);
349 -- time_out_2(J, I) <= time_out_debug(J)(I);
332 -- END GENERATE all_sample_of_time_out;
350 -- END GENERATE all_sample_of_time_out;
333 --END GENERATE all_bit_of_time_out;
351 --END GENERATE all_bit_of_time_out;
334
352 -- DEBUG --
335 time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
336 time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
337 time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
338 time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
339
340 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
341 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
342 time_out_2(J,I) <= time_out_debug(J)(I);
343 END GENERATE all_sample_of_time_out;
344 END GENERATE all_bit_of_time_out;
345
353
346 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
354 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
347 GENERIC MAP (tech => tech,
355 GENERIC MAP (tech => tech,
@@ -368,11 +376,10 BEGIN -- beh
368 rstn => rstn,
376 rstn => rstn,
369 run => run,
377 run => run,
370
378
371 empty => empty,
379 empty => s_empty,
372 empty_almost => empty_almost,
380 empty_almost => s_empty_almost,
373
381 data_ren => s_data_ren,
374 data_ren => data_ren,
382 rdata => s_rdata,
375 rdata => rdata,
376
383
377
384
378 full_almost => full_almost,
385 full_almost => full_almost,
@@ -380,10 +387,31 BEGIN -- beh
380 data_wen => data_wen,
387 data_wen => data_wen,
381 wdata => wdata);
388 wdata => wdata);
382
389
383 data_f0_data_out <= rdata;
390 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
384 data_f1_data_out <= rdata;
391 GENERIC MAP (tech => tech)
385 data_f2_data_out <= rdata;
392 PORT MAP (
386 data_f3_data_out <= rdata;
393 clk => clk,
394 rstn => rstn,
395 run => run,
396 o_empty_almost => empty_almost,
397 o_empty => empty,
398
399 o_data_ren => data_ren,
400 o_rdata_0 => data_f0_data_out,
401 o_rdata_1 => data_f1_data_out,
402 o_rdata_2 => data_f2_data_out,
403 o_rdata_3 => data_f3_data_out,
404
405 i_empty_almost => s_empty_almost,
406 i_empty => s_empty,
407 i_data_ren => s_data_ren,
408 i_rdata => s_rdata);
409
410
411 --data_f0_data_out <= rdata;
412 --data_f1_data_out <= rdata;
413 --data_f2_data_out <= rdata;
414 --data_f3_data_out <= rdata;
387
415
388 data_ren <= data_f3_data_out_ren &
416 data_ren <= data_f3_data_out_ren &
389 data_f2_data_out_ren &
417 data_f2_data_out_ren &
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@@ -251,6 +251,26 PACKAGE lpp_waveform_pkg IS
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
252 END COMPONENT;
252 END COMPONENT;
253
253
254 COMPONENT lpp_waveform_fifo_headreg
255 GENERIC (
256 tech : INTEGER);
257 PORT (
258 clk : IN STD_LOGIC;
259 rstn : IN STD_LOGIC;
260 run : IN STD_LOGIC;
261 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
263 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
264 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
266 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
267 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
268 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
269 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
270 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
271 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
272 END COMPONENT;
273
254 COMPONENT lpp_waveform_fifo_latencyCorrection
274 COMPONENT lpp_waveform_fifo_latencyCorrection
255 GENERIC (
275 GENERIC (
256 tech : INTEGER);
276 tech : INTEGER);
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@@ -6,6 +6,7 lpp_waveform_fifo_latencyCorrection.vhd
6 lpp_waveform_fifo.vhd
6 lpp_waveform_fifo.vhd
7 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_arbiter.vhd
8 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo_ctrl.vhd
9 lpp_waveform_fifo_headreg.vhd
9 lpp_waveform_snapshot.vhd
10 lpp_waveform_snapshot.vhd
10 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_genaddress.vhd
12 lpp_waveform_genaddress.vhd
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