diff --git a/designs/LFR-em-WaveFormPicker/leon3mp.vhd b/designs/LFR-em-WaveFormPicker/leon3mp.vhd --- a/designs/LFR-em-WaveFormPicker/leon3mp.vhd +++ b/designs/LFR-em-WaveFormPicker/leon3mp.vhd @@ -499,7 +499,7 @@ BEGIN pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00000007") + top_lfr_version => X"00000008") PORT MAP ( clk => clkm, rstn => rstn, diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -176,25 +176,19 @@ BEGIN -- beh IO5 <= '0'; IO6 <= '0'; IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; + IO8 <= '1'; ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge LED0 <= '0'; LED1 <= '1'; LED2 <= BP0; IO1 <= '1'; IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - IO3 <= ADC_SDO(0); - IO4 <= ADC_SDO(1); - IO5 <= ADC_SDO(2); - IO6 <= ADC_SDO(3); - IO7 <= ADC_SDO(4); - IO8 <= ADC_SDO(5); - IO9 <= ADC_SDO(6); - IO10 <= ADC_SDO(7); - IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + IO3 <= ADC_SDO(0) OR ADC_SDO(1); + IO4 <= ADC_SDO(2) OR ADC_SDO(1); + IO5 <= ADC_SDO(3) OR ADC_SDO(4); + IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); + IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + IO8 <= '0'; END IF; END PROCESS; @@ -239,7 +233,11 @@ BEGIN -- beh ahbmi => ahbi_m_ext , ahbmo => ahbo_m_ext(1), apbi => apbi_ext, - apbo => apbo_ext(5)); + apbo => apbo_ext(5), + out_ren => IO11, + out_send => IO10, + out_done => IO9 + ); ----------------------------------------------------------------------------- @@ -263,7 +261,7 @@ BEGIN -- beh ENABLE_GPT => 1, NB_AHB_MASTER => NB_AHB_MASTER, NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) + NB_APB_SLAVE => NB_APB_SLAVE) PORT MAP ( clk => clk_25, reset => reset, @@ -289,4 +287,4 @@ BEGIN -- beh ahbi_m_ext => ahbi_m_ext, ahbo_m_ext => ahbo_m_ext); -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd b/lib/lpp/lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd --- a/lib/lpp/lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd +++ b/lib/lpp/lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd @@ -59,7 +59,11 @@ ENTITY lpp_debug_dma_singleOrBurst IS ahbmo : OUT AHB_Mst_Out_Type; -- AMBA AHB Master Interface apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type + apbo : OUT apb_slv_out_type; + -- observation SIGNAL + out_ren : OUT STD_LOGIC; + out_send : OUT STD_LOGIC; + out_done : OUT STD_LOGIC ); END; @@ -94,6 +98,9 @@ ARCHITECTURE Behavioral OF lpp_debug_dma SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN + out_ren <= ren; + out_send <= send; + out_done <= done; lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst GENERIC MAP ( @@ -130,7 +137,7 @@ BEGIN reg.ren <= '0'; reg.addr <= (OTHERS => '0'); reg.data <= (OTHERS => '0'); - reg.nb_ren <= (OTHERS => '0'); + reg.nb_ren <= (OTHERS => '0'); apbo.pirq <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge @@ -167,14 +174,14 @@ BEGIN -- APB DMA WRITE -- CASE paddr(7 DOWNTO 2) IS -- - WHEN "000000" => reg.run <= apbi.pwdata(0); + WHEN "000000" => reg.run <= apbi.pwdata(0); reg.send <= apbi.pwdata(1); reg.valid_burst <= apbi.pwdata(2); reg.done <= apbi.pwdata(3); reg.ren <= apbi.pwdata(4); WHEN "000001" => reg.addr <= apbi.pwdata; WHEN "000010" => reg.data <= apbi.pwdata; - WHEN "000011" => reg.nb_ren <= apbi.pwdata; + --WHEN "000011" => reg.nb_ren <= apbi.pwdata; WHEN OTHERS => NULL; END CASE; END IF; @@ -189,4 +196,4 @@ BEGIN -END Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd b/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd --- a/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd +++ b/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd @@ -40,7 +40,10 @@ PACKAGE lpp_debug_lfr_pkg IS ahbmi : IN AHB_Mst_In_Type; ahbmo : OUT AHB_Mst_Out_Type; apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type); + apbo : OUT apb_slv_out_type; + out_ren : OUT STD_LOGIC; + out_send : OUT STD_LOGIC; + out_done : OUT STD_LOGIC ); END COMPONENT; END; diff --git a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd @@ -167,10 +167,17 @@ BEGIN -- beh DMAIn.Data <= data; + ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + '1'; + -- \/ JC - 10/12/2013 \/ --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE -- '1'; - ren <= '0' WHEN state = SEND_DATA ELSE - '1'; + -- /\ JC - 10/12/2013 /\ + + -- \/ JC - 09/12/2013 \/ + --ren <= '0' WHEN state = SEND_DATA ELSE + -- '1'; + -- /\ JC - 09/12/2013 /\ END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -39,7 +39,7 @@ ENTITY lpp_lfr IS hindex : INTEGER := 2; - top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) + top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0') ); PORT ( @@ -354,10 +354,10 @@ BEGIN debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); ----------------------------------------------------------------------------- - sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug - sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug - sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug - sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug + --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug + --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug + --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug + --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug ----------------------------------------------------------------------------- @@ -405,19 +405,19 @@ BEGIN --f0 addr_data_f0 => addr_data_f0, data_f0_in_valid => sample_f0_val, - data_f0_in => sample_f0_data_debug, -- TODO : debug + data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug --f1 addr_data_f1 => addr_data_f1, data_f1_in_valid => sample_f1_val, - data_f1_in => sample_f1_data_debug, -- TODO : debug, + data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, --f2 addr_data_f2 => addr_data_f2, data_f2_in_valid => sample_f2_val, - data_f2_in => sample_f2_data_debug, -- TODO : debug, + data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, --f3 addr_data_f3 => addr_data_f3, data_f3_in_valid => sample_f3_val, - data_f3_in => sample_f3_data_debug, -- TODO : debug, + data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, -- OUTPUT -- DMA interface --f0 data_f0_addr_out => data_f0_addr_out_s, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -180,14 +180,14 @@ PACKAGE lpp_lfr_pkg IS addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); --------------------------------------------------------------------------- - debug_reg0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; COMPONENT lpp_top_ms diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -39,13 +39,13 @@ USE techmap.gencomp.ALL; ENTITY lpp_waveform IS GENERIC ( - tech : INTEGER := inferred; - data_size : INTEGER := 96; --16*6 - nb_data_by_buffer_size : INTEGER := 11; - nb_word_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3); + tech : INTEGER := inferred; + data_size : INTEGER := 96; --16*6 + nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3); PORT ( clk : IN STD_LOGIC; @@ -75,32 +75,32 @@ ENTITY lpp_waveform IS nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma --------------------------------------------------------------------------- -- INPUT - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); --f0 - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f0_in_valid : IN STD_LOGIC; - data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f1 - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_in_valid : IN STD_LOGIC; - data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_in_valid : IN STD_LOGIC; + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f2 - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_in_valid : IN STD_LOGIC; - data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_in_valid : IN STD_LOGIC; + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --f3 - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_in_valid : IN STD_LOGIC; - data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_in_valid : IN STD_LOGIC; + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); --------------------------------------------------------------------------- -- OUTPUT @@ -109,35 +109,35 @@ ENTITY lpp_waveform IS data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f0_data_out_valid : OUT STD_LOGIC; data_f0_data_out_valid_burst : OUT STD_LOGIC; - data_f0_data_out_ren : IN STD_LOGIC; + data_f0_data_out_ren : IN STD_LOGIC; --f1 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f1_data_out_valid : OUT STD_LOGIC; data_f1_data_out_valid_burst : OUT STD_LOGIC; - data_f1_data_out_ren : IN STD_LOGIC; + data_f1_data_out_ren : IN STD_LOGIC; --f2 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f2_data_out_valid : OUT STD_LOGIC; data_f2_data_out_valid_burst : OUT STD_LOGIC; - data_f2_data_out_ren : IN STD_LOGIC; + data_f2_data_out_ren : IN STD_LOGIC; --f3 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_data_out_valid : OUT STD_LOGIC; data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC; + data_f3_data_out_ren : IN STD_LOGIC; --debug - debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f0_data_valid : OUT STD_LOGIC; - debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f1_data_valid : OUT STD_LOGIC; - debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f2_data_valid : OUT STD_LOGIC; - debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC + debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC ); END lpp_waveform; @@ -167,10 +167,10 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); -- SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -179,13 +179,19 @@ ARCHITECTURE beh OF lpp_waveform IS -- SIGNAL run : STD_LOGIC; -- - TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); - SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); - SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); - SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug - SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); + SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug + SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + -- + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN -- beh @@ -228,7 +234,7 @@ BEGIN -- beh data_in_valid => data_f0_in_valid, data_out => data_f0_out, data_out_valid => data_f0_out_valid); - + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; lpp_waveform_snapshot_f1 : lpp_waveform_snapshot @@ -295,12 +301,12 @@ BEGIN -- beh IF rstn = '0' THEN -- asynchronous reset (active low) time_reg1 <= (OTHERS => '0'); time_reg2 <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge time_reg1 <= fine_time & coarse_time; time_reg2 <= time_reg1; END IF; END PROCESS; - + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid @@ -310,46 +316,48 @@ BEGIN -- beh run => run, valid_in => valid_in(I), ack_in => valid_ack(I), - time_in => time_reg2, -- Todo + time_in => time_reg2, -- Todo valid_out => valid_out(I), - time_out => time_out(I), -- Todo + time_out => time_out(I), -- Todo error => status_new_err(I)); END GENERATE all_input_valid; - all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE - data_out(0,I) <= data_f0_out(I); - data_out(1,I) <= data_f1_out(I); - data_out(2,I) <= data_f2_out(I); - data_out(3,I) <= data_f3_out(I); + all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE + data_out(0, I) <= data_f0_out(I); + data_out(1, I) <= data_f1_out(I); + data_out(2, I) <= data_f2_out(I); + data_out(3, I) <= data_f3_out(I); END GENERATE all_bit_of_data_out; ----------------------------------------------------------------------------- -- TODO : debug ----------------------------------------------------------------------------- - --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE - -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE - -- time_out_2(J,I) <= time_out(J)(I); + all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE + all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE + time_out_2(J,I) <= time_out(J)(I); + END GENERATE all_sample_of_time_out; + END GENERATE all_bit_of_time_out; + + -- DEBUG -- + --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; + --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; + --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; + --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; + + --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + -- time_out_2(J, I) <= time_out_debug(J)(I); -- END GENERATE all_sample_of_time_out; --END GENERATE all_bit_of_time_out; - - time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; - time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; - time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; - time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; - - all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE - all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE - time_out_2(J,I) <= time_out_debug(J)(I); - END GENERATE all_sample_of_time_out; - END GENERATE all_bit_of_time_out; + -- DEBUG -- lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - GENERIC MAP (tech => tech, - nb_data_by_buffer_size =>nb_data_by_buffer_size) + GENERIC MAP (tech => tech, + nb_data_by_buffer_size => nb_data_by_buffer_size) PORT MAP ( - clk => clk, - rstn => rstn, - run => run, + clk => clk, + rstn => rstn, + run => run, nb_data_by_buffer => nb_data_by_buffer, data_in_valid => valid_out, data_in_ack => valid_ack, @@ -358,33 +366,53 @@ BEGIN -- beh data_out => wdata, data_out_wen => data_wen, - full_almost => full_almost, + full_almost => full_almost, full => full); lpp_waveform_fifo_1 : lpp_waveform_fifo GENERIC MAP (tech => tech) PORT MAP ( - clk => clk, - rstn => rstn, - run => run, + clk => clk, + rstn => rstn, + run => run, - empty => empty, - empty_almost => empty_almost, - - data_ren => data_ren, - rdata => rdata, + empty => s_empty, + empty_almost => s_empty_almost, + data_ren => s_data_ren, + rdata => s_rdata, - + full_almost => full_almost, full => full, data_wen => data_wen, wdata => wdata); - data_f0_data_out <= rdata; - data_f1_data_out <= rdata; - data_f2_data_out <= rdata; - data_f3_data_out <= rdata; - + lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_f0_data_out, + o_rdata_1 => data_f1_data_out, + o_rdata_2 => data_f2_data_out, + o_rdata_3 => data_f3_data_out, + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + + + --data_f0_data_out <= rdata; + --data_f1_data_out <= rdata; + --data_f2_data_out <= rdata; + --data_f3_data_out <= rdata; + data_ren <= data_f3_data_out_ren & data_f2_data_out_ren & data_f1_data_out_ren & @@ -401,12 +429,12 @@ BEGIN -- beh ------------------------------------------------------------------------- -- CONFIG ------------------------------------------------------------------------- - nb_data_by_buffer => nb_word_by_buffer, - - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3, + nb_data_by_buffer => nb_word_by_buffer, + + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3, ------------------------------------------------------------------------- -- CTRL ------------------------------------------------------------------------- @@ -414,14 +442,14 @@ BEGIN -- beh empty => empty, empty_almost => empty_almost, data_ren => data_ren, - + ------------------------------------------------------------------------- -- STATUS ------------------------------------------------------------------------- - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + ------------------------------------------------------------------------- -- ADDR DATA OUT ------------------------------------------------------------------------- @@ -429,16 +457,16 @@ BEGIN -- beh data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, - - data_f0_data_out_valid => data_f0_data_out_valid, - data_f1_data_out_valid => data_f1_data_out_valid, - data_f2_data_out_valid => data_f2_data_out_valid, - data_f3_data_out_valid => data_f3_data_out_valid, - + + data_f0_data_out_valid => data_f0_data_out_valid, + data_f1_data_out_valid => data_f1_data_out_valid, + data_f2_data_out_valid => data_f2_data_out_valid, + data_f3_data_out_valid => data_f3_data_out_valid, + data_f0_addr_out => data_f0_addr_out, data_f1_addr_out => data_f1_addr_out, data_f2_addr_out => data_f2_addr_out, - data_f3_addr_out => data_f3_addr_out + data_f3_addr_out => data_f3_addr_out ); END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo_headreg IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + --------------------------------------------------------------------------- + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + --------------------------------------------------------------------------- + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS + SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL one_ren_and_notEmpty : STD_LOGIC; + SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); +BEGIN + + ----------------------------------------------------------------------------- + -- DATA_REN_FIFO + ----------------------------------------------------------------------------- + i_data_ren <= s_ren; + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + s_ren_reg <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN + s_ren_reg <= s_ren; + END IF; + END PROCESS; + + s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE + NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); + s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); + s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + '1' WHEN s_ren(1) = '0' ELSE + NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); + s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + '1' WHEN s_ren(1) = '0' ELSE + '1' WHEN s_ren(2) = '0' ELSE + NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); + ----------------------------------------------------------------------------- + all_ren : FOR I IN 3 DOWNTO 0 GENERATE + ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I)); + END GENERATE all_ren; + one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1'; + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0; + o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1; + o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2; + o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + s_rdata_0 <= (OTHERS => '0'); + s_rdata_1 <= (OTHERS => '0'); + s_rdata_2 <= (OTHERS => '0'); + s_rdata_3 <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; + IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF; + IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; + IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; + END IF; + END PROCESS; + + all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + reg_full(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN +-- IF s_ren_reg(I) = '0' THEN + IF s_ren(I) = '0' THEN + reg_full(I) <= '1'; + ELSIF o_data_ren(I) = '0' THEN + reg_full(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_reg_full; + + ----------------------------------------------------------------------------- + -- EMPTY + ----------------------------------------------------------------------------- + o_empty <= NOT reg_full; + + ----------------------------------------------------------------------------- + -- EMPTY_ALMOST + ----------------------------------------------------------------------------- + o_empty_almost <= s_empty_almost; + + all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + s_empty_almost(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge +-- IF s_ren_reg(I) = '0' THEN + IF s_ren(I) = '0' THEN + s_empty_almost(I) <= i_empty_almost(I); + ELSIF o_data_ren(I) = '0' THEN + s_empty_almost(I) <= '1'; + ELSE + IF i_empty_almost(I) = '0' THEN + s_empty_almost(I) <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_empty_almost; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -251,6 +251,26 @@ PACKAGE lpp_waveform_pkg IS wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; + COMPONENT lpp_waveform_fifo_headreg + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + COMPONENT lpp_waveform_fifo_latencyCorrection GENERIC ( tech : INTEGER); diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt --- a/lib/lpp/lpp_waveform/vhdlsyn.txt +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -6,6 +6,7 @@ lpp_waveform_fifo_latencyCorrection.vhd lpp_waveform_fifo.vhd lpp_waveform_fifo_arbiter.vhd lpp_waveform_fifo_ctrl.vhd +lpp_waveform_fifo_headreg.vhd lpp_waveform_snapshot.vhd lpp_waveform_snapshot_controler.vhd lpp_waveform_genaddress.vhd