HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_cna/lpp_cna.vhd

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        Alexis
    
Minor changes

              r38
            
      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

        martin
    
debug lpp_uart and comment lpp_cna

              r40
            
      ------------------------------------------------------------------------------

      --                    Author : Martin Morlot

      --                     Mail : martin.morlot@lpp.polytechnique.fr

      ------------------------------------------------------------------------------

        martin
    
Update lpp_cna and co

              r17
            
      library ieee;

      use ieee.std_logic_1164.all;

      library grlib;

      use grlib.amba.all;

      use std.textio.all;

      library lpp;

      use lpp.lpp_amba.all;

        martin
    
save

              r90
            
      --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on

        martin
    
Update lpp_cna and co

              r17
            
      package lpp_cna is

        martin
    
ReName some files

              r242
            
      component APB_DAC is

        martin
    
Update lpp_cna and co

              r17
            
        generic (

          pindex   : integer := 0;

          paddr    : integer := 0;

          pmask    : integer := 16#fff#;

          pirq     : integer := 0;

        martin
    
SVG non working version

              r248
            
          abits    : integer := 8;

          cpt_serial : integer := 6);

        martin
    
Update lpp_cna and co

              r17
            
        port (

          clk     : in  std_logic;

          rst     : in  std_logic;

          apbi    : in  apb_slv_in_type;

          apbo    : out apb_slv_out_type;

        martin
    
SVG non working version

              r248
            
          DataIN : in std_logic_vector(15 downto 0);

        martin
    
update CAL 2/2 + driver C

              r237
            
          Cal_EN  : out std_logic;

        martin
    
SVG non working version

              r248
            
          Readn   : out std_logic;

        martin
    
Update lpp_cna and co

              r17
            
          SYNC    : out std_logic;

          SCLK    : out std_logic;

          DATA    : out std_logic

          );

      end component;

        martin
    
ReName some files

              r242
            
      component DacDriver is

        martin
    
SVG non working version

              r248
            
          generic(cpt_serial : integer := 6);

        martin
    
Update lpp_cna and co

              r17
            
          port(

        martin
    
update CAL 2/2 + driver C

              r237
            
              clk       : in std_logic;

        martin
    
Update lpp_cna and co

              r17
            
              rst         : in std_logic;

        martin
    
save

              r90
            
              enable      : in std_logic;

        martin
    
SVG non working version

              r248
            
              Data_reg      : in std_logic_vector(15 downto 0);

        martin
    
Update lpp_cna and co

              r17
            
              SYNC        : out std_logic;

              SCLK        : out std_logic;

        martin
    
SVG non working version

              r248
            
              Readn     : out std_logic;

        martin
    
Update lpp_cna and co

              r17
            
              Data        : out std_logic

              );

      end component;

        martin
    
GRLIB changes

              r29
            
      component Systeme_Clock is

        martin
    
Update lpp_cna and co

              r17
            
          generic(N :integer := 695);

          port(

              clk, raz   : in std_logic ;

              clock      : out std_logic);

      end component;

        martin
    
optimisation code CNA

              r24
            
      component Gene_SYNC is

        martin
    
SVG non working version

              r248
            
        port(

          SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant

          enable : in std_logic;       --! Autorise ou non l'utilisation du composant

      --    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e

          SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�

          );

        martin
    
Update lpp_cna and co

              r17
            
      end component;

      component Serialize is

      port(

          clk,raz : in std_logic;

          sclk    : in std_logic;

          vectin  : in std_logic_vector(15 downto 0);

          send    : in std_logic;

        martin
    
SVG non working version

              r248
            
      --    sended  : out std_logic;

        martin
    
Update lpp_cna and co

              r17
            
          Data    : out std_logic);

      end component;

        martin
    
SVG non working version

              r248
            
      component ReadFifo_GEN is

        port(

          clk,raz : in std_logic;

          SYNC : in std_logic;

          Readn : out std_logic

          );

      end component;

        martin
    
Update lpp_cna and co

              r17
            
      end;

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Alexis Minor changes	r38	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
martin debug lpp_uart and comment lpp_cna	r40	------------------------------------------------------------------------------
		-- Author : Martin Morlot
		-- Mail : martin.morlot@lpp.polytechnique.fr
		------------------------------------------------------------------------------
martin Update lpp_cna and co	r17	library ieee;
		use ieee.std_logic_1164.all;
		library grlib;
		use grlib.amba.all;
		use std.textio.all;
		library lpp;
		use lpp.lpp_amba.all;

martin save	r90	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
martin Update lpp_cna and co	r17
		package lpp_cna is

martin ReName some files	r242	component APB_DAC is
martin Update lpp_cna and co	r17	generic (
		pindex : integer := 0;
		paddr : integer := 0;
		pmask : integer := 16#fff#;
		pirq : integer := 0;
martin SVG non working version	r248	abits : integer := 8;
		cpt_serial : integer := 6);
martin Update lpp_cna and co	r17	port (
		clk : in std_logic;
		rst : in std_logic;
		apbi : in apb_slv_in_type;
		apbo : out apb_slv_out_type;
martin SVG non working version	r248	DataIN : in std_logic_vector(15 downto 0);
martin update CAL 2/2 + driver C	r237	Cal_EN : out std_logic;
martin SVG non working version	r248	Readn : out std_logic;
martin Update lpp_cna and co	r17	SYNC : out std_logic;
		SCLK : out std_logic;
		DATA : out std_logic
		);
		end component;


martin ReName some files	r242	component DacDriver is
martin SVG non working version	r248	generic(cpt_serial : integer := 6);
martin Update lpp_cna and co	r17	port(
martin update CAL 2/2 + driver C	r237	clk : in std_logic;
martin Update lpp_cna and co	r17	rst : in std_logic;
martin save	r90	enable : in std_logic;
martin SVG non working version	r248	Data_reg : in std_logic_vector(15 downto 0);
martin Update lpp_cna and co	r17	SYNC : out std_logic;
		SCLK : out std_logic;
martin SVG non working version	r248	Readn : out std_logic;
martin Update lpp_cna and co	r17	Data : out std_logic
		);
		end component;


martin GRLIB changes	r29	component Systeme_Clock is
martin Update lpp_cna and co	r17	generic(N :integer := 695);
		port(
		clk, raz : in std_logic ;
		clock : out std_logic);
		end component;


martin optimisation code CNA	r24	component Gene_SYNC is
martin SVG non working version	r248	port(
		SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
		enable : in std_logic; --! Autorise ou non l'utilisation du composant
		-- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
		SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
		);
martin Update lpp_cna and co	r17	end component;


		component Serialize is
		port(
		clk,raz : in std_logic;
		sclk : in std_logic;
		vectin : in std_logic_vector(15 downto 0);
		send : in std_logic;
martin SVG non working version	r248	-- sended : out std_logic;
martin Update lpp_cna and co	r17	Data : out std_logic);
		end component;

martin SVG non working version	r248	component ReadFifo_GEN is
		port(
		clk,raz : in std_logic;
		SYNC : in std_logic;
		Readn : out std_logic
		);
		end component;

martin Update lpp_cna and co	r17	end;