lpp_waveform_fifo.vhd
146 lines
| 4.3 KiB
| text/x-vhdl
|
VhdlLexer
pellion
|
r165 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------ | ||||
-- Author : Jean-christophe PELLION | ||||
-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | ||||
------------------------------------------------------------------------------ | ||||
LIBRARY IEEE; | ||||
USE IEEE.std_logic_1164.ALL; | ||||
USE IEEE.numeric_std.ALL; | ||||
LIBRARY lpp; | ||||
USE lpp.lpp_memory.ALL; | ||||
USE lpp.iir_filter.ALL; | ||||
USE lpp.lpp_waveform_pkg.ALL; | ||||
LIBRARY techmap; | ||||
USE techmap.gencomp.ALL; | ||||
ENTITY lpp_waveform_fifo IS | ||||
GENERIC( | ||||
tech : INTEGER := 0 | ||||
); | ||||
PORT( | ||||
clk : IN STD_LOGIC; | ||||
rstn : IN STD_LOGIC; | ||||
pellion
|
r229 | --------------------------------------------------------------------------- | ||
run : IN STD_LOGIC; | ||||
pellion
|
r165 | |||
--------------------------------------------------------------------------- | ||||
pellion
|
r232 | empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b | ||
empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | ||||
data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | ||||
pellion
|
r230 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
pellion
|
r165 | |||
--------------------------------------------------------------------------- | ||||
pellion
|
r232 | full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b | ||
full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | ||||
data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | ||||
pellion
|
r230 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | ||
pellion
|
r165 | ); | ||
END ENTITY; | ||||
ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS | ||||
SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | ||||
SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); | ||||
pellion
|
r232 | SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0); | ||
SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0); | ||||
pellion
|
r165 | |||
SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); | ||||
SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); | ||||
pellion
|
r232 | SIGNAL re : STD_LOGIC; | ||
SIGNAL we : STD_LOGIC; | ||||
pellion
|
r165 | |||
BEGIN | ||||
SRAM : syncram_2p | ||||
GENERIC MAP(tech, 7, 32) | ||||
pellion
|
r232 | PORT MAP(clk, re, data_addr_r, rdata, | ||
clk, we, data_addr_w, wdata); | ||||
pellion
|
r165 | |||
pellion
|
r232 | re <= data_mem_re(3) OR | ||
data_mem_re(2) OR | ||||
data_mem_re(1) OR | ||||
data_mem_re(0); | ||||
pellion
|
r165 | |||
pellion
|
r232 | we <= data_mem_we(3) OR | ||
data_mem_we(2) OR | ||||
data_mem_we(1) OR | ||||
data_mem_we(0); | ||||
pellion
|
r230 | |||
pellion
|
r232 | data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE | ||
data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE | ||||
data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE | ||||
pellion
|
r165 | data_mem_addr_r(3); | ||
pellion
|
r232 | data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE | ||
data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE | ||||
data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE | ||||
pellion
|
r230 | data_mem_addr_w(3); | ||
pellion
|
r165 | |||
gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE | ||||
lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl | ||||
GENERIC MAP ( | ||||
offset => 32*I, | ||||
pellion
|
r230 | length => 32) | ||
pellion
|
r165 | PORT MAP ( | ||
clk => clk, | ||||
rstn => rstn, | ||||
pellion
|
r229 | run => run, | ||
pellion
|
r165 | ren => data_ren(I), | ||
wen => data_wen(I), | ||||
pellion
|
r232 | mem_re => data_mem_re(I), | ||
mem_we => data_mem_we(I), | ||||
pellion
|
r165 | mem_addr_ren => data_mem_addr_r(I), | ||
mem_addr_wen => data_mem_addr_w(I), | ||||
pellion
|
r230 | empty_almost => empty_almost(I), | ||
empty => empty(I), | ||||
full_almost => full_almost(I), | ||||
full => full(I) | ||||
); | ||||
pellion
|
r165 | END GENERATE gen_fifo_ctrl_data; | ||
END ARCHITECTURE; | ||||