APB_UART.vhd
136 lines
| 4.2 KiB
| text/x-vhdl
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VhdlLexer
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r19 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------- | ||||
library ieee; | ||||
use ieee.std_logic_1164.all; | ||||
library grlib; | ||||
use grlib.amba.all; | ||||
use grlib.stdlib.all; | ||||
use grlib.devices.all; | ||||
library lpp; | ||||
use lpp.lpp_amba.all; | ||||
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r37 | use lpp.apb_devices_list.all; | ||
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r19 | use lpp.lpp_uart.all; | ||
entity APB_UART is | ||||
generic ( | ||||
pindex : integer := 0; | ||||
paddr : integer := 0; | ||||
pmask : integer := 16#fff#; | ||||
pirq : integer := 0; | ||||
abits : integer := 8; | ||||
Data_sz : integer := 8); | ||||
port ( | ||||
clk : in std_logic; | ||||
rst : in std_logic; | ||||
apbi : in apb_slv_in_type; | ||||
apbo : out apb_slv_out_type; | ||||
TXD : out std_logic; | ||||
RXD : in std_logic | ||||
); | ||||
end APB_UART; | ||||
architecture ar_APB_UART of APB_UART is | ||||
constant REVISION : integer := 1; | ||||
constant pconfig : apb_config_type := ( | ||||
0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), | ||||
1 => apb_iobar(paddr, pmask)); | ||||
signal NwData : std_logic; | ||||
signal ACK : std_logic; | ||||
signal Capture : std_logic; | ||||
signal Send : std_logic; | ||||
signal Sended : std_logic; | ||||
type UART_ctrlr_Reg is record | ||||
UART_Cfg : std_logic_vector(4 downto 0); | ||||
UART_Wdata : std_logic_vector(7 downto 0); | ||||
UART_Rdata : std_logic_vector(7 downto 0); | ||||
UART_BTrig : std_logic_vector(11 downto 0); | ||||
end record; | ||||
signal Rec : UART_ctrlr_Reg; | ||||
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r29 | signal Rdata : std_logic_vector(31 downto 0); | ||
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r19 | |||
begin | ||||
Capture <= Rec.UART_Cfg(0); | ||||
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r35 | --ACK <= Rec.UART_Cfg(1); | ||
--Send <= Rec.UART_Cfg(2); | ||||
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r19 | Rec.UART_Cfg(3) <= Sended; | ||
Rec.UART_Cfg(4) <= NwData; | ||||
COM0 : entity work.UART | ||||
generic map (Data_sz) | ||||
port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); | ||||
process(rst,clk) | ||||
begin | ||||
if(rst='0')then | ||||
Rec.UART_Wdata <= (others => '0'); | ||||
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r29 | |||
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r19 | |||
elsif(clk'event and clk='1')then | ||||
--APB Write OP | ||||
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | ||||
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r35 | case apbi.paddr(7 downto 2) is | ||
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r19 | when "000000" => | ||
Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0); | ||||
when "000001" => | ||||
Rec.UART_Wdata <= apbi.pwdata(7 downto 0); | ||||
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r35 | Send <= '1'; | ||
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r19 | when others => | ||
null; | ||||
end case; | ||||
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r35 | else | ||
Send <= '0'; | ||||
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r19 | end if; | ||
--APB READ OP | ||||
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r29 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | ||
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r35 | case apbi.paddr(7 downto 2) is | ||
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r19 | when "000000" => | ||
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r35 | Rdata(4 downto 0) <= Rec.UART_Cfg; | ||
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r29 | Rdata(26 downto 12) <= (others => '0'); | ||
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r35 | Rdata(27 downto 16) <= Rec.UART_BTrig; | ||
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r19 | when "000001" => | ||
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r29 | Rdata(7 downto 0) <= Rec.UART_Wdata; | ||
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r19 | when "000010" => | ||
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r29 | Rdata(7 downto 0) <= Rec.UART_Rdata; | ||
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r35 | Ack <= '1'; | ||
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r19 | when others => | ||
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r29 | Rdata <= (others => '0'); | ||
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r19 | end case; | ||
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r35 | else | ||
Ack <= '0'; | ||||
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r19 | end if; | ||
end if; | ||||
apbo.pconfig <= pconfig; | ||||
end process; | ||||
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r29 | apbo.prdata <= Rdata when apbi.penable = '1'; | ||
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r19 | end ar_APB_UART; | ||