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Few fixes....
Few fixes. Whole LFR simulation WIP.

File last commit:

r416:92057c9e9a3b JC
r682:c53e1b6b3045 default
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vhdlsyn.txt
9 lines | 167 B | text/plain | TextLexer
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Synthesis File Updated
r229 lpp_memory.vhd
lpp_FIFO.vhd
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temp
r416 lpp_FIFO_4_Shared.vhd
lpp_FIFO_control.vhd
lpp_FIFO_4_Shared_headreg_latency_0.vhd
lpp_FIFO_4_Shared_headreg_latency_1.vhd
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
r217 lppFIFOxN.vhd
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Fusion avec martin
r296
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temp
r416