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Few fixes....
Few fixes. Whole LFR simulation WIP.
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lpp_matrix.vhd
264 lines | 8.7 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / lpp_matrix / lpp_matrix.vhd
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martin
APB_MATRIX added, first version
 r70 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use std.textio.all;
library lpp;
use lpp.lpp_amba.all;
--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
package lpp_matrix is
component APB_Matrix is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
martin
Light Leon version "TEST-LEON-M7-LPP"...
 r79 abits : integer := 8;
Input_SZ : integer := 16;
Result_SZ : integer := 32);
martin
APB_MATRIX added, first version
 r70 port (
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 clk : in std_logic;
rst : in std_logic;
martin
5 FIFO Matrix added (VHDL,C)
 r94 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 Full : in std_logic_vector(1 downto 0);
Empty : in std_logic_vector(1 downto 0);
martin
5 FIFO Matrix added (VHDL,C)
 r94 ReadFIFO : out std_logic_vector(1 downto 0);
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 FullFIFO : in std_logic;
martin
Light Leon version "TEST-LEON-M7-LPP"...
 r79 WriteFIFO : out std_logic;
martin
5 FIFO Matrix added (VHDL,C)
 r94 Result : out std_logic_vector(Result_SZ-1 downto 0);
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
martin
APB_MATRIX added, first version
 r70 );
end component;
martin
Modif ALU...
 r147 component MatriceSpectrale is
generic(
Input_SZ : integer := 16;
Result_SZ : integer := 32);
port(
clkm : in std_logic;
rstn : in std_logic;
FifoIN_Full : in std_logic_vector(4 downto 0);
martin
Chaine de donnée ok...
 r163 SetReUse : in std_logic_vector(4 downto 0);
martin
UP
 r175 Valid : in std_logic;
martin
Chaine de donnée ok...
 r163 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
martin
update CAL 1/2
 r236 ACK : in std_logic;
martin
UP
 r175 SM_Write : out std_logic;
martin
Modif ALU...
 r147 FlagError : out std_logic;
martin
Chaine de donnée ok...
 r163 Statu : out std_logic_vector(3 downto 0);
martin
Modif ALU...
 r147 Write : out std_logic_vector(1 downto 0);
Read : out std_logic_vector(4 downto 0);
martin
Chaine de donnée ok...
 r163 ReUse : out std_logic_vector(4 downto 0);
Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
martin
Modif ALU...
 r147 );
end component;
martin
Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI
 r109 component TopSpecMatrix is
generic(
Input_SZ : integer := 16);
port(
clk : in std_logic;
rstn : in std_logic;
Write : in std_logic;
ReadIn : in std_logic_vector(1 downto 0);
Full : in std_logic_vector(4 downto 0);
Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
Start : out std_logic;
ReadOut : out std_logic_vector(4 downto 0);
Statu : out std_logic_vector(3 downto 0);
DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
);
end component;
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 component Top_MatrixSpec is
generic(
Input_SZ : integer := 16;
Result_SZ : integer := 32);
port(
clk : in std_logic;
reset : in std_logic;
Statu : in std_logic_vector(3 downto 0);
FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
Full : in std_logic_vector(1 downto 0);
Empty : in std_logic_vector(1 downto 0);
ReadFIFO : out std_logic_vector(1 downto 0);
FullFIFO : in std_logic;
WriteFIFO : out std_logic;
Result : out std_logic_vector(Result_SZ-1 downto 0)
);
end component;
martin
APB_MATRIX added, first version
 r70
martin
APB_MATRIX, second version /!\ not stable /!\
 r75 component SpectralMatrix is
generic(
Input_SZ : integer := 16;
Result_SZ : integer := 32);
port(
martin
5 FIFO Matrix added (VHDL,C)
 r94 clk : in std_logic;
reset : in std_logic;
Start : in std_logic;
FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
Statu : in std_logic_vector(3 downto 0);
martin
Débug de la FIFO...
 r103 -- FullFIFO : in std_logic;
martin
5 FIFO Matrix added (VHDL,C)
 r94 ReadFIFO : out std_logic_vector(1 downto 0);
WriteFIFO : out std_logic;
Result : out std_logic_vector(Result_SZ-1 downto 0)
martin
APB_MATRIX, second version /!\ not stable /!\
 r75 );
end component;
martin
APB_MATRIX added, first version
 r70 component Matrix is
generic(
Input_SZ : integer := 16);
port(
martin
APB_MATRIX, second version /!\ not stable /!\
 r75 clk : in std_logic;
raz : in std_logic;
IN1 : in std_logic_vector(Input_SZ-1 downto 0);
IN2 : in std_logic_vector(Input_SZ-1 downto 0);
Take : in std_logic;
Received : in std_logic;
Conjugate : in std_logic;
Valid : out std_logic;
Read : out std_logic;
Result : out std_logic_vector(2*Input_SZ-1 downto 0)
martin
APB_MATRIX added, first version
 r70 );
end component;
martin
5 FIFO Matrix added (VHDL,C)
 r94 component GetResult is
generic(
Result_SZ : integer := 32);
port(
clk : in std_logic;
raz : in std_logic;
Valid : in std_logic;
Conjugate : in std_logic;
Res : in std_logic_vector(Result_SZ-1 downto 0);
martin
Débug de la FIFO...
 r103 -- Full : in std_logic;
martin
5 FIFO Matrix added (VHDL,C)
 r94 WriteFIFO : out std_logic;
Received : out std_logic;
Result : out std_logic_vector(Result_SZ-1 downto 0)
);
end component;
component TopMatrix_PDR is
generic(
Input_SZ : integer := 16;
Result_SZ : integer := 32);
port(
clk : in std_logic;
reset : in std_logic;
Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
FULLin : in std_logic_vector(4 downto 0);
READin : in std_logic_vector(1 downto 0);
WRITEin : in std_logic;
FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
Start : out std_logic;
Read : out std_logic_vector(4 downto 0);
Statu : out std_logic_vector(3 downto 0)
);
end component;
martin
Débug de la FIFO...
 r103 component Dispatch is
generic(
Data_SZ : integer := 32);
port(
clk : in std_logic;
reset : in std_logic;
martin
update CAL 1/2
 r236 Ack : in std_logic;
martin
Débug de la FIFO...
 r103 Data : in std_logic_vector(Data_SZ-1 downto 0);
Write : in std_logic;
martin
UP
 r175 Valid : in std_logic;
martin
Débug de la FIFO...
 r103 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
FifoWrite : out std_logic_vector(1 downto 0);
Error : out std_logic
);
end component;
martin
5 FIFO Matrix added (VHDL,C)
 r94 component DriveInputs is
port(
clk : in std_logic;
raz : in std_logic;
Read : in std_logic;
Conjugate : in std_logic;
Take : out std_logic;
ReadFIFO : out std_logic_vector(1 downto 0)
);
end component;
martin
Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
 r95 component Starter is
port(
clk : in std_logic;
raz : in std_logic;
Full : in std_logic_vector(1 downto 0);
Empty : in std_logic_vector(1 downto 0);
Statu : in std_logic_vector(3 downto 0);
Write : in std_logic;
Start : out std_logic
);
end component;
martin
APB_MATRIX added, first version
 r70
component ALU_Driver is
generic(
Input_SZ_1 : integer := 16;
Input_SZ_2 : integer := 16);
port(
martin
APB_MATRIX, second version /!\ not stable /!\
 r75 clk : in std_logic;
reset : in std_logic;
IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
Take : in std_logic;
Received : in std_logic;
Conjugate : in std_logic;
Valid : out std_logic;
Read : out std_logic;
martin
Modif ALU...
 r147 CTRL : out std_logic_vector(2 downto 0);
COMP : out std_logic_vector(1 downto 0);
martin
APB_MATRIX, second version /!\ not stable /!\
 r75 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
martin
APB_MATRIX added, first version
 r70 );
end component;
martin
Chaine de donnée ok...
 r163 component ReUse_CTRLR is
port(
clk : in std_logic;
reset : in std_logic;
SetReUse : in std_logic_vector(4 downto 0);
Statu : in std_logic_vector(3 downto 0);
ReUse : out std_logic_vector(4 downto 0)
);
end component;
martin
APB_MATRIX added, first version
 r70 end;