HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/dsp/iir_filter/vhdlsyn.txt

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

pellion - - Load All Authors

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r520:4ecb2a443559 JC


                r594:a9702b7364d2

simu_with_Leon3

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/ lib / lpp / dsp / iir_filter / vhdlsyn.txt

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pellion Synthesis File Updated	r229	iir_filter.vhd
pellion temp	r176	FILTERcfg.vhd
pellion Synthesis File Updated	r229	RAM.vhd
		RAM_CEL.vhd
		RAM_CTRLR_v2.vhd
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	IIR_CEL_CTRLR_v2_CONTROL.vhd
		IIR_CEL_CTRLR_v2_DATAFLOW.vhd
jeandet Restored previous ALU version as ALU_V0 for IIR filter first version...	r226	IIR_CEL_CTRLR_v2.vhd
pellion add filter (f2,f3)	r520	IIR_CEL_CTRLR_v3_DATAFLOW.vhd
		IIR_CEL_CTRLR_v3.vhd

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