HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/dsp/iir_filter/vhdlsyn.txt

temp : update ADC driver...

temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)

pellion - - Load All Authors

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simu_with_Leon3

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/ lib / lpp / dsp / iir_filter / vhdlsyn.txt

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				iir_filter.vhd
				FILTERcfg.vhd
				RAM.vhd
				RAM_CEL.vhd
				RAM_CTRLR_v2.vhd
				IIR_CEL_CTRLR_v2_CONTROL.vhd
				IIR_CEL_CTRLR_v2_DATAFLOW.vhd
				IIR_CEL_CTRLR_v2.vhd
				IIR_CEL_CTRLR_v3_DATAFLOW.vhd
				IIR_CEL_CTRLR_v3.vhd

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