lpp_waveform_dma_genvalid.vhd
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| 3.1 KiB
| text/x-vhdl
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VhdlLexer
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r165 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------- | ||||
-- Author : Jean-christophe Pellion | ||||
-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | ||||
-- jean-christophe.pellion@easii-ic.com | ||||
------------------------------------------------------------------------------- | ||||
-- 1.0 - initial version | ||||
------------------------------------------------------------------------------- | ||||
LIBRARY ieee; | ||||
USE ieee.std_logic_1164.ALL; | ||||
USE ieee.numeric_std.ALL; | ||||
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r230 | ENTITY lpp_waveform_dma_genvalid IS | ||
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r165 | PORT ( | ||
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r229 | HCLK : IN STD_LOGIC; | ||
HRESETn : IN STD_LOGIC; | ||||
run : IN STD_LOGIC; | ||||
valid_in : IN STD_LOGIC; | ||||
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r230 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
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r229 | |||
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r439 | ack_in : IN STD_LOGIC; | ||
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r229 | valid_out : OUT STD_LOGIC; | ||
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r230 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
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r229 | error : OUT STD_LOGIC | ||
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r165 | ); | ||
END; | ||||
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r230 | ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS | ||
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r165 | TYPE state_fsm IS (IDLE, VALID); | ||
SIGNAL state : state_fsm; | ||||
BEGIN | ||||
FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | ||||
BEGIN | ||||
IF HRESETn = '0' THEN | ||||
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r229 | state <= IDLE; | ||
valid_out <= '0'; | ||||
error <= '0'; | ||||
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r439 | time_out <= (OTHERS => '0'); | ||
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r165 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | ||
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r439 | IF run = '1' THEN | ||
CASE state IS | ||||
WHEN IDLE => | ||||
valid_out <= valid_in; | ||||
error <= '0'; | ||||
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r230 | time_out <= time_in; | ||
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r165 | |||
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r439 | IF valid_in = '1' THEN | ||
state <= VALID; | ||||
END IF; | ||||
WHEN VALID => | ||||
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r229 | IF valid_in = '1' THEN | ||
IF ack_in = '1' THEN | ||||
state <= VALID; | ||||
valid_out <= '1'; | ||||
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r230 | time_out <= time_in; | ||
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r229 | ELSE | ||
state <= IDLE; | ||||
error <= '1'; | ||||
valid_out <= '0'; | ||||
END IF; | ||||
ELSIF ack_in = '1' THEN | ||||
state <= IDLE; | ||||
valid_out <= '0'; | ||||
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r165 | END IF; | ||
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r439 | |||
WHEN OTHERS => NULL; | ||||
END CASE; | ||||
ELSE | ||||
state <= IDLE; | ||||
valid_out <= '0'; | ||||
error <= '0'; | ||||
time_out <= (OTHERS => '0'); | ||||
END IF; | ||||
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r165 | END IF; | ||
END PROCESS FSM_SELECT_ADDRESS; | ||||
END Behavioral; | ||||