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Mini LFR - 0.1.84
Mini LFR - 0.1.84
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r345:21fc600461fa (MINI-LFR) WFP_MS-0-1-10 JC
r617:7ac14cef3eb0 simu_with_Leon3
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Linker_FFT.vhd
113 lines | 3.6 KiB | text/x-vhdl | VhdlLexer
/ lib / lpp / dsp / lpp_fft / Linker_FFT.vhd
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martin
update ADC
 r98 ------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
------------------------------------------------------------------------------
pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
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update ADC
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(MINI-LFR) WFP_MS_0-1-10
 r345 ENTITY Linker_FFT IS
GENERIC(
Data_sz : INTEGER RANGE 1 TO 32 := 16;
NbData : INTEGER RANGE 1 TO 512 := 256
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 r98 );
pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 PORT(
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
Ready : IN STD_LOGIC; --
Valid : IN STD_LOGIC; --
Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --
Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
Read : OUT STD_LOGIC; -- Link_Read
Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
);
END ENTITY;
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update ADC
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 ARCHITECTURE ar_Linker OF Linker_FFT IS
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 TYPE etat IS (eX, e0, e1, e2);
SIGNAL ect : etat;
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 SIGNAL sRead : STD_LOGIC;
SIGNAL sReady : STD_LOGIC;
martin
FFT sur 5 Voies Okai...
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 BEGIN
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 PROCESS(clk, rstn)
BEGIN
IF(rstn = '0')then
ect <= e0;
sRead <= '0';
sReady <= '0';
Write <= (OTHERS => '1');
Reuse <= (OTHERS => '0');
FifoCpt <= 0;
ELSIF(clk'EVENT AND clk = '1')then
sReady <= Ready;
martin
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 IF(sReady = '1' and Ready = '0')THEN
IF(FifoCpt = 4)THEN
FifoCpt <= 0;
ELSE
FifoCpt <= FifoCpt + 1;
END IF;
ELSIF(Ready = '1')then
sRead <= NOT sRead;
ELSE
sRead <= '0';
END IF;
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 CASE ect IS
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 WHEN e0 =>
Write(FifoCpt) <= '1';
IF(Valid = '1' and Full(FifoCpt) = '0')THEN
DataTmp <= Data_im;
DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re;
Write(FifoCpt) <= '0';
ect <= e1;
ELSIF(Full(FifoCpt) = '1')then
ReUse(FifoCpt) <= '1';
END IF;
martin
update ADC
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 WHEN e1 =>
DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp;
ect <= e0;
WHEN OTHERS =>
NULL;
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 END CASE;
END IF;
END PROCESS;
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 Read <= sRead;
martin
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pellion
(MINI-LFR) WFP_MS_0-1-10
 r345 END ARCHITECTURE;