lpp_memory.vhd
83 lines
| 2.9 KiB
| text/x-vhdl
|
VhdlLexer
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r53 | ------------------------------------------------------------------------------ | ||
-- This file is a part of the LPP VHDL IP LIBRARY | ||||
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
-- | ||||
-- This program is free software; you can redistribute it and/or modify | ||||
-- it under the terms of the GNU General Public License as published by | ||||
-- the Free Software Foundation; either version 3 of the License, or | ||||
-- (at your option) any later version. | ||||
-- | ||||
-- This program is distributed in the hope that it will be useful, | ||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
-- GNU General Public License for more details. | ||||
-- | ||||
-- You should have received a copy of the GNU General Public License | ||||
-- along with this program; if not, write to the Free Software | ||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
------------------------------------------------------------------------------ | ||||
-- Author : Martin Morlot | ||||
-- Mail : martin.morlot@lpp.polytechnique.fr | ||||
------------------------------------------------------------------------------ | ||||
library ieee; | ||||
use ieee.std_logic_1164.all; | ||||
library grlib; | ||||
use grlib.amba.all; | ||||
use std.textio.all; | ||||
library lpp; | ||||
use lpp.lpp_amba.all; | ||||
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r85 | library gaisler; | ||
use gaisler.misc.all; | ||||
use gaisler.memctrl.all; | ||||
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r53 | |||
--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | ||||
package lpp_memory is | ||||
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r92 | component lpp_fifo is | ||
generic( | ||||
tech : integer := 0; | ||||
DataSz : integer range 1 to 32 := 8; | ||||
abits : integer range 2 to 12 := 8 | ||||
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r53 | ); | ||
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r92 | port( | ||
rstn : in std_logic; | ||||
rclk : in std_logic; | ||||
ren : in std_logic; | ||||
rdata : out std_logic_vector(DataSz-1 downto 0); | ||||
empty : out std_logic; | ||||
raddr : out std_logic_vector(abits-1 downto 0); | ||||
wclk : in std_logic; | ||||
wen : in std_logic; | ||||
wdata : in std_logic_vector(DataSz-1 downto 0); | ||||
full : out std_logic; | ||||
waddr : out std_logic_vector(abits-1 downto 0) | ||||
); | ||||
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r53 | end component; | ||
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r84 | component ssram_plugin is | ||
generic (tech : integer := 0); | ||||
port | ||||
( | ||||
clk : in std_logic; | ||||
mem_ctrlr_o : in memory_out_type; | ||||
SSRAM_CLK : out std_logic; | ||||
nBWa : out std_logic; | ||||
nBWb : out std_logic; | ||||
nBWc : out std_logic; | ||||
nBWd : out std_logic; | ||||
nBWE : out std_logic; | ||||
nADSC : out std_logic; | ||||
nADSP : out std_logic; | ||||
nADV : out std_logic; | ||||
nGW : out std_logic; | ||||
nCE1 : out std_logic; | ||||
CE2 : out std_logic; | ||||
nCE3 : out std_logic; | ||||
nOE : out std_logic; | ||||
MODE : out std_logic; | ||||
ZZ : out std_logic | ||||
); | ||||
end component; | ||||
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r53 | end; | ||