HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_cna/CNA_TabloC.vhd

Added LFR DM board files and miniAMBA design tesed under Libero9.1 sp1

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        martin
    
debug lpp_uart and comment lpp_cna

              r40
            
      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      ------------------------------------------------------------------------------

      --                    Author : Martin Morlot

      --                     Mail : martin.morlot@lpp.polytechnique.fr

      ------------------------------------------------------------------------------

        martin
    
Update lpp_cna and co

              r17
            
      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      use work.Convertisseur_config.all;

        martin
    
debug lpp_uart and comment lpp_cna

              r40
            
      --! Programme du Convertisseur Num�rique/Analogique

        martin
    
Update lpp_cna and co

              r17
            
      entity CNA_TabloC is

        martin
    
debug lpp_uart and comment lpp_cna

              r40
            
        port(

          clock       : in std_logic;                        --! Horloge du composant

          rst         : in std_logic;                        --! Reset general du composant

          enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant

          Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits

          SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur

          SCLK        : out std_logic;                       --! Horloge systeme du convertisseur

          flag_sd     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e

          Data        : out std_logic                        --! Donn�e num�rique s�rialis�

          );

        martin
    
Update lpp_cna and co

              r17
            
      end CNA_TabloC;

        martin
    
debug lpp_uart and comment lpp_cna

              r40
            
      --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits, 

      --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.

        martin
    
Update lpp_cna and co

              r17
            
      architecture ar_CNA_TabloC of CNA_TabloC is

      component CLKINT

      port( A : in    std_logic := 'U';

            Y : out   std_logic);

      end component;

      signal clk      : std_logic;

      signal raz          : std_logic;

        martin
    
optimisation code CNA

              r24
            
      signal s_SCLK      : std_logic;

        martin
    
Update lpp_cna and co

              r17
            
      signal OKAI_send    : std_logic;

      begin

      CLKINT_0 : CLKINT

          port map(A => clock, Y => clk);

      CLKINT_1 : CLKINT

          port map(A => rst, Y => raz);

        martin
    
GRLIB changes

              r29
            
      SystemCLK : entity work.Systeme_Clock

        martin
    
Update lpp_cna and co

              r17
            
          generic map (nb_serial)

        martin
    
optimisation code CNA

              r24
            
          port map (clk,raz,s_SCLK);

        martin
    
Update lpp_cna and co

              r17
            
        martin
    
optimisation code CNA

              r24
            
      Signal_sync : entity work.Gene_SYNC

          port map (s_SCLK,raz,enable,OKAI_send,SYNC);

        martin
    
Update lpp_cna and co

              r17
            
      Serial : entity work.serialize

        martin
    
optimisation code CNA

              r24
            
          port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);

        martin
    
Update lpp_cna and co

              r17
            
        martin
    
optimisation code CNA

              r24
            
      SCLK        <= s_SCLK;

        martin
    
Update lpp_cna and co

              r17
            
      end ar_CNA_TabloC;

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martin debug lpp_uart and comment lpp_cna	r40	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		------------------------------------------------------------------------------
		-- Author : Martin Morlot
		-- Mail : martin.morlot@lpp.polytechnique.fr
		------------------------------------------------------------------------------
martin Update lpp_cna and co	r17	library IEEE;
		use IEEE.std_logic_1164.all;
		use IEEE.numeric_std.all;
		use work.Convertisseur_config.all;

martin debug lpp_uart and comment lpp_cna	r40	--! Programme du Convertisseur Num�rique/Analogique

martin Update lpp_cna and co	r17	entity CNA_TabloC is
martin debug lpp_uart and comment lpp_cna	r40	port(
		clock : in std_logic; --! Horloge du composant
		rst : in std_logic; --! Reset general du composant
		enable : in std_logic; --! Autorise ou non l'utilisation du composant
		Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
		SYNC : out std_logic; --! Signal de synchronisation du convertisseur
		SCLK : out std_logic; --! Horloge systeme du convertisseur
		flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
		Data : out std_logic --! Donn�e num�rique s�rialis�
		);
martin Update lpp_cna and co	r17	end CNA_TabloC;

martin debug lpp_uart and comment lpp_cna	r40	--! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
		--! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
martin Update lpp_cna and co	r17
		architecture ar_CNA_TabloC of CNA_TabloC is

		component CLKINT
		port( A : in std_logic := 'U';
		Y : out std_logic);
		end component;

		signal clk : std_logic;

		signal raz : std_logic;
martin optimisation code CNA	r24	signal s_SCLK : std_logic;
martin Update lpp_cna and co	r17	signal OKAI_send : std_logic;

		begin

		CLKINT_0 : CLKINT
		port map(A => clock, Y => clk);

		CLKINT_1 : CLKINT
		port map(A => rst, Y => raz);


martin GRLIB changes	r29	SystemCLK : entity work.Systeme_Clock
martin Update lpp_cna and co	r17	generic map (nb_serial)
martin optimisation code CNA	r24	port map (clk,raz,s_SCLK);
martin Update lpp_cna and co	r17

martin optimisation code CNA	r24	Signal_sync : entity work.Gene_SYNC
		port map (s_SCLK,raz,enable,OKAI_send,SYNC);
martin Update lpp_cna and co	r17

		Serial : entity work.serialize
martin optimisation code CNA	r24	port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
martin Update lpp_cna and co	r17

martin optimisation code CNA	r24	SCLK <= s_SCLK;
martin Update lpp_cna and co	r17
		end ar_CNA_TabloC;