Makefile
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MakefileLexer
pellion
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r310 | ##------------------------------------------------------------------------------ | ||
| ##-- This file is a part of the LPP VHDL IP LIBRARY | ||||
| ##-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | ||||
| ##-- | ||||
| ##-- This program is free software; you can redistribute it and/or modify | ||||
| ##-- it under the terms of the GNU General Public License as published by | ||||
| ##-- the Free Software Foundation; either version 3 of the License, or | ||||
| ##-- (at your option) any later version. | ||||
| ##-- | ||||
| ##-- This program is distributed in the hope that it will be useful, | ||||
| ##-- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
| ##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
| ##-- GNU General Public License for more details. | ||||
| ##-- | ||||
| ##-- You should have received a copy of the GNU General Public License | ||||
| ##-- along with this program; if not, write to the Free Software | ||||
| ##-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
| ##------------------------------------------------------------------------------- | ||||
| ##-- Author : Jean-christophe Pellion | ||||
| ##-- Mail : jean-christophe.pellion@lpp.polytechnique.fr | ||||
| ##-- jean-christophe.pellion@easii-ic.com | ||||
| ##------------------------------------------------------------------------------- | ||||
| VHDLIB=../.. | ||||
| SCRIPTSDIR=$(VHDLIB)/scripts/ | ||||
| GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | ||||
| TOP=MINI_LFR_top | ||||
| BOARD=MINI-LFR | ||||
| include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | ||||
| DEVICE=$(PART)-$(PACKAGE)$(SPEED) | ||||
| UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf | ||||
| QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf | ||||
| EFFORT=high | ||||
| XSTOPT= | ||||
| SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | ||||
| VHDLSYNFILES= MINI_LFR_top.vhd | ||||
| PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc | ||||
| BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | ||||
| CLEAN=soft-clean | ||||
| TECHLIBS = proasic3e | ||||
| LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | ||||
| tmtc openchip hynix ihp gleichmann micron usbhc | ||||
| DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | ||||
| pci grusbhc haps slink ascs pwm coremp7 spi ac97 | ||||
| FILESKIP = | ||||
| include $(GRLIB)/bin/Makefile | ||||
| include $(GRLIB)/software/leon3/Makefile | ||||
| ################## project specific targets ########################## | ||||