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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.
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r570:0b1aedcd4196 JC
r655:2dbcdaf8bb73 default
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LFR_EQM_place_and_route-debug.sdc
40 lines | 1.2 KiB | application/vnd.stardivision.calc | TextLexer
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pellion
EQM debug
 r567 # Top Level Design Parameters
# Clocks
create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
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debug EQM...
 r570 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
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EQM debug
 r569
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debug EQM...
 r570
#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
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EQM debug
 r569 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
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EQM debug
 r567 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
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EQM debug
 r569 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
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EQM debug
 r567
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
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EQM debug
 r569
## GRSPW constraints
create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]