HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ICI4-Integ1/Makefile

Added file init for RAM_CEL IP.[Need tests]...

Added file init for RAM_CEL IP.[Need tests] Made IIR filter design more GHDL friendly.

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             Makefile
        
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        jeandet
    
Added ICI4 designs....

              r129
            
      include .config

      #GRLIB=$(GRLIB)

      TOP=ici4

        jeandet
    
ICI rockets designs added

              r168
            
      BOARD=ICI4-main-BD

      #BOARD=SP601

        jeandet
    
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              r223
            
      include ../../boards/$(BOARD)/Makefile.inc

        jeandet
    
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      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

        jeandet
    
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      #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf

        jeandet
    
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              r223
            
      UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf

      QSF=../../boards/$(BOARD)/$(TOP).qsf

        jeandet
    
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      EFFORT=high

      ISEMAPOPT="-timing"

      XSTOPT=""

      SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"

      VHDLOPTSYNFILES= \

        jeandet
    
ICI rockets designs added

              r168
            
                       ICI4HDL/Convertisseur_config.vhd \

                       ICI4HDL/Convertisseur_Data.vhd \

                       ICI4HDL/DC_FRAME_PLACER.vhd \

                       ICI4HDL/DC_SMPL_CLK.vhd \

                       ICI4HDL/LF_FRAME_PLACER.vhd \

        jeandet
    
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              r223
            
                       ICI4HDL/LF_SMPL_CLK.vhd \

                       ICI4HDL/Fast2SlowSync.vhd \

                       ICI4HDL/Slow2FastSync.vhd \

                       ICI4HDL/CrossDomainSyncGen.vhd \

                       ICI4HDL/TM_MODULE.vhd \

                       ICI4HDL/DC_ACQ_TOP.vhd \

                       ICI4HDL/LF_ACQ_TOP.vhd \

                 	 ICI4HDL/FAKE_ADC.vhd \

        jeandet
    
Restored previous ALU version as ALU_V0 for IIR filter first version...

              r226
            
                       ICI4HDL/OneShot.vhd \

                       ICI4HDL/IIR_FILTER_TOP.vhd

        jeandet
    
Added cross domain synchronisation blocks.

              r223
            
        jeandet
    
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              r129
            
      VHDLSYNFILES= \

      	config.vhd  ici4.vhd

      VHDLSIMFILES=testbench.vhd

      SIMTOP=testbench

      #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

      SDCFILE=default.sdc

        jeandet
    
Added cross domain synchronisation blocks.

              r223
            
      BITGEN=../../boards/$(BOARD)/default.ut

        jeandet
    
Added ICI4 designs....

              r129
            
      CLEAN=soft-clean

      VCOMOPT=-explicit

      TECHLIBS = secureip unisim 

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip cypress ihp gleichmann gsi fmf spansion 

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \

      	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \

      	ac97 hcan usb

      DIRADD = 

        jeandet
    
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              r168
            
      FILEADD = 

        jeandet
    
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      FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

        jeandet
    
Added cross domain synchronisation blocks.

              r223
            
      flash:

      	xc3sprog -c ftdi -p 1 ici4.bit

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jeandet Added ICI4 designs....	r129	include .config

		#GRLIB=$(GRLIB)
		TOP=ici4
jeandet ICI rockets designs added	r168	BOARD=ICI4-main-BD
		#BOARD=SP601
jeandet Added cross domain synchronisation blocks.	r223	include ../../boards/$(BOARD)/Makefile.inc
jeandet Added ICI4 designs....	r129	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
jeandet ICI rockets designs added	r168	#UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
jeandet Added cross domain synchronisation blocks.	r223	UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf
		QSF=../../boards/$(BOARD)/$(TOP).qsf
jeandet Added ICI4 designs....	r129	EFFORT=high
		ISEMAPOPT="-timing"
		XSTOPT=""
		SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
		VHDLOPTSYNFILES= \
jeandet ICI rockets designs added	r168	ICI4HDL/Convertisseur_config.vhd \
		ICI4HDL/Convertisseur_Data.vhd \
		ICI4HDL/DC_FRAME_PLACER.vhd \
		ICI4HDL/DC_SMPL_CLK.vhd \
		ICI4HDL/LF_FRAME_PLACER.vhd \
jeandet Added cross domain synchronisation blocks.	r223	ICI4HDL/LF_SMPL_CLK.vhd \
		ICI4HDL/Fast2SlowSync.vhd \
		ICI4HDL/Slow2FastSync.vhd \
		ICI4HDL/CrossDomainSyncGen.vhd \
		ICI4HDL/TM_MODULE.vhd \
		ICI4HDL/DC_ACQ_TOP.vhd \
		ICI4HDL/LF_ACQ_TOP.vhd \
		ICI4HDL/FAKE_ADC.vhd \
jeandet Restored previous ALU version as ALU_V0 for IIR filter first version...	r226	ICI4HDL/OneShot.vhd \
		ICI4HDL/IIR_FILTER_TOP.vhd
jeandet Added cross domain synchronisation blocks.	r223
jeandet Added ICI4 designs....	r129
		VHDLSYNFILES= \
		config.vhd ici4.vhd
		VHDLSIMFILES=testbench.vhd
		SIMTOP=testbench
		#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
		SDCFILE=default.sdc
jeandet Added cross domain synchronisation blocks.	r223	BITGEN=../../boards/$(BOARD)/default.ut
jeandet Added ICI4 designs....	r129	CLEAN=soft-clean
		VCOMOPT=-explicit
		TECHLIBS = secureip unisim

		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		tmtc openchip cypress ihp gleichmann gsi fmf spansion
		DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
		leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
		ac97 hcan usb
		DIRADD =
jeandet ICI rockets designs added	r168	FILEADD =
jeandet Added ICI4 designs....	r129	FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile


		################## project specific targets ##########################

jeandet Added cross domain synchronisation blocks.	r223	flash:
		xc3sprog -c ftdi -p 1 ici4.bit