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@@ -0,0 +1,128
1 import numpy as np
2
3 from test_fft.register_addresses_fft_test import *
4
5 from __main__ import RMAPPlugin0
6
7 def print_custom( value ):
8 print value
9 RMAPPlugin0.ProcessPendingEvents()
10
11 def read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM ):
12 currentComp_re = np.zeros( nbFrequencyBins )
13 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
14 mask_REN = mask_REN_FIFO_0
15 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
16 mask_REN = mask_REN_FIFO_1
17 else:
18 print_custom( "ERR *** read_SM_Re *** unexpected address_MEM_OUT_SM" )
19 for frequencyBin in range(nbFrequencyBins):
20 # read Re
21 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
22 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
23 currentComp_re[frequencyBin] = val[0]
24 RMAPPlugin0.ProcessPendingEvents()
25 return currentComp_re
26
27 def read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM ):
28 currentComp_re = np.zeros( nbFrequencyBins )
29 currentComp_im = np.zeros( nbFrequencyBins )
30 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
31 mask_REN = mask_REN_FIFO_0
32 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
33 mask_REN = mask_REN_FIFO_1
34 else:
35 print_custom( "ERR *** read_SM_Re_Im *** unexpected address_MEM_OUT_SM" )
36 for frequencyBin in range(nbFrequencyBins):
37 # read Re
38 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
39 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
40 currentComp_re[frequencyBin] = val[0]
41 # read Im
42 RMAPPlugin0.Write( address_CTRL_SM, [mask_REN] )
43 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
44 currentComp_im[frequencyBin] = val[0]
45 RMAPPlugin0.ProcessPendingEvents()
46 return (currentComp_re, currentComp_im)
47
48 def is_MEM_OUT_SM_Empty( ):
49 ret = 0
50 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
51 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
52 if MEM_OUT_SM_Empty == 0x3:
53 ret = 1
54 return ret
55
56 def is_MEM_OUT_SM_Full( ):
57 ret = 0
58 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
59 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
60 if MEM_OUT_SM_Full != 0x0:
61 ret = 1
62 return ret
63
64 def is_MEM_OUT_SM_Full_FIFO_0( ):
65 ret = 0
66 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
67 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000004) >> 2
68 if MEM_OUT_SM_Full == 0x01:
69 ret = 1
70 return ret
71
72 def is_MEM_OUT_SM_Full_FIFO_1( ):
73 ret = 0
74 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
75 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000008) >> 3
76 if MEM_OUT_SM_Full == 0x01:
77 ret = 1
78 return ret
79
80 def wait_for_FIFO_0_Full():
81 counter = 0
82 while ( is_MEM_OUT_SM_Full_FIFO_0() == 0 ):
83 print_custom( "FIFO_0 not full " + str(counter) )
84 counter = counter + 1
85 if counter == 10:
86 break
87
88 def wait_for_FIFO_1_Full():
89 counter = 0
90 while ( is_MEM_OUT_SM_Full_FIFO_1() == 0 ):
91 print_custom( "FIFO_1 not full " + str(counter))
92 counter = counter + 1
93 if counter == 10:
94 break
95
96 def wait_for_FIFO_Full( fifo ):
97 if fifo == 0:
98 wait_for_FIFO_0_Full()
99 elif fifo == 1:
100 wait_for_FIFO_1_Full()
101 else:
102 print_custom( "ERR *** wait_for_FIFO_Full *** unexpted value for parameter [fifo]" )
103
104 def wait_for_FIFO_0_or_1_Full():
105 counter = 0
106 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
107 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
108 while ( MEM_OUT_SM_Full == 0 ):
109 print_custom( "FIFO 0 or 1 not full " + str(counter))
110 counter = counter + 1
111 if counter == 10:
112 break
113 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
114 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
115 RMAPPlugin0.ProcessPendingEvents()
116
117 def print_reg_sm( ):
118 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
119 out_ren = (sm_reg[0] & 0x00000003)
120 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
121 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
122 MEM_OUT_SM_Full_s= (sm_reg[0] & 0x00000040) >> 6
123 print "sm_reg = " + bin( sm_reg[0] & 0x7f ) \
124 + ", out_ren = " + bin( out_ren ) \
125 + ", MEM_OUT_SM_Full = " + bin( MEM_OUT_SM_Full ) \
126 + ", MEM_OUT_SM_Empty = " + bin( MEM_OUT_SM_Empty ) \
127 + ", MEM_OUT_SM_Full_s = " + bin( MEM_OUT_SM_Full_s )
128 RMAPPlugin0.ProcessPendingEvents() No newline at end of file
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@@ -4,58 +4,94
4 4 "selected_items":
5 5 [
6 6 [
7 "c",
8 "c"
7 "fi",
8 "fifo_to_wait_for"
9 ],
10 [
11 "MEM",
12 "MEM_OUT_SM_Full"
13 ],
14 [
15 "add",
16 "address_MEM_OUT_SM"
17 ],
18 [
19 "addrses",
20 "address_MEM_OUT_SM_0"
21 ],
22 [
23 "address_MEM",
24 "address_MEM_OUT_SM_1"
9 25 ],
10 26 [
11 "g",
12 "g"
27 "address_M",
28 "address_MEM_OUT_SM_1"
29 ],
30 [
31 "ad",
32 "address_MEM_OUT_SM_0"
13 33 ],
14 34 [
15 "compo",
16 "components_re"
35 "address",
36 "address_MEM_OUT_SM"
17 37 ],
18 38 [
19 "cur",
39 "print",
40 "print_custom"
41 ],
42 [
43 "is_MEM_OUT_SM_Full_",
44 "is_MEM_OUT_SM_Full_FIFO_0"
45 ],
46 [
47 "curre",
20 48 "currentComp_im"
21 49 ],
22 50 [
23 "current",
24 "currentComp_im"
51 "MEM_OUT_SM_Ful",
52 "MEM_OUT_SM_Full_s"
53 ],
54 [
55 "fft0",
56 "fft0_im"
57 ],
58 [
59 "fft",
60 "fft0_im"
61 ],
62 [
63 "dataB",
64 "dataBufferConverted"
25 65 ],
26 66 [
27 "curre",
28 "currentComp_re"
67 "convert",
68 "convertToSigned16Bits"
69 ],
70 [
71 "data",
72 "dataInInt16"
29 73 ],
30 74 [
31 "nb",
32 "nbComponentsPerMatrix"
75 "wfrm",
76 "wfrm2"
33 77 ],
34 78 [
35 "MEM",
36 "MEM_IN_SM_Empty"
79 "column",
80 "columnB3"
81 ],
82 [
83 "colum",
84 "columnV"
37 85 ],
38 86 [
39 87 "out_re",
40 88 "out_ren"
41 89 ],
42 90 [
43 "fft",
44 "fft_reg"
45 ],
46 [
47 "address_MEM",
48 "address_MEM_IN_SM_0"
49 ],
50 [
51 91 "wfr",
52 92 "wfrm0"
53 93 ],
54 94 [
55 "print",
56 "print_reg_fft"
57 ],
58 [
59 95 "sin",
60 96 "sineWave"
61 97 ],
@@ -76,14 +112,6
76 112 "address_FIFO_F0_4"
77 113 ],
78 114 [
79 "add",
80 "address_CTRL"
81 ],
82 [
83 "wfrm",
84 "wfrm1"
85 ],
86 [
87 115 "index",
88 116 "indexTransformDecimationInFrequency"
89 117 ],
@@ -128,6 +156,10
128 156 "groupbox_tc_lfr_load_common_par"
129 157 ],
130 158 [
159 "c",
160 "common"
161 ],
162 [
131 163 "laben",
132 164 "label_UNKNOWN_nb"
133 165 ],
@@ -143,15 +175,15
143 175 "file": "test_fft/test_sm_mini_lfr.py",
144 176 "settings":
145 177 {
146 "buffer_size": 4053,
178 "buffer_size": 5847,
147 179 "line_ending": "Unix"
148 180 }
149 181 },
150 182 {
151 "file": "test_fft/fft_test_functions.py",
183 "file": "test_fft/test_sm_functions.py",
152 184 "settings":
153 185 {
154 "buffer_size": 3885,
186 "buffer_size": 3914,
155 187 "line_ending": "Unix"
156 188 }
157 189 },
@@ -159,7 +191,7
159 191 "file": "test_fft/register_addresses_fft_test.py",
160 192 "settings":
161 193 {
162 "buffer_size": 798,
194 "buffer_size": 873,
163 195 "line_ending": "Unix"
164 196 }
165 197 }
@@ -188,7 +220,9
188 220 },
189 221 "file_history":
190 222 [
223 "/opt/LFR_EMULATOR/test_fft/fft_test_functions.py",
191 224 "/opt/LFR_EMULATOR/test_fft/test_fft_mini_lfr.py",
225 "/opt/LFR_EMULATOR/test_fft/register_addresses_fft_test.py",
192 226 "/opt/LFR_EMULATOR/test_fft/functions_evaluations.py",
193 227 "/opt/LFR_EMULATOR/SRC/processing_chain.py",
194 228 "/opt/LFR_EMULATOR/main.py",
@@ -237,6 +271,7
237 271 "case_sensitive": false,
238 272 "find_history":
239 273 [
274 "np",
240 275 "def displayInfoSendTc",
241 276 "dump",
242 277 "tc_lfr_dump_par",
@@ -269,15 +304,15
269 304 "file": "test_fft/test_sm_mini_lfr.py",
270 305 "settings":
271 306 {
272 "buffer_size": 4053,
307 "buffer_size": 5847,
273 308 "regions":
274 309 {
275 310 },
276 311 "selection":
277 312 [
278 313 [
279 2731,
280 2731
314 5847,
315 5847
281 316 ]
282 317 ],
283 318 "settings":
@@ -286,25 +321,25
286 321 "translate_tabs_to_spaces": false
287 322 },
288 323 "translation.x": 0.0,
289 "translation.y": 1295.0,
324 "translation.y": 1640.0,
290 325 "zoom_level": 1.0
291 326 },
292 327 "type": "text"
293 328 },
294 329 {
295 330 "buffer": 1,
296 "file": "test_fft/fft_test_functions.py",
331 "file": "test_fft/test_sm_functions.py",
297 332 "settings":
298 333 {
299 "buffer_size": 3885,
334 "buffer_size": 3914,
300 335 "regions":
301 336 {
302 337 },
303 338 "selection":
304 339 [
305 340 [
306 2140,
307 2140
341 2764,
342 2764
308 343 ]
309 344 ],
310 345 "settings":
@@ -313,7 +348,7
313 348 "translate_tabs_to_spaces": false
314 349 },
315 350 "translation.x": 0.0,
316 "translation.y": 1081.0,
351 "translation.y": 1404.0,
317 352 "zoom_level": 1.0
318 353 },
319 354 "type": "text"
@@ -323,15 +358,15
323 358 "file": "test_fft/register_addresses_fft_test.py",
324 359 "settings":
325 360 {
326 "buffer_size": 798,
361 "buffer_size": 873,
327 362 "regions":
328 363 {
329 364 },
330 365 "selection":
331 366 [
332 367 [
333 717,
334 717
368 703,
369 703
335 370 ]
336 371 ],
337 372 "settings":
@@ -339,7 +374,7
339 374 "syntax": "Packages/Python/Python.tmLanguage"
340 375 },
341 376 "translation.x": 0.0,
342 "translation.y": 0.0,
377 "translation.y": 108.0,
343 378 "zoom_level": 1.0
344 379 },
345 380 "type": "text"
@@ -411,6 +446,6
411 446 "show_open_files": false,
412 447 "show_tabs": true,
413 448 "side_bar_visible": true,
414 "side_bar_width": 255.0,
449 "side_bar_width": 289.0,
415 450 "status_bar_visible": true
416 451 }
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1 NO CONTENT: modified file, binary diff hidden
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@@ -68,49 +68,6 def is_MEM_IN_SM_Emty( ):
68 68 ret = 1
69 69 return ret
70 70
71 def print_reg_sm( ):
72 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
73 out_ren = (sm_reg[0] & 0x00000003)
74 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
75 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
76 print "sm_reg = " + bin( sm_reg[0] & 0x3f ) \
77 + ", out_ren = " + bin( out_ren ) \
78 + ", MEM_OUT_SM_Full = " + bin( MEM_OUT_SM_Full ) \
79 + ", MEM_OUT_SM_Empty = " + bin( MEM_OUT_SM_Empty )
80 RMAPPlugin0.ProcessPendingEvents()
81
82 def is_MEM_OUT_SM_Empty( ):
83 ret = 0
84 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
85 MEM_OUT_SM_Empty = (sm_reg[0] & 0x00000030) >> 4
86 if MEM_OUT_SM_Empty == 0x3:
87 ret = 1
88 return ret
89
90 def is_MEM_OUT_SM_Full( ):
91 ret = 0
92 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
93 MEM_OUT_SM_Full = (sm_reg[0] & 0x0000000c) >> 2
94 if MEM_OUT_SM_Full != 0x0:
95 ret = 1
96 return ret
97
98 def is_MEM_OUT_SM_Full_FIFO_0( ):
99 ret = 0
100 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
101 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000004) >> 3
102 if MEM_OUT_SM_Full == 0x01:
103 ret = 1
104 return ret
105
106 def is_MEM_OUT_SM_Full_FIFO_1( ):
107 ret = 0
108 sm_reg = RMAPPlugin0.Read( address_CTRL_SM, 1)
109 MEM_OUT_SM_Full = (sm_reg[0] & 0x00000008) >> 3
110 if MEM_OUT_SM_Full == 0x01:
111 ret = 1
112 return ret
113
114 71 def out_locked_AND_out_reuse_AND_out_ren( ):
115 72 # reuse => 0111 1111 1111 1111
116 73 RMAPPlugin0.Write( address_CTRL, [0x00007fff] )
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1 NO CONTENT: modified file, binary diff hidden
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@@ -25,6 +25,9 address_CTRL = 0x80000f44
25 25 address_MEM_OUT_SM_0= 0x80000f30
26 26 address_MEM_OUT_SM_1= 0x80000f34
27 27
28 mask_REN_FIFO_0 = 0xfffffffe # 1110
29 mask_REN_FIFO_1 = 0xfffffffd # 1101
30
28 31 address_CTRL_SM = 0x80000f38
29 32
30 33 #
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1 NO CONTENT: modified file, binary diff hidden
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@@ -6,6 +6,7 import matplotlib.pyplot as plt
6 6
7 7 from test_fft.register_addresses_fft_test import *
8 8 from test_fft.fft_test_functions import *
9 from test_fft.test_sm_functions import *
9 10
10 11 print_custom( '*' )
11 12 print_custom( '*' )
@@ -28,7 +29,7 cwf_f1 = np.zeros( 1000 )
28 29 #################
29 30 # BUILD WAVEFORMS
30 31 nbSamples = 256
31 nbComponentsPerMatrix = 25
32 nbComponentsPerMatrix = 15
32 33 nbFrequencyBins = 128
33 34 #wfrm0 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnV )
34 35 #wfrm1 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnE1 )
@@ -36,9 +37,9 nbFrequencyBins = 128
36 37 #wfrm3 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnB1 )
37 38 #wfrm4 = getWaveFromRecord( cwf_f1, nbSamples, 0, columnB2 )
38 39 wfrm0 = sineWave( 256, 10, 1000 )
39 wfrm1 = sineWave( 256, 20, 1000 )
40 wfrm2 = sineWave( 256, 30, 1000 )
41 wfrm3 = sineWave( 256, 40, 1000 )
40 wfrm1 = sineWave( 256, 10, 1000 )
41 wfrm2 = sineWave( 256, 20, 1000 )
42 wfrm3 = sineWave( 256, 20, 1000 )
42 43 wfrm4 = sineWave( 256, 50, 1000 )
43 44
44 45 ################
@@ -61,42 +62,69 for k in range(nbSamples):
61 62
62 63 print_custom( "1) data written in FIFOs" )
63 64
64 print_reg_sm( )
65
66 # wait for SM_OUT_Full
67 while ( is_MEM_OUT_SM_Full() ) == 0:
68 print_custom( "SM not full" )
69
70 print_reg_sm( )
71
72 65 ################
73 66 # SM FIRST READ
74 67 print_custom( "======= SM FIRST READ" )
75 68
76 69 components = []
77 70
78 if is_MEM_OUT_SM_Full_FIFO_0():
79 print_custom( "FIFO_0 is full" )
71 wait_for_FIFO_0_or_1_Full()
72
73 if is_MEM_OUT_SM_Full_FIFO_0( ):
74 address_MEM_OUT_SM = address_MEM_OUT_SM_1
75 fifo_to_wait_for = 0
76 elif is_MEM_OUT_SM_Full_FIFO_1( ):
80 77 address_MEM_OUT_SM = address_MEM_OUT_SM_0
81 elif is_MEM_OUT_SM_Full_FIFO_1():
82 print_custom( "FIFO_1 is full")
83 address_MEM_OUT_SM = address_MEM_OUT_SM_1
84 else:
85 print_custom( "/!\ no MEM_OUT_SM FIFO full /!\ " )
78 fifo_to_wait_for = 1
86 79
87 80 for component in range(nbComponentsPerMatrix):
88 print_custom( "component = " + str( component ) )
89 currentComp = np.zeros( nbFrequencyBins )
90 for frequencyBin in range(nbFrequencyBins):
91 # read enable => 0000 0000 0000 0000
92 if is_MEM_OUT_SM_Empty( ) == 1:
93 print_custom( "component = " + str( component ) \
94 + " bin = " + str( frequencyBin ) )
95 val = RMAPPlugin0.Read( address_MEM_OUT_SM, 1)
96 RMAPPlugin0.Write( address_CTRL_SM, [0x00000000] )
97 currentComp[frequencyBin] = val[0]
98 RMAPPlugin0.ProcessPendingEvents()
99 components.append( currentComp )
81 print_custom( "==== component = " + str( component )
82 + ", read @" + hex(address_MEM_OUT_SM & 0xffffffff) )
83 print_reg_sm( )
84 currentComp_re = np.zeros( nbFrequencyBins )
85 currentComp_im = np.zeros( nbFrequencyBins )
86 if (component == 0) | (component == 12):
87 wait_for_FIFO_Full( fifo_to_wait_for )
88 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
89 components.append( currentComp_re )
90 elif (component == 5) | (component == 9):
91 wait_for_FIFO_Full( fifo_to_wait_for )
92 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
93 components.append( currentComp_re )
94 elif (component == 1) | (component == 3) | (component == 7):
95 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
96 components.append( currentComp_re )
97 components.append( currentComp_im )
98 wait_for_FIFO_Full( fifo_to_wait_for )
99 elif (component == 2) | (component == 6) | (component == 10):
100 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
101 components.append( currentComp_re )
102 components.append( currentComp_im )
103 wait_for_FIFO_Full( fifo_to_wait_for )
104 elif (component == 4) | (component == 8):
105 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
106 components.append( currentComp_re )
107 components.append( currentComp_im )
108 elif (component == 11) | (component == 13):
109 currentComp_re, currentComp_im = read_SM_Re_Im( nbFrequencyBins, address_MEM_OUT_SM )
110 components.append( currentComp_re )
111 components.append( currentComp_im )
112 elif (component == 14):
113 currentComp_re = read_SM_Re( nbFrequencyBins, address_MEM_OUT_SM )
114 components.append( currentComp_re )
115 else:
116 print_custom( "unexpected value for component" )
117 # change FIFO
118 if address_MEM_OUT_SM == address_MEM_OUT_SM_0:
119 address_MEM_OUT_SM = address_MEM_OUT_SM_1
120 fifo_to_wait_for = 0
121 elif address_MEM_OUT_SM == address_MEM_OUT_SM_1:
122 address_MEM_OUT_SM = address_MEM_OUT_SM_0
123 fifo_to_wait_for = 1
124
125 print_custom( "======= READ COMPLETE" )
126
127 print_reg_sm( )
100 128
101 129 # PLOT SM
102 130
@@ -115,36 +143,48 plt.subplot(235)
115 143 plt.plot(wfrm4, 'm')
116 144
117 145 plt.figure( 2 )
146
118 147 plt.subplot(231)
119 plt.plot(components[0][:])
120 plt.plot(components[1][:])
121 plt.plot(components[2][:])
122 plt.plot(components[3][:])
148 plt.plot(components[0], label='0')
149 plt.plot(components[1], label='1')
150 plt.plot(components[2], label='2')
151 plt.plot(components[3], label='3')
152 plt.legend(loc='upper right')
153
123 154 plt.subplot(232)
124 plt.plot(components[4][:])
125 plt.plot(components[5][:])
126 plt.plot(components[6][:])
127 plt.plot(components[7][:])
155 plt.plot(components[4], label='4')
156 plt.plot(components[5], label='5')
157 plt.plot(components[6], label='6')
158 plt.plot(components[7], label='7')
159 plt.legend(loc='upper right')
160
128 161 plt.subplot(233)
129 plt.plot(components[8][:])
130 plt.plot(components[9][:])
131 plt.plot(components[10][:])
132 plt.plot(components[11][:])
162 plt.plot(components[8], label='8')
163 plt.plot(components[9], label='9')
164 plt.plot(components[10], label='10')
165 plt.plot(components[11], label='11')
166 plt.legend(loc='upper right')
167
133 168 plt.subplot(234)
134 plt.plot(components[12][:])
135 plt.plot(components[13][:])
136 plt.plot(components[14][:])
137 plt.plot(components[15][:])
169 plt.plot(components[12], label='12')
170 plt.plot(components[13], label='13')
171 plt.plot(components[14], label='14')
172 plt.plot(components[15], label='15')
173 plt.legend(loc='upper right')
174
138 175 plt.subplot(235)
139 plt.plot(components[16][:])
140 plt.plot(components[17][:])
141 plt.plot(components[18][:])
142 plt.plot(components[19][:])
176 plt.plot(components[16], label='16')
177 plt.plot(components[17], label='17')
178 plt.plot(components[18], label='18')
179 plt.plot(components[19], label='19')
180 plt.legend(loc='upper right')
181
143 182 plt.subplot(236)
144 plt.plot(components[20][:])
145 plt.plot(components[21][:])
146 plt.plot(components[22][:])
147 plt.plot(components[23][:])
148 plt.plot(components[24][:])
183 plt.plot(components[20], label='20')
184 plt.plot(components[21], label='21')
185 plt.plot(components[22], label='22')
186 plt.plot(components[23], label='23')
187 plt.plot(components[24], label='24')
188 plt.legend(loc='upper right')
149 189
150 190 plt.show() No newline at end of file
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