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Task #13

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Mise à jour de la documentation VHDL

Added by paul leroy almost 11 years ago. Updated over 10 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Jean-Christophe Pellion
Start date:
03/12/2013
Due date:
% Done:

0%

Estimated time:
revision:

Description

Vérifier la prise en compte des remarques de Vincent dans les documents FPGA (doc système et doc IP).

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