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Task #13

Mise à jour de la documentation VHDL

Added by paul leroy almost 8 years ago. Updated over 7 years ago.

Status:
Closed
Priority:
Normal
Start date:
03/12/2013
Due date:
% Done:

0%

Estimated time:
revision:
r0

Description

Vérifier la prise en compte des remarques de Vincent dans les documents FPGA (doc système et doc IP).

History

#1 Updated by paul leroy over 7 years ago

  • Status changed from New to Closed

Action à clore suite à point LFR 09 janvier 2014.

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