HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r407:fe963db0333b

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designs/LFR_simu/Makefile +6 -3

             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
             #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-            VHDLSYNFILES=config.vhd leon3mp.vhd
+            VHDLSYNFILES=
-            VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd
+            VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd
             SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
             #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
             	./lpp_cna \
             	./lpp_uart \
             	./lpp_usb \
+            	./dsp/lpp_fft_rtax \
             FILESKIP = i2cmst.vhd \
             	APB_MULTI_DIODE.vhd \
             	APB_MULTI_DIODE.vhd \
             	Top_MatrixSpec.vhd \
-            	APB_FFT.vhd
+            	APB_FFT.vhd \
+            	lpp_lfr_apbreg.vhd \
+            	CoreFFT.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile

designs/LFR_simu/run_tb_waveform.do +1 -16

@@ -1,19 +1,4
1	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd	1	vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
2	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
9	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
11	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
12	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
13	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
14	vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
15
16	vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
17		2
18	vcom -quiet -93 -work lpp testbench_package.vhd	3	vcom -quiet -93 -work lpp testbench_package.vhd
19		4

designs/LFR_simu/tb_waveform.vhd +9 -3

             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
-            USE lpp.testbench_package.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.CY7C1061DV33_pkg.ALL;
+            USE work.testbench_package.ALL;
             ENTITY testbench IS
             END;
               -- AD Converter RHF1401
               SIGNAL sample     : Samples14v(7 DOWNTO 0);
+              SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val : STD_LOGIC;
               -- AHB/APB SIGNAL
                 PORT MAP (
                   clk             => clk25MHz,
                   rstn            => rstn,
-                  sample_B        => sample(2 DOWNTO 0),
+                  sample_B        => sample_s(2 DOWNTO 0),
-                  sample_E        => sample(7 DOWNTO 3),
+                  sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi,
                   apbo            => apbo(15),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_bw);
+              all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+                sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
+              END GENERATE all_sample;
               -----------------------------------------------------------------------------
               ---  AHB CONTROLLER  -------------------------------------------------

designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd +1 -1

                       WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
                       WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
-                      WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
+                      WHEN "010001" => prdata(4 DOWNTO 0)   <= reg_ftt.out_ren;
                                        prdata(9 DOWNTO 5)   <= reg_ftt.out_reuse;
                                        prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
                                        prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;

lib/lpp/dirs.txt +3 -3

             ./lpp_amba
             ./dsp/iir_filter
             ./dsp/lpp_downsampling
+            ./dsp/lpp_fft_rtax
+            ./lpp_memory
             ./dsp/lpp_fft
-            ./dsp/lpp_fft_rtax
             ./lfr_time_management
             ./lpp_ad_Conv
             ./lpp_bootloader
             ./lpp_demux
             ./lpp_Header
             ./lpp_matrix
-            ./lpp_memory
-            ./lpp_dma
             ./lpp_uart
             ./lpp_usb
             ./lpp_waveform
+            ./lpp_dma
             ./lpp_top_lfr
             ./lpp_Header
             ./lpp_leon3_soc

lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +3 -2

                 WEN <= NOT ram_write;
                 REN <= NOT ram_read;
             --    RAMblk : RAM_CEL_N
-                RAMblk : RAM_CEL_N
+            --       GENERIC MAP(Input_SZ_1)
-                  GENERIC MAP(Input_SZ_1)
+                RAMblk : RAM_CEL
+                  GENERIC MAP(Input_SZ_1, 8)
                   PORT MAP(
                     WD    => WD,
                     RD    => RD,

lib/lpp/dsp/lpp_fft/vhdlsyn.txt +1 -1

+            fft_components.vhd
             lpp_fft.vhd
             actar.vhd
             actram.vhd
             CoreFFT.vhd
-            fft_components.vhd
             fftDp.vhd
             fftSm.vhd
             primitives.vhd

lib/lpp/lpp_matrix/vhdlsyn.txt +1 -1

+            lpp_matrix.vhd
             ALU_Driver.vhd
             APB_Matrix.vhd
             ReUse_CTRLR.vhd
             TopMatrix_PDR.vhd
             TopSpecMatrix.vhd
             Top_MatrixSpec.vhd
-            lpp_matrix.vhd

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