# HG changeset patch
# User pellion
# Date 2014-08-29 11:10:46
# Node ID fe963db0333b7d26e2a231fb850ebb998cfe64b7
# Parent  c218371d90d3de2454049fdee4376ff8ffe62469

temp

diff --git a/designs/LFR_simu/Makefile b/designs/LFR_simu/Makefile
--- a/designs/LFR_simu/Makefile
+++ b/designs/LFR_simu/Makefile
@@ -12,8 +12,8 @@ EFFORT=high
 XSTOPT=
 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-VHDLSYNFILES=config.vhd leon3mp.vhd
-VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd
+VHDLSYNFILES=
+VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd 
 SIMTOP=testbench
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
@@ -36,12 +36,15 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt
 	./lpp_cna \
 	./lpp_uart \
 	./lpp_usb \
+	./dsp/lpp_fft_rtax \
 
 FILESKIP = i2cmst.vhd \
 	APB_MULTI_DIODE.vhd \
 	APB_MULTI_DIODE.vhd \
 	Top_MatrixSpec.vhd \
-	APB_FFT.vhd
+	APB_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd
 
 include $(GRLIB)/bin/Makefile
 include $(GRLIB)/software/leon3/Makefile
diff --git a/designs/LFR_simu/run_tb_waveform.do b/designs/LFR_simu/run_tb_waveform.do
--- a/designs/LFR_simu/run_tb_waveform.do
+++ b/designs/LFR_simu/run_tb_waveform.do
@@ -1,19 +1,4 @@
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
-
-vcom -quiet  -93  -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
-
-vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
-vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
-vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
-vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
-
-vcom -quiet  -93  -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
+vcom -quiet  -93  -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
 
 vcom -quiet  -93  -work lpp testbench_package.vhd
 
diff --git a/designs/LFR_simu/tb_waveform.vhd b/designs/LFR_simu/tb_waveform.vhd
--- a/designs/LFR_simu/tb_waveform.vhd
+++ b/designs/LFR_simu/tb_waveform.vhd
@@ -39,12 +39,13 @@ LIBRARY lpp;
 USE lpp.lpp_waveform_pkg.ALL;
 USE lpp.lpp_memory.ALL;
 USE lpp.lpp_ad_conv.ALL;
-USE lpp.testbench_package.ALL;
 USE lpp.lpp_lfr_pkg.ALL;
 USE lpp.iir_filter.ALL;
 USE lpp.general_purpose.ALL;
 USE lpp.CY7C1061DV33_pkg.ALL;
 
+USE work.testbench_package.ALL;
+
 ENTITY testbench IS
 END;
 
@@ -111,6 +112,7 @@ ARCHITECTURE behav OF testbench IS
 
   -- AD Converter RHF1401
   SIGNAL sample     : Samples14v(7 DOWNTO 0);
+  SIGNAL sample_s    : Samples(7 DOWNTO 0);
   SIGNAL sample_val : STD_LOGIC;
 
   -- AHB/APB SIGNAL
@@ -314,8 +316,8 @@ BEGIN
     PORT MAP (
       clk             => clk25MHz,
       rstn            => rstn,
-      sample_B        => sample(2 DOWNTO 0),
-      sample_E        => sample(7 DOWNTO 3),
+      sample_B        => sample_s(2 DOWNTO 0),
+      sample_E        => sample_s(7 DOWNTO 3),
       sample_val      => sample_val,
       apbi            => apbi,
       apbo            => apbo(15),
@@ -324,6 +326,10 @@ BEGIN
       coarse_time     => coarse_time,
       fine_time       => fine_time,
       data_shaping_BW => bias_fail_bw);
+  
+  all_sample: FOR I IN 7 DOWNTO 0 GENERATE
+    sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
+  END GENERATE all_sample;
 
   -----------------------------------------------------------------------------
   ---  AHB CONTROLLER  -------------------------------------------------
diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd
--- a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd
+++ b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd
@@ -164,7 +164,7 @@ BEGIN  -- beh
           WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
           WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
 
-          WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
+          WHEN "010001" => prdata(4 DOWNTO 0)   <= reg_ftt.out_ren;
                            prdata(9 DOWNTO 5)   <= reg_ftt.out_reuse;
                            prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
                            prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;
diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt
--- a/lib/lpp/dirs.txt
+++ b/lib/lpp/dirs.txt
@@ -6,8 +6,9 @@
 ./lpp_amba
 ./dsp/iir_filter
 ./dsp/lpp_downsampling
+./dsp/lpp_fft_rtax
+./lpp_memory
 ./dsp/lpp_fft
-./dsp/lpp_fft_rtax
 ./lfr_time_management
 ./lpp_ad_Conv
 ./lpp_bootloader
@@ -16,11 +17,10 @@
 ./lpp_demux
 ./lpp_Header
 ./lpp_matrix
-./lpp_memory
-./lpp_dma
 ./lpp_uart
 ./lpp_usb
 ./lpp_waveform
+./lpp_dma
 ./lpp_top_lfr
 ./lpp_Header
 ./lpp_leon3_soc
diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
--- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
+++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
@@ -73,8 +73,9 @@ BEGIN
     WEN <= NOT ram_write;
     REN <= NOT ram_read;
 --    RAMblk : RAM_CEL_N
-    RAMblk : RAM_CEL_N
-      GENERIC MAP(Input_SZ_1)
+--       GENERIC MAP(Input_SZ_1)
+    RAMblk : RAM_CEL
+      GENERIC MAP(Input_SZ_1, 8)
       PORT MAP(
         WD    => WD,
         RD    => RD,
diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
--- a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
+++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
@@ -1,8 +1,8 @@
+fft_components.vhd
 lpp_fft.vhd
 actar.vhd
 actram.vhd
 CoreFFT.vhd
-fft_components.vhd
 fftDp.vhd
 fftSm.vhd
 primitives.vhd
diff --git a/lib/lpp/lpp_matrix/vhdlsyn.txt b/lib/lpp/lpp_matrix/vhdlsyn.txt
--- a/lib/lpp/lpp_matrix/vhdlsyn.txt
+++ b/lib/lpp/lpp_matrix/vhdlsyn.txt
@@ -1,3 +1,4 @@
+lpp_matrix.vhd
 ALU_Driver.vhd
 APB_Matrix.vhd
 ReUse_CTRLR.vhd
@@ -11,4 +12,3 @@ Starter.vhd
 TopMatrix_PDR.vhd
 TopSpecMatrix.vhd
 Top_MatrixSpec.vhd
-lpp_matrix.vhd