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pellion -
r611:ec07182522e1 simu_with_Leon3
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@@ -34,7 +34,7 ENTITY cic_lfr_control_r2 IS
34 PORT (
34 PORT (
35 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
37 -- run : IN STD_LOGIC;
38 --
38 --
39 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
@@ -55,7 +55,7 ARCHITECTURE beh OF cic_lfr_control_r2 I
55
55
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
56 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
57
57
58 SIGNAL nb_data_receipt : INTEGER := 0;
58 SIGNAL nb_data_receipt : INTEGER RANGE 0 TO 255:= 0;
59 SIGNAL current_cmd : INTEGER := 0;
59 SIGNAL current_cmd : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
60 SIGNAL current_channel : INTEGER := 0;
61 SIGNAL sample_16_odd : STD_LOGIC;
61 SIGNAL sample_16_odd : STD_LOGIC;
@@ -246,4 +246,4 BEGIN
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248
248
249 END beh;
249 END beh; No newline at end of file
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@@ -280,7 +280,7 BEGIN
280 PORT MAP (
280 PORT MAP (
281 clk => clk,
281 clk => clk,
282 rstn => rstn,
282 rstn => rstn,
283 run => run,
283 -- run => run,
284 data_in_valid => data_in_valid,
284 data_in_valid => data_in_valid,
285 data_out_16_valid => data_out_16_valid_s,
285 data_out_16_valid => data_out_16_valid_s,
286 data_out_256_valid => data_out_256_valid_s,
286 data_out_256_valid => data_out_256_valid_s,
@@ -390,4 +390,4 BEGIN
390 END GENERATE all_bits;
390 END GENERATE all_bits;
391 END GENERATE all_channel_out_v;
391 END GENERATE all_channel_out_v;
392
392
393 END beh; No newline at end of file
393 END beh;
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@@ -139,7 +139,7 PACKAGE cic_pkg IS
139 PORT (
139 PORT (
140 clk : IN STD_LOGIC;
140 clk : IN STD_LOGIC;
141 rstn : IN STD_LOGIC;
141 rstn : IN STD_LOGIC;
142 run : IN STD_LOGIC;
142 -- run : IN STD_LOGIC;
143 data_in_valid : IN STD_LOGIC;
143 data_in_valid : IN STD_LOGIC;
144 data_out_16_valid : OUT STD_LOGIC;
144 data_out_16_valid : OUT STD_LOGIC;
145 data_out_256_valid : OUT STD_LOGIC;
145 data_out_256_valid : OUT STD_LOGIC;
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@@ -68,7 +68,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL
68 wait_valid_last_output_2);
68 wait_valid_last_output_2);
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
69 SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
70
70
71 SIGNAL alu_selected_coeff : INTEGER;
71 SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
72 SIGNAL Chanel_ongoing : INTEGER;
72 SIGNAL Chanel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
73 SIGNAL Cel_ongoing : INTEGER;
74
74
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@@ -44,7 +44,7 END Downsampling;
44
44
45 ARCHITECTURE beh OF Downsampling IS
45 ARCHITECTURE beh OF Downsampling IS
46
46
47 SIGNAL counter : INTEGER;
47 SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1;
48
48
49 BEGIN -- beh
49 BEGIN -- beh
50
50
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@@ -123,7 +123,7 ARCHITECTURE Behavioral OF apb_lfr_manag
123 SIGNAL force_reset : STD_LOGIC;
123 SIGNAL force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
124 SIGNAL previous_force_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
125 SIGNAL soft_reset : STD_LOGIC;
126 SIGNAL soft_reset_sync : STD_LOGIC;
126
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
129
129
@@ -521,4 +521,5 BEGIN
521 );
521 );
522
522
523 DAC_CAL_EN <= DAC_CAL_EN_s;
523 DAC_CAL_EN <= DAC_CAL_EN_s;
524
524 END Behavioral;
525 END Behavioral;
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@@ -114,6 +114,31 PACKAGE lpp_lfr_management IS
114 fine_time_add : IN STD_LOGIC;
114 fine_time_add : IN STD_LOGIC;
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
115 fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
116 END COMPONENT;
116 END COMPONENT;
117
118 COMPONENT apb_lfr_management_nocal
119 GENERIC (
120 tech : INTEGER;
121 pindex : INTEGER;
122 paddr : INTEGER;
123 pmask : INTEGER;
124 NB_SECOND_DESYNC : INTEGER);
125 PORT (
126 clk25MHz : IN STD_LOGIC;
127 resetn_25MHz : IN STD_LOGIC;
128 grspw_tick : IN STD_LOGIC;
129 apbi : IN apb_slv_in_type;
130 apbo : OUT apb_slv_out_type;
131 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
132 HK_val : IN STD_LOGIC;
133 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
134 DAC_SDO : OUT STD_LOGIC;
135 DAC_SCK : OUT STD_LOGIC;
136 DAC_SYNC : OUT STD_LOGIC;
137 DAC_CAL_EN : OUT STD_LOGIC;
138 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
140 LFR_soft_rstn : OUT STD_LOGIC);
141 END COMPONENT;
117
142
118 END lpp_lfr_management;
143 END lpp_lfr_management;
119
144
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@@ -1,6 +1,7
1 lpp_lfr_management.vhd
1 lpp_lfr_management.vhd
2 lpp_lfr_management_apbreg_pkg.vhd
2 lpp_lfr_management_apbreg_pkg.vhd
3 apb_lfr_management.vhd
3 apb_lfr_management.vhd
4 apb_lfr_management_nocal.vhd
4 lfr_time_management.vhd
5 lfr_time_management.vhd
5 fine_time_counter.vhd
6 fine_time_counter.vhd
6 coarse_time_counter.vhd
7 coarse_time_counter.vhd
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@@ -30,7 +30,7 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
34 SIGNAL cnv_s : STD_LOGIC;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
@@ -225,4 +225,3 END ar_top_ad_conv_RHF1401;
225
225
226
226
227
227
228
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@@ -19,81 +19,82
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 LIBRARY IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
24 USE IEEE.NUMERIC_STD.ALL;
25
25
26 entity dynamic_freq_div is
26 ENTITY dynamic_freq_div IS
27 generic(
27 GENERIC(
28 PRESZ : integer range 1 to 32:=4;
28 PRESZ : INTEGER RANGE 1 TO 32 := 4;
29 PREMAX : integer := 16#FFFFFF#;
29 PREMAX : INTEGER := 16#FFFFFF#;
30 CPTSZ : integer range 1 to 32:=16
30 CPTSZ : INTEGER RANGE 1 TO 32 := 16
31 );
31 );
32 Port (
32 PORT (
33 clk : in STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : in STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
35 pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
36 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
36 N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
37 Reload : in std_logic;
37 Reload : IN STD_LOGIC;
38 clk_out : out STD_LOGIC
38 clk_out : OUT STD_LOGIC
39 );
39 );
40 end dynamic_freq_div;
40 END dynamic_freq_div;
41
41
42 architecture Behavioral of dynamic_freq_div is
42 ARCHITECTURE Behavioral OF dynamic_freq_div IS
43 constant prescaller_reg_sz : integer := 2**PRESZ;
43 CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ;
44 constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
44 CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1');
45 signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
45 SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
46 SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0');
47 signal internal_clk : std_logic:='0';
47 SIGNAL internal_clk : STD_LOGIC := '0';
48 signal internal_clk_reg : std_logic:='0';
48 SIGNAL internal_clk_reg : STD_LOGIC := '0';
49 signal clk_out_reg : std_logic:='0';
49 SIGNAL clk_out_reg : STD_LOGIC := '0';
50
51 BEGIN
50
52
51 begin
53 max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE
52
54
53 max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
55 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE
54
55 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
56 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
56 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
57 end generate;
57 END GENERATE;
58 max1: if UNSIGNED(PREMAX_max) > PREMAX generate
58
59 internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
59 max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE
60 internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE
60 prescaller_reg(PREMAX);
61 prescaller_reg(PREMAX);
61 end generate;
62 END GENERATE;
62
63
63
64
64
65
65 prescaller: process(rstn, clk)
66 prescaller : PROCESS(rstn, clk)
66 begin
67 BEGIN
67 if rstn='0' then
68 IF rstn = '0' then
68 prescaller_reg <= (others => '0');
69 prescaller_reg <= (OTHERS => '0');
69 elsif clk'event and clk = '1' then
70 ELSIF clk'EVENT AND clk = '1' THEN
70 prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
71 prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1);
71 end if;
72 END IF;
72 end process;
73 END PROCESS;
73
74
74
75
75 clk_out <= clk_out_reg;
76 clk_out <= clk_out_reg;
76
77
77 counter: process(rstn, clk)
78 counter : PROCESS(rstn, clk)
78 begin
79 BEGIN
79 if rstn='0' then
80 IF rstn = '0' then
80 cpt_reg <= (others => '0');
81 cpt_reg <= (OTHERS => '0');
81 internal_clk_reg <= '0';
82 internal_clk_reg <= '0';
82 clk_out_reg <= '0';
83 clk_out_reg <= '0';
83 elsif clk'event and clk = '1' then
84 ELSIF clk'EVENT AND clk = '1' THEN
84 internal_clk_reg <= internal_clk;
85 internal_clk_reg <= internal_clk;
85 if Reload = '1' then
86 IF Reload = '1' THEN
86 clk_out_reg <= '0';
87 clk_out_reg <= '0';
87 cpt_reg <= (others => '0');
88 cpt_reg <= (OTHERS => '0');
88 elsif (internal_clk = '1' and internal_clk_reg = '0') then
89 ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN
89 if cpt_reg = N then
90 IF cpt_reg = N THEN
90 clk_out_reg <= not clk_out_reg;
91 clk_out_reg <= NOT clk_out_reg;
91 cpt_reg <= (others => '0');
92 cpt_reg <= (OTHERS => '0');
92 else
93 ELSE
93 cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
94 cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1);
94 end if;
95 END IF;
95 end if;
96 END IF;
96 end if;
97 END IF;
97 end process;
98 END PROCESS;
98
99
99 end Behavioral; No newline at end of file
100 END Behavioral;
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@@ -65,7 +65,7 ARCHITECTURE beh OF DMA_SubSystem IS
65 PORT (
65 PORT (
66 clk : IN STD_LOGIC;
66 clk : IN STD_LOGIC;
67 rstn : IN STD_LOGIC;
67 rstn : IN STD_LOGIC;
68 run : IN STD_LOGIC;
68 -- run : IN STD_LOGIC;
69 buffer_new : IN STD_LOGIC;
69 buffer_new : IN STD_LOGIC;
70 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
70 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
71 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
71 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
@@ -222,7 +222,7 BEGIN -- beh
222 PORT MAP (
222 PORT MAP (
223 clk => clk,
223 clk => clk,
224 rstn => rstn,
224 rstn => rstn,
225 run => run,
225 -- run => run,
226
226
227 buffer_new => buffer_new(I),
227 buffer_new => buffer_new(I),
228 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
228 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
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@@ -10,7 +10,7 ENTITY DMA_SubSystem_GestionBuffer IS
10 PORT (
10 PORT (
11 clk : IN STD_LOGIC;
11 clk : IN STD_LOGIC;
12 rstn : IN STD_LOGIC;
12 rstn : IN STD_LOGIC;
13 run : IN STD_LOGIC;
13 -- run : IN STD_LOGIC;
14 --
14 --
15 buffer_new : IN STD_LOGIC;
15 buffer_new : IN STD_LOGIC;
16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
16 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
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@@ -1,255 +1,251
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
31 USE grlib.devices.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
45 GENERIC (
46 hindex : INTEGER := 2;
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
49 version : IN INTEGER := 0
50 );
50 );
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- FIFO Interface
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
62
63 -- Controls
63 -- Controls
64 send : IN STD_LOGIC;
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
68 );
69 END;
69 END;
70
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
72
73 CONSTANT HConfig : AHB_Config_Type := (
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81
82
82 SIGNAL data_window : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
83 SIGNAL ctrl_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
84
85
85 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL bus_request : STD_LOGIC;
86
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL HREADY_pre : STD_LOGIC;
88
88 SIGNAL HREADY_falling : STD_LOGIC;
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
89
90
90 SIGNAL inhib_ren : STD_LOGIC;
91 SIGNAL HREADY_pre : STD_LOGIC;
91
92 SIGNAL HREADY_falling : STD_LOGIC;
92 BEGIN
93
93
94 SIGNAL inhib_ren : STD_LOGIC;
94 -----------------------------------------------------------------------------
95
95 AHB_Master_Out.HCONFIG <= HConfig;
96 BEGIN
96 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
97
97 AHB_Master_Out.HINDEX <= hindex;
98 -----------------------------------------------------------------------------
98 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
99 AHB_Master_Out.HCONFIG <= HConfig;
99 AHB_Master_Out.HIRQ <= (OTHERS => '0');
100 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
100 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
101 AHB_Master_Out.HINDEX <= hindex;
101 AHB_Master_Out.HWRITE <= '1';
102 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
102
103 AHB_Master_Out.HIRQ <= (OTHERS => '0');
103 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
104 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
104
105 AHB_Master_Out.HWRITE <= '1';
105 --AHB_Master_Out.HBUSREQ <= bus_request;
106
106 --AHB_Master_Out.HLOCK <= data_window;
107 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
107
108
108 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
109 --AHB_Master_Out.HBUSREQ <= bus_request;
109 -- '1' WHEN ctrl_window = '1' ELSE
110 --AHB_Master_Out.HLOCK <= data_window;
110 -- '0';
111
111
112 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
112 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
113 -- '1' WHEN ctrl_window = '1' ELSE
113 -- '1' WHEN ctrl_window = '1' ELSE '0';
114 -- '0';
114
115
115 -----------------------------------------------------------------------------
116 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
116 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
117 -- '1' WHEN ctrl_window = '1' ELSE '0';
117 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
120 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
121 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
121 --ren <= NOT beat;
122
122 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
123
124 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
124 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
125 --ren <= NOT beat;
125
126 -----------------------------------------------------------------------------
126
127
127 PROCESS (clk, rstn)
128 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
128 BEGIN -- PROCESS
129
129 IF rstn = '0' THEN -- asynchronous reset (active low)
130
130 state <= IDLE;
131 PROCESS (clk, rstn)
131 done <= '0';
132 BEGIN -- PROCESS
132 ren <= '1';
133 IF rstn = '0' THEN -- asynchronous reset (active low)
133 address_counter_reg <= (OTHERS => '0');
134 state <= IDLE;
134 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
135 done <= '0';
135 AHB_Master_Out.HBUSREQ <= '0';
136 ren <= '1';
136 AHB_Master_Out.HLOCK <= '0';
137 address_counter_reg <= (OTHERS => '0');
137
138 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
138 data_reg <= (OTHERS => '0');
139 AHB_Master_Out.HBUSREQ <= '0';
139
140 AHB_Master_Out.HLOCK <= '0';
140 HREADY_pre <= '0';
141
141 inhib_ren <= '0';
142 data_reg <= (OTHERS => '0');
142 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
143
143 HREADY_pre <= AHB_Master_In.HREADY;
144 HREADY_pre <= '0';
144
145 inhib_ren <= '0';
145 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
146 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
146 data_reg <= data;
147 HREADY_pre <= AHB_Master_In.HREADY;
147 END IF;
148
148
149 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
149 done <= '0';
150 data_reg <= data;
150 ren <= '1';
151 END IF;
151 inhib_ren <= '0';
152
152 CASE state IS
153 done <= '0';
153 WHEN IDLE =>
154 ren <= '1';
154 AHB_Master_Out.HBUSREQ <= '0';
155 inhib_ren <= '0';
155 AHB_Master_Out.HLOCK <= '0';
156 CASE state IS
156 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
157 WHEN IDLE =>
157 address_counter_reg <= (OTHERS => '0');
158 AHB_Master_Out.HBUSREQ <= '0';
158 IF send = '1' THEN
159 AHB_Master_Out.HLOCK <= '0';
159 state <= s_INIT_TRANS;
160 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
160 END IF;
161 address_counter_reg <= (OTHERS => '0');
161
162 IF send = '1' THEN
162 WHEN s_INIT_TRANS =>
163 state <= s_INIT_TRANS;
163 AHB_Master_Out.HBUSREQ <= '1';
164 END IF;
164 AHB_Master_Out.HLOCK <= '1';
165
165 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
166 WHEN s_INIT_TRANS =>
166 state <= s_ARBITER;
167 AHB_Master_Out.HBUSREQ <= '1';
167
168 AHB_Master_Out.HLOCK <= '1';
168 WHEN s_ARBITER =>
169 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
169 AHB_Master_Out.HBUSREQ <= '1';
170 state <= s_ARBITER;
170 AHB_Master_Out.HLOCK <= '1';
171
171 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
172 WHEN s_ARBITER =>
172 address_counter_reg <= (OTHERS => '0');
173 AHB_Master_Out.HBUSREQ <= '1';
173
174 AHB_Master_Out.HLOCK <= '1';
174 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 address_counter_reg <= (OTHERS => '0');
176 state <= s_CTRL;
177
177 END IF;
178 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
178
179 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
179 WHEN s_CTRL =>
180 state <= s_CTRL;
180 inhib_ren <= '1';
181 END IF;
181 AHB_Master_Out.HBUSREQ <= '1';
182
182 AHB_Master_Out.HLOCK <= '1';
183 WHEN s_CTRL =>
183 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
184 inhib_ren <= '1';
184 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
185 AHB_Master_Out.HBUSREQ <= '1';
185 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
186 AHB_Master_Out.HLOCK <= '1';
186 state <= s_CTRL_DATA;
187 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
187 --ren <= '0';
188 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
188 END IF;
189 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
189
190 state <= s_CTRL_DATA;
190 WHEN s_CTRL_DATA =>
191 --ren <= '0';
191 AHB_Master_Out.HBUSREQ <= '1';
192 END IF;
192 AHB_Master_Out.HLOCK <= '1';
193
193 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
194 WHEN s_CTRL_DATA =>
194 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
195 AHB_Master_Out.HBUSREQ <= '1';
195 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
196 AHB_Master_Out.HLOCK <= '1';
196 END IF;
197 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
197
198 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
198 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
199 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
199 AHB_Master_Out.HBUSREQ <= '0';
200 END IF;
200 AHB_Master_Out.HLOCK <= '1';--'0';
201
201 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
202 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
202 state <= s_DATA;
203 AHB_Master_Out.HBUSREQ <= '0';
203 END IF;
204 AHB_Master_Out.HLOCK <= '1';--'0';
204
205 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
205 ren <= HREADY_falling;
206 state <= s_DATA;
206
207 END IF;
207 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
208
208 -- ren <= '0';
209 ren <= HREADY_falling;
209 --END IF;
210
210
211 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
211
212 -- ren <= '0';
212 WHEN s_DATA =>
213 --END IF;
213 ren <= HREADY_falling;
214
214
215
215 AHB_Master_Out.HBUSREQ <= '0';
216 WHEN s_DATA =>
216 --AHB_Master_Out.HLOCK <= '0';
217 ren <= HREADY_falling;
217 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
218
218 IF AHB_Master_In.HREADY = '1' THEN
219 AHB_Master_Out.HBUSREQ <= '0';
219 AHB_Master_Out.HLOCK <= '0';
220 --AHB_Master_Out.HLOCK <= '0';
220 state <= IDLE;
221 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
221 done <= '1';
222 IF AHB_Master_In.HREADY = '1' THEN
222 END IF;
223 AHB_Master_Out.HLOCK <= '0';
223
224 state <= IDLE;
224 WHEN OTHERS => NULL;
225 done <= '1';
225 END CASE;
226 END IF;
226 END IF;
227
227 END PROCESS;
228 WHEN OTHERS => NULL;
228
229 END CASE;
229 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
230 END IF;
230 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
231 END PROCESS;
231 -----------------------------------------------------------------------------
232
232
233 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
233
234 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
234 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
235 -----------------------------------------------------------------------------
235
236
236 -----------------------------------------------------------------------------
237
237 --PROCESS (clk, rstn)
238 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
238 --BEGIN -- PROCESS
239
239 -- IF rstn = '0' THEN -- asynchronous reset (active low)
240 -----------------------------------------------------------------------------
240 -- address_counter_reg <= (OTHERS => '0');
241 --PROCESS (clk, rstn)
241 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
242 --BEGIN -- PROCESS
242 -- address_counter_reg <= address_counter;
243 -- IF rstn = '0' THEN -- asynchronous reset (active low)
243 -- END IF;
244 -- address_counter_reg <= (OTHERS => '0');
244 --END PROCESS;
245 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
245
246 -- address_counter_reg <= address_counter;
246 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
247 -- END IF;
247 -- address_counter_reg;
248 --END PROCESS;
248 -----------------------------------------------------------------------------
249
249
250 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
250
251 -- address_counter_reg;
251 END Behavioral; No newline at end of file
252 -----------------------------------------------------------------------------
253
254
255 END Behavioral;
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@@ -251,7 +251,7 PACKAGE lpp_dma_pkg IS
251 PORT (
251 PORT (
252 clk : IN STD_LOGIC;
252 clk : IN STD_LOGIC;
253 rstn : IN STD_LOGIC;
253 rstn : IN STD_LOGIC;
254 run : IN STD_LOGIC;
254 -- run : IN STD_LOGIC;
255 buffer_new : IN STD_LOGIC;
255 buffer_new : IN STD_LOGIC;
256 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
256 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
257 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
257 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
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@@ -46,8 +46,8 USE iap.memctrl.ALL;
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := axcel;--apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := axcel;--apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
@@ -56,11 +56,11 ENTITY leon3_soc IS
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 1;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 0;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
@@ -71,8 +71,8 ENTITY leon3_soc IS
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 19;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
75 USES_IAP_MEMCTRLR : INTEGER := 1;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
77 SRBANKSZ : INTEGER := 8
78
78
@@ -276,7 +276,7 BEGIN
276 l3 : IF CFG_LEON3 = 1 GENERATE
276 l3 : IF CFG_LEON3 = 1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : leon3s -- LEON3 processor
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
@@ -288,7 +288,7 BEGIN
288 END GENERATE leon3_non_radhard;
288 END GENERATE leon3_non_radhard;
289
289
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 cpu : ENTITY gaisler.leon3ft
291 cpu : leon3ft
292 GENERIC MAP (
292 GENERIC MAP (
293 HINDEX => i, --: integer; --CPU_HINDEX,
293 HINDEX => i, --: integer; --CPU_HINDEX,
294 FABTECH => fabtech, --CFG_TECH,
294 FABTECH => fabtech, --CFG_TECH,
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@@ -63,9 +63,6 ARCHITECTURE beh OF MS_calculation IS
63
63
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65
65
66
67 SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
68
69
66
70 BEGIN
67 BEGIN
71
68
@@ -94,7 +91,6 BEGIN
94 select_op1 <= select_R0(0);
91 select_op1 <= select_R0(0);
95 select_op2 <= select_R0;
92 select_op2 <= select_R0;
96 res_wen <= '1';
93 res_wen <= '1';
97 fifo_in_empty_reg <= "11";
98
94
99 ELSIF clk'EVENT AND clk = '1' THEN
95 ELSIF clk'EVENT AND clk = '1' THEN
100 select_ctrl <= select_ctrl_NOP;
96 select_ctrl <= select_ctrl_NOP;
@@ -103,7 +99,6 BEGIN
103 fifo_in_ren_s <= "11";
99 fifo_in_ren_s <= "11";
104 res_wen <= '1';
100 res_wen <= '1';
105 correlation_done <= '0';
101 correlation_done <= '0';
106 fifo_in_empty_reg <= fifo_in_empty;
107 CASE state IS
102 CASE state IS
108 WHEN IDLE =>
103 WHEN IDLE =>
109 IF correlation_start = '1' THEN
104 IF correlation_start = '1' THEN
@@ -259,4 +254,4 BEGIN
259 END PROCESS;
254 END PROCESS;
260
255
261
256
262 END beh;
257 END beh; No newline at end of file
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@@ -26,20 +26,20 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 tech : INTEGER := inferred;
28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 11;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 32;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 15;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 14;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43
43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45
45
@@ -86,9 +86,6 ARCHITECTURE beh OF lpp_lfr IS
86 SIGNAL sample_f2_val : STD_LOGIC;
86 SIGNAL sample_f2_val : STD_LOGIC;
87 SIGNAL sample_f3_val : STD_LOGIC;
87 SIGNAL sample_f3_val : STD_LOGIC;
88 --
88 --
89 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
91 --
92 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
@@ -599,4 +596,4 BEGIN
599 END GENERATE all_channel_sim;
596 END GENERATE all_channel_sim;
600 -----------------------------------------------------------------------------
597 -----------------------------------------------------------------------------
601
598
602 END beh;
599 END beh; No newline at end of file
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This diff has been collapsed as it changes many lines, (963 lines changed) Show them Hide them
@@ -1,485 +1,478
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
42
42
43 GENERIC (
43 GENERIC (
44 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
45 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
46 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
47 -- nb_word_by_buffer_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
49 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
50 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
51
51
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55
55
56 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59
59
60 --config
60 --config
61 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68
68
69 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
73
73
74 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
77
77
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81
81
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83
83
84
84
85 -- REG DMA
85 -- REG DMA
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89
89
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93
93
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 -- INPUT
95 -- INPUT
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98
98
99 --f0
99 --f0
100 data_f0_in_valid : IN STD_LOGIC;
100 data_f0_in_valid : IN STD_LOGIC;
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
103 --f1
103 --f1
104 data_f1_in_valid : IN STD_LOGIC;
104 data_f1_in_valid : IN STD_LOGIC;
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
107 --f2
107 --f2
108 data_f2_in_valid : IN STD_LOGIC;
108 data_f2_in_valid : IN STD_LOGIC;
109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
111 --f3
111 --f3
112 data_f3_in_valid : IN STD_LOGIC;
112 data_f3_in_valid : IN STD_LOGIC;
113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
115
115
116 ---------------------------------------------------------------------------
116 ---------------------------------------------------------------------------
117 -- DMA --------------------------------------------------------------------
117 -- DMA --------------------------------------------------------------------
118
118
119 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
119 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
120 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
120 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
121 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
121 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
122 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
123 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
123 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
124 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
124 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
125 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
125 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
126 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
126 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
127
127
128 );
128 );
129
129
130 END lpp_waveform;
130 END lpp_waveform;
131
131
132 ARCHITECTURE beh OF lpp_waveform IS
132 ARCHITECTURE beh OF lpp_waveform IS
133 SIGNAL start_snapshot_f0 : STD_LOGIC;
133 SIGNAL start_snapshot_f0 : STD_LOGIC;
134 SIGNAL start_snapshot_f1 : STD_LOGIC;
134 SIGNAL start_snapshot_f1 : STD_LOGIC;
135 SIGNAL start_snapshot_f2 : STD_LOGIC;
135 SIGNAL start_snapshot_f2 : STD_LOGIC;
136
136
137 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141
141
142 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146
146
147 SIGNAL data_f0_out_valid : STD_LOGIC;
147 SIGNAL data_f0_out_valid : STD_LOGIC;
148 SIGNAL data_f1_out_valid : STD_LOGIC;
148 SIGNAL data_f1_out_valid : STD_LOGIC;
149 SIGNAL data_f2_out_valid : STD_LOGIC;
149 SIGNAL data_f2_out_valid : STD_LOGIC;
150 SIGNAL data_f3_out_valid : STD_LOGIC;
150 SIGNAL data_f3_out_valid : STD_LOGIC;
151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
152 --
152 --
153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 --
163 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 --
165 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL run : STD_LOGIC;
166 --
166 --
167 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
171 --
171 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
172 SIGNAL run : STD_LOGIC;
172 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
173 --
173 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
174 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
174 --
175 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
175
176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
176 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
177 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
178 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
179 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
180 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
181 --
181
182
182 --
183 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
183 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
185
186 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
187 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
187
188
188 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
189 --
189
190 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 BEGIN -- beh
191 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
191
192
192 -----------------------------------------------------------------------------
193 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
193
194
194 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
195 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
195 GENERIC MAP (
196
196 delta_vector_size => delta_vector_size,
197 BEGIN -- beh
197 delta_vector_size_f0_2 => delta_vector_size_f0_2
198
198 )
199 -----------------------------------------------------------------------------
199 PORT MAP (
200
200 clk => clk,
201 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
201 rstn => rstn,
202 GENERIC MAP (
202 reg_run => reg_run,
203 delta_vector_size => delta_vector_size,
203 reg_start_date => reg_start_date,
204 delta_vector_size_f0_2 => delta_vector_size_f0_2
204 reg_delta_snapshot => reg_delta_snapshot,
205 )
205 reg_delta_f0 => reg_delta_f0,
206 PORT MAP (
206 reg_delta_f0_2 => reg_delta_f0_2,
207 clk => clk,
207 reg_delta_f1 => reg_delta_f1,
208 rstn => rstn,
208 reg_delta_f2 => reg_delta_f2,
209 reg_run => reg_run,
209 coarse_time => coarse_time(30 DOWNTO 0),
210 reg_start_date => reg_start_date,
210 data_f0_valid => data_f0_in_valid,
211 reg_delta_snapshot => reg_delta_snapshot,
211 data_f2_valid => data_f2_in_valid,
212 reg_delta_f0 => reg_delta_f0,
212 start_snapshot_f0 => start_snapshot_f0,
213 reg_delta_f0_2 => reg_delta_f0_2,
213 start_snapshot_f1 => start_snapshot_f1,
214 reg_delta_f1 => reg_delta_f1,
214 start_snapshot_f2 => start_snapshot_f2,
215 reg_delta_f2 => reg_delta_f2,
215 wfp_on => run);
216 coarse_time => coarse_time(30 DOWNTO 0),
216
217 data_f0_valid => data_f0_in_valid,
217 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
218 data_f2_valid => data_f2_in_valid,
218 GENERIC MAP (
219 start_snapshot_f0 => start_snapshot_f0,
219 data_size => data_size,
220 start_snapshot_f1 => start_snapshot_f1,
220 nb_snapshot_param_size => nb_snapshot_param_size)
221 start_snapshot_f2 => start_snapshot_f2,
221 PORT MAP (
222 wfp_on => run);
222 clk => clk,
223
223 rstn => rstn,
224 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
224 run => run,
225 GENERIC MAP (
225 enable => enable_f0,
226 data_size => data_size,
226 burst_enable => burst_f0,
227 nb_snapshot_param_size => nb_snapshot_param_size)
227 nb_snapshot_param => nb_snapshot_param,
228 PORT MAP (
228 start_snapshot => start_snapshot_f0,
229 clk => clk,
229 data_in => data_f0_in,
230 rstn => rstn,
230 data_in_valid => data_f0_in_valid,
231 run => run,
231 data_out => data_f0_out,
232 enable => enable_f0,
232 data_out_valid => data_f0_out_valid);
233 burst_enable => burst_f0,
233
234 nb_snapshot_param => nb_snapshot_param,
234 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
235 start_snapshot => start_snapshot_f0,
235
236 data_in => data_f0_in,
236 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
237 data_in_valid => data_f0_in_valid,
237 GENERIC MAP (
238 data_out => data_f0_out,
238 data_size => data_size,
239 data_out_valid => data_f0_out_valid);
239 nb_snapshot_param_size => nb_snapshot_param_size+1)
240
240 PORT MAP (
241 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
241 clk => clk,
242
242 rstn => rstn,
243 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
243 run => run,
244 GENERIC MAP (
244 enable => enable_f1,
245 data_size => data_size,
245 burst_enable => burst_f1,
246 nb_snapshot_param_size => nb_snapshot_param_size+1)
246 nb_snapshot_param => nb_snapshot_param_more_one,
247 PORT MAP (
247 start_snapshot => start_snapshot_f1,
248 clk => clk,
248 data_in => data_f1_in,
249 rstn => rstn,
249 data_in_valid => data_f1_in_valid,
250 run => run,
250 data_out => data_f1_out,
251 enable => enable_f1,
251 data_out_valid => data_f1_out_valid);
252 burst_enable => burst_f1,
252
253 nb_snapshot_param => nb_snapshot_param_more_one,
253 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
254 start_snapshot => start_snapshot_f1,
254 GENERIC MAP (
255 data_in => data_f1_in,
255 data_size => data_size,
256 data_in_valid => data_f1_in_valid,
256 nb_snapshot_param_size => nb_snapshot_param_size+1)
257 data_out => data_f1_out,
257 PORT MAP (
258 data_out_valid => data_f1_out_valid);
258 clk => clk,
259
259 rstn => rstn,
260 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
260 run => run,
261 GENERIC MAP (
261 enable => enable_f2,
262 data_size => data_size,
262 burst_enable => burst_f2,
263 nb_snapshot_param_size => nb_snapshot_param_size+1)
263 nb_snapshot_param => nb_snapshot_param_more_one,
264 PORT MAP (
264 start_snapshot => start_snapshot_f2,
265 clk => clk,
265 data_in => data_f2_in,
266 rstn => rstn,
266 data_in_valid => data_f2_in_valid,
267 run => run,
267 data_out => data_f2_out,
268 enable => enable_f2,
268 data_out_valid => data_f2_out_valid);
269 burst_enable => burst_f2,
269
270 nb_snapshot_param => nb_snapshot_param_more_one,
270 lpp_waveform_burst_f3 : lpp_waveform_burst
271 start_snapshot => start_snapshot_f2,
271 GENERIC MAP (
272 data_in => data_f2_in,
272 data_size => data_size)
273 data_in_valid => data_f2_in_valid,
273 PORT MAP (
274 data_out => data_f2_out,
274 clk => clk,
275 data_out_valid => data_f2_out_valid);
275 rstn => rstn,
276
276 run => run,
277 lpp_waveform_burst_f3 : lpp_waveform_burst
277 enable => enable_f3,
278 GENERIC MAP (
278 data_in => data_f3_in,
279 data_size => data_size)
279 data_in_valid => data_f3_in_valid,
280 PORT MAP (
280 data_out => data_f3_out,
281 clk => clk,
281 data_out_valid => data_f3_out_valid);
282 rstn => rstn,
282
283 run => run,
283 -----------------------------------------------------------------------------
284 enable => enable_f3,
284 -- DEBUG -- SNAPSHOT OUT
285 data_in => data_f3_in,
285 --debug_f0_data_valid <= data_f0_out_valid;
286 data_in_valid => data_f3_in_valid,
286 --debug_f0_data <= data_f0_out;
287 data_out => data_f3_out,
287 --debug_f1_data_valid <= data_f1_out_valid;
288 data_out_valid => data_f3_out_valid);
288 --debug_f1_data <= data_f1_out;
289
289 --debug_f2_data_valid <= data_f2_out_valid;
290 -----------------------------------------------------------------------------
290 --debug_f2_data <= data_f2_out;
291 -- DEBUG -- SNAPSHOT OUT
291 --debug_f3_data_valid <= data_f3_out_valid;
292 --debug_f0_data_valid <= data_f0_out_valid;
292 --debug_f3_data <= data_f3_out;
293 --debug_f0_data <= data_f0_out;
293 -----------------------------------------------------------------------------
294 --debug_f1_data_valid <= data_f1_out_valid;
294
295 --debug_f1_data <= data_f1_out;
295 PROCESS (clk, rstn)
296 --debug_f2_data_valid <= data_f2_out_valid;
296 BEGIN -- PROCESS
297 --debug_f2_data <= data_f2_out;
297 IF rstn = '0' THEN -- asynchronous reset (active low)
298 --debug_f3_data_valid <= data_f3_out_valid;
298 time_reg1 <= (OTHERS => '0');
299 --debug_f3_data <= data_f3_out;
299 time_reg2 <= (OTHERS => '0');
300 -----------------------------------------------------------------------------
300 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
301
301 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
302 PROCESS (clk, rstn)
302 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
303 BEGIN -- PROCESS
303 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
304 IF rstn = '0' THEN -- asynchronous reset (active low)
304 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
305 time_reg1 <= (OTHERS => '0');
305 time_reg2 <= time_reg1;
306 time_reg2 <= (OTHERS => '0');
306 END IF;
307 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 END PROCESS;
308 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
308
309 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
310 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
311 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
312 time_reg2 <= time_reg1;
312 PORT MAP (
313 END IF;
313 HCLK => clk,
314 END PROCESS;
314 HRESETn => rstn,
315
315 run => run,
316 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
316 valid_in => valid_in(I),
317 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
317 ack_in => valid_ack(I),
318 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
318 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
319 PORT MAP (
319 valid_out => valid_out(I),
320 HCLK => clk,
320 time_out => time_out(I), -- Todo
321 HRESETn => rstn,
321 error => status_new_err(I));
322 run => run,
322 END GENERATE all_input_valid;
323 valid_in => valid_in(I),
323
324 ack_in => valid_ack(I),
324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
325 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
325 data_f0_out((16*6)-1 DOWNTO 16*5) &
326 valid_out => valid_out(I),
326 data_f0_out((16*3)-1 DOWNTO 16*2) &
327 time_out => time_out(I), -- Todo
327 data_f0_out((16*4)-1 DOWNTO 16*3) &
328 error => status_new_err(I));
328 data_f0_out((16*1)-1 DOWNTO 16*0) &
329 END GENERATE all_input_valid;
329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
330
330
331 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
332 data_f0_out((16*6)-1 DOWNTO 16*5) &
332 data_f1_out((16*6)-1 DOWNTO 16*5) &
333 data_f0_out((16*3)-1 DOWNTO 16*2) &
333 data_f1_out((16*3)-1 DOWNTO 16*2) &
334 data_f0_out((16*4)-1 DOWNTO 16*3) &
334 data_f1_out((16*4)-1 DOWNTO 16*3) &
335 data_f0_out((16*1)-1 DOWNTO 16*0) &
335 data_f1_out((16*1)-1 DOWNTO 16*0) &
336 data_f0_out((16*2)-1 DOWNTO 16*1) ;
336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
337
337
338 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
339 data_f1_out((16*6)-1 DOWNTO 16*5) &
339 data_f2_out((16*6)-1 DOWNTO 16*5) &
340 data_f1_out((16*3)-1 DOWNTO 16*2) &
340 data_f2_out((16*3)-1 DOWNTO 16*2) &
341 data_f1_out((16*4)-1 DOWNTO 16*3) &
341 data_f2_out((16*4)-1 DOWNTO 16*3) &
342 data_f1_out((16*1)-1 DOWNTO 16*0) &
342 data_f2_out((16*1)-1 DOWNTO 16*0) &
343 data_f1_out((16*2)-1 DOWNTO 16*1) ;
343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
344
344
345 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
346 data_f2_out((16*6)-1 DOWNTO 16*5) &
346 data_f3_out((16*6)-1 DOWNTO 16*5) &
347 data_f2_out((16*3)-1 DOWNTO 16*2) &
347 data_f3_out((16*3)-1 DOWNTO 16*2) &
348 data_f2_out((16*4)-1 DOWNTO 16*3) &
348 data_f3_out((16*4)-1 DOWNTO 16*3) &
349 data_f2_out((16*1)-1 DOWNTO 16*0) &
349 data_f3_out((16*1)-1 DOWNTO 16*0) &
350 data_f2_out((16*2)-1 DOWNTO 16*1) ;
350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
351
351
352 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
353 data_f3_out((16*6)-1 DOWNTO 16*5) &
353 data_out(0, I) <= data_f0_out_swap(I);
354 data_f3_out((16*3)-1 DOWNTO 16*2) &
354 data_out(1, I) <= data_f1_out_swap(I);
355 data_f3_out((16*4)-1 DOWNTO 16*3) &
355 data_out(2, I) <= data_f2_out_swap(I);
356 data_f3_out((16*1)-1 DOWNTO 16*0) &
356 data_out(3, I) <= data_f3_out_swap(I);
357 data_f3_out((16*2)-1 DOWNTO 16*1) ;
357 END GENERATE all_bit_of_data_out;
358
358
359 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
359 -----------------------------------------------------------------------------
360 data_out(0, I) <= data_f0_out_swap(I);
360 -- TODO : debug
361 data_out(1, I) <= data_f1_out_swap(I);
361 -----------------------------------------------------------------------------
362 data_out(2, I) <= data_f2_out_swap(I);
362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
363 data_out(3, I) <= data_f3_out_swap(I);
363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
364 END GENERATE all_bit_of_data_out;
364 time_out_2(J, I) <= time_out(J)(I);
365
365 END GENERATE all_sample_of_time_out;
366 -----------------------------------------------------------------------------
366 END GENERATE all_bit_of_time_out;
367 -- TODO : debug
367
368 -----------------------------------------------------------------------------
368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
369 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
369 GENERIC MAP (tech => tech,
370 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
370 nb_data_by_buffer_size => nb_data_by_buffer_size)
371 time_out_2(J, I) <= time_out(J)(I);
371 PORT MAP (
372 END GENERATE all_sample_of_time_out;
372 clk => clk,
373 END GENERATE all_bit_of_time_out;
373 rstn => rstn,
374
374 run => run,
375 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
375 nb_data_by_buffer => nb_data_by_buffer,
376 GENERIC MAP (tech => tech,
376 data_in_valid => valid_out,
377 nb_data_by_buffer_size => nb_data_by_buffer_size)
377 data_in_ack => valid_ack,
378 PORT MAP (
378 data_in => data_out,
379 clk => clk,
379 time_in => time_out_2,
380 rstn => rstn,
380
381 run => run,
381 data_out => wdata,
382 nb_data_by_buffer => nb_data_by_buffer,
382 data_out_wen => data_wen,
383 data_in_valid => valid_out,
383 full_almost => full_almost,
384 data_in_ack => valid_ack,
384 full => full,
385 data_in => data_out,
385
386 time_in => time_out_2,
386 time_out => arbiter_time_out,
387
387 time_out_new => arbiter_time_out_new
388 data_out => wdata,
388
389 data_out_wen => data_wen,
389 );
390 full_almost => full_almost,
390
391 full => full,
391 -----------------------------------------------------------------------------
392
392 -----------------------------------------------------------------------------
393 time_out => arbiter_time_out,
393
394 time_out_new => arbiter_time_out_new
394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
395
395 lpp_fifo_1: lpp_fifo
396 );
396 GENERIC MAP (
397
397 tech => 0,
398 -----------------------------------------------------------------------------
398 Mem_use => use_RAM,
399 -----------------------------------------------------------------------------
399 EMPTY_THRESHOLD_LIMIT => 15,
400
400 FULL_THRESHOLD_LIMIT => 3,
401 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
401 DataSz => 32,
402 lpp_fifo_1: lpp_fifo
402 AddrSz => 7)
403 GENERIC MAP (
403 PORT MAP (
404 tech => 0,
404 clk => clk,
405 Mem_use => use_RAM,
405 rstn => rstn,
406 EMPTY_THRESHOLD_LIMIT => 15,
406 reUse => '0',
407 FULL_THRESHOLD_LIMIT => 3,
407 run => run,
408 DataSz => 32,
408 ren => data_ren(I),
409 AddrSz => 7)
409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
410 PORT MAP (
410 wen => data_wen(I),
411 clk => clk,
411 wdata => wdata,
412 rstn => rstn,
412 empty => empty(I),
413 reUse => '0',
413 full => full(I),
414 run => run,
414 full_almost => OPEN,
415 ren => data_ren(I),
415 empty_threshold => empty_almost(I),
416 rdata => s_rdata_v((I+1)*32-1 downto I*32),
416 full_threshold => full_almost(I) );
417 wen => data_wen(I),
417
418 wdata => wdata,
418 END GENERATE generate_all_fifo;
419 empty => empty(I),
419
420 full => full(I),
420 -----------------------------------------------------------------------------
421 full_almost => OPEN,
421 --
422 empty_threshold => empty_almost(I),
422 -----------------------------------------------------------------------------
423 full_threshold => full_almost(I) );
423
424
424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
425 END GENERATE generate_all_fifo;
425
426
426 PROCESS (clk, rstn)
427 -----------------------------------------------------------------------------
427 BEGIN
428 --
428 IF rstn = '0' THEN
429 -----------------------------------------------------------------------------
429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
430
430 ELSIF clk'event AND clk = '1' THEN
431 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
431 IF run = '0' THEN
432
432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
433 PROCESS (clk, rstn)
433 ELSE
434 BEGIN
434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
435 IF rstn = '0' THEN
435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
436 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
436 END IF;
437 ELSIF clk'event AND clk = '1' THEN
437 END IF;
438 IF run = '0' THEN
438 END IF;
439 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
439 END PROCESS;
440 ELSE
440
441 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
443 END IF;
443
444 END IF;
444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
445 END IF;
445 PORT MAP (
446 END PROCESS;
446 clk => clk,
447
447 rstn => rstn,
448 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
448 run => run,
449 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
449
450
450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
451 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
451
452 PORT MAP (
452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
453 clk => clk,
453 fifo_empty => empty(I),
454 rstn => rstn,
454 fifo_empty_threshold => empty_almost(I),
455 run => run,
455 fifo_ren => data_ren(I),
456
456
457 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
458
458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
459 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
459 dma_fifo_ren => dma_fifo_ren(I),
460 fifo_empty => empty(I),
460 dma_buffer_new => dma_buffer_new(I),
461 fifo_empty_threshold => empty_almost(I),
461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
462 fifo_ren => data_ren(I),
462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
463
463 dma_buffer_full => dma_buffer_full(I),
464 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
464 dma_buffer_full_err => dma_buffer_full_err(I),
465 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
465
466 dma_fifo_ren => dma_fifo_ren(I),
466 status_buffer_ready => status_buffer_ready(I), -- TODO
467 dma_buffer_new => dma_buffer_new(I),
467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
468 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
469 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
469 ready_buffer => ready_buffer(I), -- TODO
470 dma_buffer_full => dma_buffer_full(I),
470 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
471 dma_buffer_full_err => dma_buffer_full_err(I),
471 error_buffer_full => error_buffer_full(I)); -- TODO
472
472
473 status_buffer_ready => status_buffer_ready(I), -- TODO
473 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
474 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
474
475 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
475 END GENERATE all_channel;
476 ready_buffer => ready_buffer(I), -- TODO
476
477 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
477
478 error_buffer_full => error_buffer_full(I)); -- TODO
478 END beh; No newline at end of file
479
480 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
481
482 END GENERATE all_channel;
483
484
485 END beh;
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