HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r611:ec07182522e1

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lib/lpp/dsp/cic/cic_lfr_control_r2.vhd +3 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             ENTITY cic_lfr_control_r2 IS
               PORT (
                 clk                : IN  STD_LOGIC;
                 rstn               : IN  STD_LOGIC;
-                run                : IN  STD_LOGIC;
+            --    run                : IN  STD_LOGIC;
                 --
                 data_in_valid      : IN  STD_LOGIC;
                 data_out_16_valid  : OUT STD_LOGIC;
                 data_out_256_valid : OUT STD_LOGIC;
                 --
                 OPERATION          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
                 );
             END cic_lfr_control_r2;
             ARCHITECTURE beh OF cic_lfr_control_r2 IS
               TYPE STATE_CIC_LFR_TYPE IS (IDLE,
                                           RUN_PROG_I,
                                           RUN_PROG_C16,
                                           RUN_PROG_C256
                                           );
               SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
-              SIGNAL nb_data_receipt : INTEGER := 0;
+              SIGNAL nb_data_receipt : INTEGER RANGE 0 TO 255:= 0;
               SIGNAL current_cmd     : INTEGER := 0;
               SIGNAL current_channel : INTEGER := 0;
               SIGNAL sample_16_odd   : STD_LOGIC;
               SIGNAL sample_256_odd  : STD_LOGIC;
               TYPE     PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
               --OPERATION( 8 DOWNTO  0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
               --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
               --OPERATION(11 DOWNTO  9) <= current_channel
               --OPERATION(14)           <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
               CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
                 (
                 -- DCBA     98765     43210
                 --PROG I------------------
                   "0001" & "00011" & "00000",                     --0
                   "0101" & "00010" & "00001",                     --1
                   "0101" & "00010" & "00001",                     --2
                   "0001" & "00010" & "01011",                     --3
                   "0101" & "00010" & "01001",                     --4
                   "0101" & "00010" & "01001",                     --5
                   "0001" & "00010" & "01011",                     --6
                   "0101" & "00010" & "01001",                     --7
                   "0101" & "00010" & "01001",                     --8
                 --PROG_C16
                   "1001" & "00100" & "10010",                     --9
                   "1001" & "10010" & "10101",                     --10
                   "1001" & "10010" & "10101",                     --11
                   "1010" & "10010" & "10101",                     --12
                   "1001" & "01000" & "10010",                     --13
                   "1001" & "10010" & "11101",                     --14
                   "1001" & "10010" & "11101",                     --15
                   "1010" & "10010" & "11101",                     --16
                 --PROG_C256
                   "1001" & "00100" & "10010",                     --17
                   "1001" & "10110" & "10101",                     --18
                   "1001" & "10110" & "10101",                     --19
                   "1010" & "10110" & "10101",                     --20
                   "1001" & "01000" & "10010",                     --21
                   "1001" & "10110" & "11101",                     --22
                   "1001" & "10110" & "11101",                     --23
                   "1010" & "10110" & "11101",                     --24
                   "1001" & "01100" & "10010",                     --25
                   "1001" & "10110" & "11101",                     --26
                   "1001" & "10110" & "11101",                     --27
                   "1010" & "10110" & "11101"                      --28
                   );
               CONSTANT PROG_START_I    : INTEGER := 0;
               CONSTANT PROG_END_I      : INTEGER := 8;
               CONSTANT PROG_START_C16  : INTEGER := 9;
               CONSTANT PROG_END_C16    : INTEGER := 16;
               CONSTANT PROG_START_C256 : INTEGER := 17;
               CONSTANT PROG_END_C256   : INTEGER := 28;
             BEGIN
               OPERATION(2 DOWNTO 0)   <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));                                   --SEL_SAMPLE
               OPERATION(4 DOWNTO 3)   <= PROG(current_cmd)(1 DOWNTO 0);                                                       --SEL_DATA_A
               OPERATION(6 DOWNTO 5)   <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2);                                                       --ALU_CMD
               OPERATION(7)            <= '0'  WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4);                                                                --CARRY_PUSH
               OPERATION(8)            <= PROG(current_cmd)(5);                                                                --@_init
               OPERATION(9)            <= PROG(current_cmd)(6);                                                                --@_add_1
               OPERATION(10)           <= PROG(current_cmd)(7)  AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256  AND PROG(current_cmd)(9) = '1' ELSE
                                          PROG(current_cmd)(7);                        --@_sel(1..0)
               OPERATION(11)           <= PROG(current_cmd)(8);
               OPERATION(12)           <= PROG(current_cmd)(9) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE
                                          --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
                                          PROG(current_cmd)(9)                    WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
                                          '0'; --@_sel(2)
               OPERATION(13)           <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10);                            --WE
               OPERATION(14)           <= PROG(current_cmd)(12);  -- SEL_DATA_A = data_b_reg
               OPERATION(15)           <= PROG(current_cmd)(13);  -- WRITE_ADDR_sel
               data_out_16_valid       <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE '0';
               data_out_256_valid      <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0);
               --OPERATION(2)          <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
               --                           PROG(current_cmd)(2);
               --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
               --                           PROG(current_cmd)(5 DOWNTO 3);
               --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
               --                           PROG(current_cmd)(8 DOWNTO 6);
               --OPERATION(11 DOWNTO 9)  <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
               --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
               --OPERATION(14)           <= PROG(current_cmd)(11) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
               --                           PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               --OPERATION(15)           <= PROG(current_cmd)(12);
               --data_out_16_valid  <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE '0';
               --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   STATE_CIC_LFR      <= IDLE;
                   nb_data_receipt    <= 0;
                   current_channel    <= 0;
                   current_cmd        <= 0;
                   sample_16_odd      <= '0';
                   sample_256_odd     <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE STATE_CIC_LFR IS
                     WHEN IDLE =>
                       IF data_in_valid = '1' THEN
                         STATE_CIC_LFR   <= RUN_PROG_I;
                         current_cmd     <= PROG_START_I;
                         current_channel <= 0;
                         nb_data_receipt <= nb_data_receipt + 1;
                       END IF;
                     WHEN RUN_PROG_I =>
                       IF current_cmd = PROG_END_I THEN
                         IF nb_data_receipt MOD 16 = 15 THEN
                           STATE_CIC_LFR <= RUN_PROG_C16;
                           current_cmd   <= PROG_START_C16;
                           IF current_channel = 0 THEN
                             sample_16_odd <= NOT sample_16_odd;
                           END IF;
                         ELSE
                           IF current_channel = 7 THEN
                             current_channel <= 0;
                             STATE_CIC_LFR   <= IDLE;
                           ELSE
                             current_cmd     <= PROG_START_I;
                             current_channel <= current_channel + 1;
                           END IF;
                         END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN RUN_PROG_C16 =>
                       IF current_cmd = PROG_END_C16 THEN
                         IF nb_data_receipt MOD 256 = 255 AND current_channel < 6 THEN
                           STATE_CIC_LFR <= RUN_PROG_C256;
                           current_cmd   <= PROG_START_C256;
                           IF current_channel = 0 THEN
                             sample_256_odd <= NOT sample_256_odd;
                           END IF;
                         ELSE
                           IF current_channel = 7 THEN
                             current_channel <= 0;
                             STATE_CIC_LFR   <= IDLE;
                           ELSE
                             STATE_CIC_LFR   <= RUN_PROG_I;
                             current_cmd     <= PROG_START_I;
                             current_channel <= current_channel + 1;
                           END IF;
                         END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN RUN_PROG_C256 =>
                       IF current_cmd = PROG_END_C256 THEN
             --          data_out_256_valid  <= '1';
             --            IF current_channel = 5 THEN
             --              current_channel <= 0;
             --              STATE_CIC_LFR   <= IDLE;
             --            ELSE
                         STATE_CIC_LFR   <= RUN_PROG_I;
                         current_cmd     <= PROG_START_I;
                         current_channel <= current_channel + 1;
             --            END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/dsp/cic/cic_lfr_r2.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.all;
             LIBRARY lpp;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.iir_filter.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY cic_lfr_r2 IS
               GENERIC(
                 tech         : INTEGER := 0;
                 use_RAM_nCEL : INTEGER := 0         -- 1 => RAM(tech) , 0 => RAM_CEL
                 );
               PORT (
                 clk            : IN  STD_LOGIC;
                 rstn           : IN  STD_LOGIC;
                 run            : IN  STD_LOGIC;
                 param_r2       : IN  STD_LOGIC;
                 data_in        : IN  sample_vector(7 DOWNTO 0,15 DOWNTO 0);
                 data_in_valid  : IN  STD_LOGIC;
                 data_out_16        : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_16_valid  : OUT STD_LOGIC;
                 data_out_256       : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_256_valid : OUT STD_LOGIC
                 );
             END cic_lfr_r2;
             ARCHITECTURE beh OF cic_lfr_r2 IS
               --
               SIGNAL sel_sample  : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
               SIGNAL sample      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL sel_A  : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
               SIGNAL data_A  : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_B      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_B_reg      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_out      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_in_Carry  : STD_LOGIC;
               SIGNAL data_out_Carry : STD_LOGIC;
               --
               CONSTANT S_parameter : INTEGER := 3;
               SIGNAL carry_reg  : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
               --
               SIGNAL OPERATION    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL   base_addr_INT   : ARRAY_OF_ADDR;
               CONSTANT base_addr_delta : INTEGER := 40;
               SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL data_we: STD_LOGIC;
               SIGNAL data_we_s: STD_LOGIC;
               SIGNAL data_wen       : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16   : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_out_reg256  : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0);
               SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
               SIGNAL  data_out_16_valid_s  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s : STD_LOGIC;
               SIGNAL  data_out_16_valid_s1  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s1 : STD_LOGIC;
               SIGNAL  data_out_16_valid_s2  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s2 : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16_s   : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
               SIGNAL sample_out_reg256_s  : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
               -----------------------------------------------------------------------------
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_B_reg <=  (OTHERS => '0');
                   OPERATION_reg <= (OTHERS => '0');
                   OPERATION_reg2 <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   OPERATION_reg <= OPERATION;
                   OPERATION_reg2 <= OPERATION_reg;
                   data_B_reg <= data_B;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SEL_SAMPLE
               -----------------------------------------------------------------------------
               sel_sample <= OPERATION_reg(2 DOWNTO 0);
               all_bit: FOR I IN 15 DOWNTO 0 GENERATE
                 sample_temp(0,I) <= data_in(0,I)     WHEN sel_sample(0) = '0' ELSE data_in(1,I);
                 sample_temp(1,I) <= data_in(2,I)     WHEN sel_sample(0) = '0' ELSE data_in(3,I);
                 sample_temp(2,I) <= data_in(4,I)     WHEN sel_sample(0) = '0' ELSE data_in(5,I);
                 sample_temp(3,I) <= data_in(6,I)     WHEN sel_sample(0) = '0' ELSE data_in(7,I);
                 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
                 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
                 sample(I)        <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
               END GENERATE all_bit;
               -----------------------------------------------------------------------------
               -- SEL_DATA_IN_A
               -----------------------------------------------------------------------------
               sel_A <= OPERATION_reg(4 DOWNTO 3);
               all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
                 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
                 data_A_temp(1,I) <= '0'       WHEN sel_A(0) = '0' ELSE sample(15);
                 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
                 data_A(I)        <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
               END GENERATE all_data_mux_A;
               -----------------------------------------------------------------------------
               -- ALU
               -----------------------------------------------------------------------------
               ALU_OP <= OPERATION_reg(6 DOWNTO 5);
               ALU: cic_lfr_add_sub
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   run            => run,
                   OP             => ALU_OP,
                   data_in_A      => data_A,
                   data_in_B      => data_B,
                   data_in_Carry  => data_in_Carry,
                   data_out       => data_out,
                   data_out_Carry => data_out_Carry);
               -----------------------------------------------------------------------------
               -- CARRY_MANAGER
               -----------------------------------------------------------------------------
               data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
             --  CARRY_PUSH <= OPERATION_reg(7);
             --  CARRY_POP  <= OPERATION_reg(6);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   carry_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
                     carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
                     carry_reg(0)                      <= data_out_Carry;
                   --END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- MEMORY
               -----------------------------------------------------------------------------
               all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE
                 all_channel: FOR I IN 7 DOWNTO 0 GENERATE
                   base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
                 END GENERATE all_channel;
               END GENERATE all_bit_base_ADDR;
               addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
               cic_lfr_address_gen_1: cic_lfr_address_gen
                 GENERIC MAP (
                   ADDR_SIZE => 9)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   addr_base         => addr_base_sel,
                   addr_init         => OPERATION(8),
                   addr_add_1        => OPERATION(9),
                   addr              => addr_gen);
               addr_read <= addr_gen                                                               WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+15,9));
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   addr_write   <= (OTHERS => '0');
                   data_we      <= '0';
                   addr_write_s <= (OTHERS => '0');
                   data_we_s    <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   addr_write_s <= addr_read;
                   data_we_s    <= OPERATION(13);
                   IF OPERATION_reg(15) = '0' THEN
                     addr_write   <= addr_write_s;
                   ELSE
                     addr_write <= addr_read;
                   END IF;
                   data_we      <= data_we_s;
                 END IF;
               END PROCESS;
               memCEL : IF use_RAM_nCEL = 0 GENERATE
                 data_wen <= NOT data_we;
                 RAMblk : RAM_CEL
                   GENERIC MAP(16, 9)
                   PORT MAP(
                     WD    => data_out,
                     RD    => data_B,
                     WEN   => data_wen,
                     REN   => '0',
                     WADDR => addr_write,
                     RADDR => addr_read,
                     RWCLK => clk,
                     RESET => rstn
                     ) ;
               END GENERATE;
               memRAM : IF use_RAM_nCEL = 1 GENERATE
                 SRAM : syncram_2p
                   GENERIC MAP(tech, 9, 16)
                   PORT MAP(clk, '1', addr_read,  data_B,
                            clk, data_we, addr_write, data_out);
               END GENERATE;
               -----------------------------------------------------------------------------
               -- CONTROL
               -----------------------------------------------------------------------------
               cic_lfr_control_1: cic_lfr_control_r2
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
-                  run                => run,
+            --      run                => run,
                   data_in_valid      => data_in_valid,
                   data_out_16_valid  => data_out_16_valid_s,
                   data_out_256_valid => data_out_256_valid_s,
                   OPERATION          => OPERATION);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_out_16_valid_s1 <= '0';
                   data_out_256_valid_s1 <= '0';
                   data_out_16_valid_s2 <= '0';
                   data_out_256_valid_s2 <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   data_out_16_valid_s1 <= data_out_16_valid_s;
                   data_out_256_valid_s1 <= data_out_256_valid_s;
                   data_out_16_valid_s2  <= data_out_16_valid_s1;
                   data_out_256_valid_s2 <= data_out_256_valid_s1;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_valid_reg16  <= "00000" & "000000" & "000001";
                   sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '0' THEN
                     sample_valid_reg16  <= "00000" & "000000" & "000001";
                     sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                   ELSE
                     IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN
                       sample_valid_reg16  <= sample_valid_reg16(8*2-1 DOWNTO 0)  & sample_valid_reg16(8*2);
                     END IF;
                     IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
                       sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               data_out_16_valid  <= sample_valid_reg16(8*2);
               data_out_256_valid <= sample_valid_reg256(6*3);
               -----------------------------------------------------------------------------
               all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                 all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg16(I,J)  <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg16(I,J)  <= '0';
                       ELSE
                         IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
                           sample_out_reg16(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out16;
                 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg256(I,J) <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg256(I,J) <= '0';
                       ELSE
                         IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
                           sample_out_reg256(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out256;
               END GENERATE all_bits;
               all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE
                 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
                   sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J);
                   sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE  sample_out_reg16(2*6+K,J);
                   sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE  sample_out_reg16(2*7+K,J);
                   sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J);
                   sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J);
                   sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J);
                 END GENERATE all_reg_16;
               END GENERATE all_bits_16;
               all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE
                   all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
                     sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
                   END GENERATE all_reg_256;
                 END GENERATE all_bits_256;
               END GENERATE all_channel_out_256;
               all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                   data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
                   data_out_16(I,J)  <= sample_out_reg16_s (I,J+16  -16+15);
                 END GENERATE all_bits;
               END GENERATE all_channel_out_v;
-            END beh;
  No newline at end of file
+            END beh;

lib/lpp/dsp/cic/cic_pkg.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.data_type_pkg.ALL;
             PACKAGE cic_pkg IS
               -----------------------------------------------------------------------------
               COMPONENT cic
                 GENERIC (
                   D_delay_number                   : INTEGER;
                   S_stage_number                   : INTEGER;
                   R_downsampling_decimation_factor : INTEGER;
                   b_data_size                      : INTEGER;
                   b_grow                           : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT cic_integrator
                 GENERIC (
                   b_data_size : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT cic_downsampler
                 GENERIC (
                   R_downsampling_decimation_factor : INTEGER;
                   b_data_size                      : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT cic_comb
                 GENERIC (
                   b_data_size    : INTEGER;
                   D_delay_number : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               COMPONENT cic_lfr
                 GENERIC (
                   tech         : INTEGER;
                   use_RAM_nCEL : INTEGER);
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   run                : IN  STD_LOGIC;
                   data_in            : IN  sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
                   data_in_valid      : IN  STD_LOGIC;
                   data_out_16        : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
                   data_out_16_valid  : OUT STD_LOGIC;
                   data_out_256       : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
                   data_out_256_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT cic_lfr_r2
                 GENERIC (
                   tech         : INTEGER;
                   use_RAM_nCEL : INTEGER);
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   run                : IN  STD_LOGIC;
                   param_r2           : IN  STD_LOGIC;
                   data_in            : IN  sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
                   data_in_valid      : IN  STD_LOGIC;
                   data_out_16        : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
                   data_out_16_valid  : OUT STD_LOGIC;
                   data_out_256       : OUT sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
                   data_out_256_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT cic_lfr_control
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   run                : IN  STD_LOGIC;
                   data_in_valid      : IN  STD_LOGIC;
                   data_out_16_valid  : OUT STD_LOGIC;
                   data_out_256_valid : OUT STD_LOGIC;
                   OPERATION          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
               END COMPONENT;
               COMPONENT cic_lfr_control_r2
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
-                  run                : IN  STD_LOGIC;
+            --      run                : IN  STD_LOGIC;
                   data_in_valid      : IN  STD_LOGIC;
                   data_out_16_valid  : OUT STD_LOGIC;
                   data_out_256_valid : OUT STD_LOGIC;
                   OPERATION          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
               END COMPONENT;
               COMPONENT cic_lfr_add_sub
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   OP             : IN  STD_LOGIC_VECTOR( 1 DOWNTO 0);
                   data_in_A      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_in_B      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_in_Carry  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_out_Carry : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT cic_lfr_address_gen
                 GENERIC (
                   ADDR_SIZE : INTEGER);
                 PORT (
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   run        : IN  STD_LOGIC;
                   addr_base  : IN  STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0);
                   addr_init  : IN  STD_LOGIC;
                   addr_add_1 : IN  STD_LOGIC;
                   addr       : OUT STD_LOGIC_VECTOR(ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
             END cic_pkg;

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more Cdetails.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
               GENERIC (
                 Coef_sel_SZ  : INTEGER;
                 Cels_count   : INTEGER := 5;
                 ChanelsCount : INTEGER := 1);
               PORT (
                 rstn : IN STD_LOGIC;
                 clk  : IN STD_LOGIC;
                 sample_in_val  : IN  STD_LOGIC;
                 sample_in_rot  : OUT STD_LOGIC;
                 sample_out_val : OUT STD_LOGIC;
                 sample_out_rot : OUT STD_LOGIC;
                 in_sel_src     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ram_sel_Wdata  : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ram_write      : OUT STD_LOGIC;
                 ram_read       : OUT STD_LOGIC;
                 raddr_rst      : OUT STD_LOGIC;
                 raddr_add1     : OUT STD_LOGIC;
                 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 alu_sel_input  : OUT STD_LOGIC;
                 alu_sel_coeff  : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
                 alu_ctrl       : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END IIR_CEL_CTRLR_v2_CONTROL;
             ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS
               TYPE fsmIIR_CEL_T IS (waiting,
                                     first_read,
                                     compute_b0,
                                     compute_b1,
                                     compute_b2,
                                     compute_a1,
                                     compute_a2,
                                     LAST_CEL,
                                     wait_valid_last_output,
                                     wait_valid_last_output_2);
               SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T;
-              SIGNAL alu_selected_coeff : INTEGER;
+              SIGNAL alu_selected_coeff : INTEGER RANGE 0 TO 2**Coef_sel_SZ-1;
               SIGNAL Chanel_ongoing     : INTEGER;
               SIGNAL Cel_ongoing        : INTEGER;
             BEGIN
               alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ));
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   --REG -------------------------------------------------------------------
                   in_sel_src         <= (OTHERS => '0');  --
                   --RAM_WRitE -------------------------------------------------------------
                   ram_sel_Wdata      <= "00";       --
                   ram_write          <= '0';        --
                   waddr_previous     <= "00";       --
                   --RAM_READ --------------------------------------------------------------
                   ram_read           <= '0';        --
                   raddr_rst          <= '0';        --
                   raddr_add1         <= '0';        --
                   --ALU -------------------------------------------------------------------
                   alu_selected_coeff <= 0;          --
                   alu_sel_input      <= '0';        --
                   alu_ctrl           <= ctrl_IDLE;  --
                   --OUT
                   sample_out_val     <= '0';        --
                   sample_out_rot     <= '0';        --
                   Chanel_ongoing <= 0;              --
                   Cel_ongoing    <= 0;              --
                   sample_in_rot  <= '0';
                   IIR_CEL_STATE <= waiting;
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   CASE IIR_CEL_STATE IS
                     WHEN waiting =>
                       sample_out_rot     <= '0';
                       sample_in_rot      <= '0';
                       sample_out_val     <= '0';
                       alu_ctrl           <= ctrl_CLRMAC;
                       alu_selected_coeff <= 0;
                       in_sel_src         <= "01";
                       ram_read           <= '0';
                       ram_sel_Wdata      <= "00";
                       ram_write          <= '0';
                       waddr_previous     <= "00";
                       IF sample_in_val = '1' THEN
                         raddr_rst      <= '0';
                         alu_sel_input  <= '1';
                         ram_read       <= '1';
                         raddr_add1     <= '1';
                         IIR_CEL_STATE  <= first_read;
                         Chanel_ongoing <= Chanel_ongoing + 1;
                         Cel_ongoing    <= 1;
                       ELSE
                         raddr_add1     <= '0';
                         raddr_rst      <= '1';
                         Chanel_ongoing <= 0;
                         Cel_ongoing    <= 0;
                       END IF;
                     WHEN first_read =>
                       IIR_CEL_STATE <= compute_b2;
                       ram_read      <= '1';
                       raddr_add1    <= '1';
                       alu_ctrl      <= ctrl_MULT;
                       alu_sel_input <= '1';
                       in_sel_src    <= "01";
                     WHEN compute_b2 =>
                       sample_out_rot <= '0';
                       sample_in_rot  <= '0';
                       sample_out_val <= '0';
                       alu_sel_input  <= '1';
                       --
                       ram_sel_Wdata  <= "10";
                       ram_write      <= '1';
                       waddr_previous <= "10";
                       --
                       ram_read       <= '1';
                       raddr_rst      <= '0';
                       raddr_add1     <= '0';
                       IF Cel_ongoing = 1 THEN
                         in_sel_src <= "00";
                       ELSE
                         in_sel_src <= "11";
                       END IF;
                       alu_selected_coeff <= alu_selected_coeff+1;
                       alu_ctrl           <= ctrl_MAC;
                       IIR_CEL_STATE      <= compute_b1;
                     WHEN compute_b1 =>
                       sample_in_rot  <= '0';
                       alu_sel_input  <= '0';
                       --
                       ram_sel_Wdata  <= "00";
                       ram_write      <= '1';
                       waddr_previous <= "01";
                       --
                       ram_read       <= '1';
                       raddr_rst      <= '0';
                       raddr_add1     <= '1';
                       sample_out_rot <= '0';
                       IF Cel_ongoing = 1 THEN
                         in_sel_src     <= "10";
                         sample_out_val <= '0';
                       ELSE
                         sample_out_val <= '0';
                         in_sel_src     <= "00";
                       END IF;
                       alu_selected_coeff <= alu_selected_coeff+1;
                       alu_ctrl           <= ctrl_MAC;
                       IIR_CEL_STATE      <= compute_b0;
                     WHEN compute_b0 =>
                       sample_out_rot     <= '0';
                       sample_out_val     <= '0';
                       sample_in_rot      <= '0';
                       alu_sel_input      <= '1';
                       ram_sel_Wdata      <= "00";
                       ram_write          <= '0';
                       waddr_previous     <= "01";
                       ram_read           <= '1';
                       raddr_rst          <= '0';
                       raddr_add1         <= '0';
                       in_sel_src         <= "10";
                       alu_selected_coeff <= alu_selected_coeff+1;
                       alu_ctrl           <= ctrl_MAC;
                       IIR_CEL_STATE      <= compute_a2;
                       IF Cel_ongoing = Cels_count THEN
                         sample_in_rot <= '1';
                       ELSE
                         sample_in_rot <= '0';
                       END IF;
                     WHEN compute_a2 =>
                       sample_out_val <= '0';
                       sample_out_rot <= '0';
                       alu_sel_input  <= '1';
                       ram_sel_Wdata  <= "00";
                       ram_write      <= '0';
                       waddr_previous <= "01";
                       ram_read       <= '1';
                       raddr_rst      <= '0';
                       IF Cel_ongoing = Cels_count THEN
                         raddr_add1 <= '1';
                       ELSE
                         raddr_add1 <= '0';
                       END IF;
                       in_sel_src         <= "00";
                       alu_selected_coeff <= alu_selected_coeff+1;
                       alu_ctrl           <= ctrl_MAC;
                       IIR_CEL_STATE      <= compute_a1;
                       sample_in_rot      <= '0';
                     WHEN compute_a1 =>
                       sample_out_val <= '0';
                       sample_out_rot <= '0';
                       alu_sel_input  <= '0';
                       ram_sel_Wdata  <= "00";
                       ram_write      <= '0';
                       waddr_previous <= "01";
                       ram_read       <= '1';
                       raddr_rst      <= '0';
                       alu_ctrl       <= ctrl_MULT;
                       sample_in_rot  <= '0';
                       IF Cel_ongoing = Cels_count THEN
                         alu_selected_coeff <= 0;
                         ram_sel_Wdata  <= "10";
                         raddr_add1     <= '1';
                         ram_write      <= '1';
                         waddr_previous <= "10";
                         IF Chanel_ongoing = ChanelsCount THEN
                           IIR_CEL_STATE <= wait_valid_last_output;
                         ELSE
                           Chanel_ongoing <= Chanel_ongoing + 1;
                           Cel_ongoing    <= 1;
                           IIR_CEL_STATE  <= LAST_CEL;
                           in_sel_src     <= "01";
                         END IF;
                       ELSE
                         raddr_add1         <= '1';
                         alu_selected_coeff <= alu_selected_coeff+1;
                         Cel_ongoing        <= Cel_ongoing+1;
                         IIR_CEL_STATE      <= compute_b2;
                       END IF;
                     WHEN LAST_CEL =>
                       alu_sel_input  <= '1';
                       IIR_CEL_STATE  <= compute_b2;
                       raddr_add1     <= '1';
                       ram_sel_Wdata  <= "01";
                       ram_write      <= '1';
                       waddr_previous <= "10";
                       sample_out_rot <= '1';
                     WHEN wait_valid_last_output =>
                       IIR_CEL_STATE      <= wait_valid_last_output_2;
                       sample_in_rot      <= '0';
                       alu_ctrl           <= ctrl_IDLE;
                       alu_selected_coeff <= 0;
                       in_sel_src         <= "01";
                       ram_read           <= '0';
                       raddr_rst          <= '1';
                       raddr_add1         <= '1';
                       ram_sel_Wdata      <= "01";
                       ram_write          <= '1';
                       waddr_previous     <= "10";
                       Chanel_ongoing     <= 0;
                       Cel_ongoing        <= 0;
                       sample_out_val     <= '0';
                       sample_out_rot     <= '1';
                     WHEN wait_valid_last_output_2 =>
                       IIR_CEL_STATE      <= waiting;
                       sample_in_rot      <= '0';
                       alu_ctrl           <= ctrl_IDLE;
                       alu_selected_coeff <= 0;
                       in_sel_src         <= "01";
                       ram_read           <= '0';
                       raddr_rst          <= '1';
                       raddr_add1         <= '1';
                       ram_sel_Wdata      <= "10";
                       ram_write          <= '1';
                       waddr_previous     <= "10";
                       Chanel_ongoing     <= 0;
                       Cel_ongoing        <= 0;
                       sample_out_val     <= '1';
                       sample_out_rot     <= '0';
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
             END ar_IIR_CEL_CTRLR_v2_CONTROL;

lib/lpp/dsp/lpp_downsampling/Downsampling.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author :  Jean-christophe PELLION
             --                     Mail :   jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.std_logic_arith.ALL;
             LIBRARY lpp;
             use lpp.iir_filter.all;
             ENTITY Downsampling IS
               GENERIC (
                 ChanelCount : INTEGER;
                 SampleSize  : INTEGER;
                 DivideParam : INTEGER );
               PORT (
                 clk            : IN  STD_LOGIC;
                 rstn           : IN  STD_LOGIC;
                 sample_in_val  : IN  STD_LOGIC;
                 sample_in      : IN  samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
                 sample_out_val : OUT STD_LOGIC;
                 sample_out     : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)
                 );
             END Downsampling;
             ARCHITECTURE beh OF Downsampling IS
-              SIGNAL counter : INTEGER;
+              SIGNAL counter : INTEGER RANGE 0 TO DivideParam-1;
             BEGIN  -- beh
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   counter        <= 0;
                   sample_out_val <= '0';
                   all_sampl: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
                   	all_bit: FOR J IN SampleSize-1 DOWNTO 0 LOOP
             	        sample_out(I,J)     <= '0';
                     END LOOP all_bit;
                   END LOOP all_sampl;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF sample_in_val = '1' THEN
                     IF counter = 0 THEN
                       counter        <= DivideParam-1;
                       sample_out_val <= '1';
                       sample_out     <= sample_in;
                     ELSE
                       counter        <= counter-1;
                       sample_out_val <= '0';
                     END IF;
                   ELSE
                     sample_out_val <= '0';
                   END IF;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lfr_management/apb_lfr_management.vhd +2 -1

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:17:05 07/02/2012
             -- Design Name:
             -- Module Name:    apb_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
             USE lpp.lpp_cna.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY apb_lfr_management IS
               GENERIC(
                 tech             : INTEGER := 0;
                 pindex           : INTEGER := 0;        --! APB slave index
                 paddr            : INTEGER := 0;        --! ADDR field of the APB BAR
                 pmask            : INTEGER := 16#fff#;  --! MASK field of the APB BAR
             --    FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60
                 );
               PORT (
                 clk25MHz         : IN STD_LOGIC;    --! Clock
                 resetn_25MHz     : IN STD_LOGIC;    --! Reset
             --    clk24_576MHz     : IN STD_LOGIC;    --! secondary clock
             --    resetn_24_576MHz : IN STD_LOGIC;    --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                 apbi          : IN  apb_slv_in_type;   --! APB slave input signals
                 apbo          : OUT apb_slv_out_type;  --! APB slave output signals
                 ---------------------------------------------------------------------------
                 HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_val        : IN  STD_LOGIC;
                 HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 DAC_SDO       : OUT STD_LOGIC;
                 DAC_SCK       : OUT STD_LOGIC;
                 DAC_SYNC      : OUT STD_LOGIC;
                 DAC_CAL_EN    : OUT STD_LOGIC;
                 ---------------------------------------------------------------------------
                 coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                 fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);  --! fine TIME
                 ---------------------------------------------------------------------------
                 LFR_soft_rstn : OUT STD_LOGIC
                 );
             END apb_lfr_management;
             ARCHITECTURE Behavioral OF apb_lfr_management IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
 => apb_iobar(paddr, pmask)
                 );
               TYPE apb_lfr_time_management_Reg IS RECORD
                 ctrl             : STD_LOGIC;
                 soft_reset       : STD_LOGIC;
                 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
                 coarse_time      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 LFR_soft_reset   : STD_LOGIC;
                 HK_temp_0        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_1        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 HK_temp_2        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END RECORD;
               SIGNAL r : apb_lfr_time_management_Reg;
               SIGNAL Rdata               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL force_tick          : STD_LOGIC;
               SIGNAL previous_force_tick : STD_LOGIC;
               SIGNAL soft_tick           : STD_LOGIC;
               SIGNAL coarsetime_reg_updated : STD_LOGIC;
               SIGNAL coarsetime_reg         : STD_LOGIC_VECTOR(30 DOWNTO 0);
               --SIGNAL coarse_time_new    : STD_LOGIC;
               SIGNAL coarse_time_new_49 : STD_LOGIC;
               SIGNAL coarse_time_49     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL coarse_time_s      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL fine_time_new      : STD_LOGIC;
               --SIGNAL fine_time_new_temp : STD_LOGIC;
               SIGNAL fine_time_new_49 : STD_LOGIC;
               SIGNAL fine_time_49     : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fine_time_s      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL tick             : STD_LOGIC;
               SIGNAL new_timecode     : STD_LOGIC;
               SIGNAL new_coarsetime   : STD_LOGIC;
               SIGNAL time_new_49 : STD_LOGIC;
               SIGNAL time_new    : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL force_reset          : STD_LOGIC;
               SIGNAL previous_force_reset : STD_LOGIC;
               SIGNAL soft_reset           : STD_LOGIC;
-              SIGNAL soft_reset_sync      : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL HK_sel_s             : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL previous_fine_time_bit : STD_LOGIC;
               SIGNAL rstn_LFR_TM : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- DAC
               -----------------------------------------------------------------------------
               CONSTANT PRESZ         : INTEGER := 8;
               CONSTANT CPTSZ         : INTEGER := 16;
               CONSTANT datawidth     : INTEGER := 18;
               CONSTANT dacresolution : INTEGER := 12;
               CONSTANT abits         : INTEGER := 8;
               SIGNAL pre           : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
               SIGNAL N             : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
               SIGNAL Reload        : STD_LOGIC;
               SIGNAL DATA_IN       : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
               SIGNAL WEN           : STD_LOGIC;
               SIGNAL LOAD_ADDRESSN : STD_LOGIC;
               SIGNAL ADDRESS_IN    : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
               SIGNAL ADDRESS_OUT   : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
               SIGNAL INTERLEAVED   : STD_LOGIC;
               SIGNAL DAC_CFG       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL DAC_CAL_EN_s  : STD_LOGIC;
             BEGIN
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
               PROCESS(resetn_25MHz, clk25MHz)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN
                 IF resetn_25MHz = '0' THEN
                   Rdata              <= (OTHERS => '0');
                   r.coarse_time_load <= (OTHERS => '0');
                   r.soft_reset       <= '0';
                   r.ctrl             <= '0';
                   r.LFR_soft_reset   <= '1';
                   force_tick          <= '0';
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
                   coarsetime_reg_updated <= '0';
                   --DAC
                   pre                    <= (OTHERS => '1');
                   N                      <= (OTHERS => '1');
                   Reload                 <= '1';
                   DATA_IN                <= (OTHERS => '0');
                   WEN                    <= '1';
                   LOAD_ADDRESSN          <= '1';
                   ADDRESS_IN             <= (OTHERS => '1');
                   INTERLEAVED            <= '0';
                   DAC_CFG                <= (OTHERS => '0');
                   --
                   DAC_CAL_EN_s           <= '0';
                   force_reset            <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
                   coarsetime_reg_updated <= '0';
                   force_tick          <= r.ctrl;
                   previous_force_tick <= force_tick;
                   IF (previous_force_tick = '0') AND (force_tick = '1') THEN
                     soft_tick <= '1';
                   ELSE
                     soft_tick <= '0';
                   END IF;
                   force_reset          <= r.soft_reset;
                   previous_force_reset <= force_reset;
                   IF (previous_force_reset = '0') AND (force_reset = '1') THEN
                     soft_reset <= '1';
                   ELSE
                     soft_reset <= '0';
                   END IF;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   Rdata             <= (OTHERS => '0');
                   LOAD_ADDRESSN <= '1';
                   WEN           <= '1';
                   IF apbi.psel(pindex) = '1' THEN
                     --APB READ OP
                     CASE paddr(7 DOWNTO 2) IS
                       WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                         Rdata(0)           <= r.ctrl;
                         Rdata(1)           <= r.soft_reset;
                         Rdata(2)           <= r.LFR_soft_reset;
                         Rdata(31 DOWNTO 3) <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                         Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
                         Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.fine_time(15 DOWNTO 0);
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_0;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_1;
                       WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.HK_temp_2;
                       WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
                         Rdata(3 DOWNTO 0)  <= DAC_CFG;
                         Rdata(4)           <= Reload;
                         Rdata(5)           <= INTERLEAVED;
                         Rdata(6)           <= DAC_CAL_EN_s;
                         Rdata(31 DOWNTO 7) <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
                         Rdata(PRESZ-1 DOWNTO 0) <= pre;
                         Rdata(31 DOWNTO PRESZ)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_N =>
                         Rdata(CPTSZ-1 DOWNTO 0) <= N;
                         Rdata(31 DOWNTO CPTSZ)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
                         Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
                         Rdata(31 DOWNTO abits)  <= (OTHERS => '0');
                       WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
                         Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
                         Rdata(31 DOWNTO datawidth)  <= (OTHERS => '0');
                       WHEN OTHERS =>
                         Rdata(31 DOWNTO 0) <= (OTHERS => '0');
                     END CASE;
                     --APB Write OP
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       CASE paddr(7 DOWNTO 2) IS
                         WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                           r.ctrl           <= apbi.pwdata(0);
                           r.soft_reset     <= apbi.pwdata(1);
                           r.LFR_soft_reset <= apbi.pwdata(2);
                         WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                           r.coarse_time_load     <= apbi.pwdata(30 DOWNTO 0);
                           coarsetime_reg_updated <= '1';
                         WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
                           DAC_CFG      <= apbi.pwdata(3 DOWNTO 0);
                           Reload       <= apbi.pwdata(4);
                           INTERLEAVED  <= apbi.pwdata(5);
                           DAC_CAL_EN_s <= apbi.pwdata(6);
                         WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
                           pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
                         WHEN ADDR_LFR_MANAGMENT_DAC_N =>
                           N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
                         WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
                           ADDRESS_IN    <= apbi.pwdata(abits-1 DOWNTO 0);
                           LOAD_ADDRESSN <= '0';
                         WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
                           DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
                           WEN     <= '0';
                         WHEN OTHERS =>
                           NULL;
                       END CASE;
                     ELSE
                       IF r.ctrl = '1' THEN
                         r.ctrl <= '0';
                       END IF;
                       IF r.soft_reset = '1' THEN
                         r.soft_reset <= '0';
                       END IF;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               apbo.pirq    <= (OTHERS => '0');
               apbo.prdata  <= Rdata;
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
               -----------------------------------------------------------------------------
               -- IN
               coarse_time    <= r.coarse_time;
               fine_time      <= r.fine_time;
               coarsetime_reg <= r.coarse_time_load;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- OUT
               r.coarse_time <= coarse_time_s;
               r.fine_time   <= fine_time_s;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               tick <= grspw_tick OR soft_tick;
               --SYNC_VALID_BIT_1 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk25MHz,
               --    rstn_in    => resetn_25MHz,
               --    clk_out => clk24_576MHz,
               --    rstn_out => resetn_24_576MHz,
               --    sin     => tick,
               --    sout    => new_timecode);
               new_timecode <= tick;
               --SYNC_VALID_BIT_2 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk25MHz,
               --    rstn_in    => resetn_25MHz,
               --    clk_out => clk24_576MHz,
               --    rstn_out => resetn_24_576MHz,
               --    sin     => coarsetime_reg_updated,
               --    sout    => new_coarsetime);
               new_coarsetime <= coarsetime_reg_updated;
               --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk25MHz,
               --    rstn_in    => resetn_25MHz,
               --    clk_out => clk24_576MHz,
               --    rstn_out => resetn_24_576MHz,
               --    sin     => soft_reset,
               --    sout    => soft_reset_sync);
               -----------------------------------------------------------------------------
               time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
               --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk24_576MHz,
               --    rstn_in    => resetn_24_576MHz,
               --    clk_out => clk25MHz,
               --    rstn_out => resetn_25MHz,
               --    sin     => time_new_49,
               --    sout    => time_new);
               time_new <= time_new_49;
               --PROCESS (clk25MHz, resetn_25MHz)
               --BEGIN  -- PROCESS
               --  IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
               --    fine_time_s   <= (OTHERS => '0');
               --    coarse_time_s <= (OTHERS => '0');
               --  ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
               --    IF time_new = '1' THEN
               --    END IF;
               --  END IF;
               --END PROCESS;
               fine_time_s   <= fine_time_49;
               coarse_time_s <= coarse_time_49;
               rstn_LFR_TM <= '0' WHEN resetn_25MHz = '0' ELSE
                              '0' WHEN soft_reset = '1' ELSE
                              '1';
               -----------------------------------------------------------------------------
               -- LFR_TIME_MANAGMENT
               -----------------------------------------------------------------------------
               lfr_time_management_1 : lfr_time_management
                 GENERIC MAP (
                   --FIRST_DIVISION   => FIRST_DIVISION,
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC)
                 PORT MAP (
                   clk  => clk25MHz,
                   rstn => rstn_LFR_TM,
                   tick           => new_timecode,
                   new_coarsetime => new_coarsetime,
                   coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
                   fine_time       => fine_time_49,
                   fine_time_new   => fine_time_new_49,
                   coarse_time     => coarse_time_49,
                   coarse_time_new => coarse_time_new_49);
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, resetn_25MHz)
                 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14;  -- freq = 2^(16-BIT)
                                       -- for each HK, the update frequency is freq/3
                                       --
                                       -- for 14, the update frequency is
                                       -- 4Hz and update for each
                                       -- HK is 1.33Hz
               BEGIN  -- PROCESS
                 IF resetn_25MHz = '0' THEN                -- asynchronous reset (active low)
                   r.HK_temp_0 <= (OTHERS => '0');
                   r.HK_temp_1 <= (OTHERS => '0');
                   r.HK_temp_2 <= (OTHERS => '0');
                   HK_sel_s <= "00";
                   previous_fine_time_bit <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF HK_val = '1' THEN
                     IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
                       previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
                       CASE HK_sel_s IS
                         WHEN "00" =>
                           r.HK_temp_0 <= HK_sample;
                           HK_sel_s    <= "01";
                         WHEN "01" =>
                           r.HK_temp_1 <= HK_sample;
                           HK_sel_s    <= "10";
                         WHEN "10" =>
                           r.HK_temp_2 <= HK_sample;
                           HK_sel_s    <= "00";
                         WHEN OTHERS => NULL;
                       END CASE;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               HK_sel <= HK_sel_s;
               -----------------------------------------------------------------------------
               -- DAC
               -----------------------------------------------------------------------------
               cal : lfr_cal_driver
                 GENERIC MAP(
                   tech      => tech,
                   PRESZ     => PRESZ,
                   CPTSZ     => CPTSZ,
                   datawidth => datawidth,
                   abits     => abits
                   )
                 PORT MAP(
                   clk  => clk25MHz,
                   rstn => resetn_25MHz,
                   pre           => pre,
                   N             => N,
                   Reload        => Reload,
                   DATA_IN       => DATA_IN,
                   WEN           => WEN,
                   LOAD_ADDRESSN => LOAD_ADDRESSN,
                   ADDRESS_IN    => ADDRESS_IN,
                   ADDRESS_OUT   => ADDRESS_OUT,
                   INTERLEAVED   => INTERLEAVED,
                   DAC_CFG       => DAC_CFG,
                   SYNC   => DAC_SYNC,
                   DOUT   => DAC_SDO,
                   SCLK   => DAC_SCK,
                   SMPCLK => OPEN                    --DAC_SMPCLK
                   );
               DAC_CAL_EN <= DAC_CAL_EN_s;
             END Behavioral;

lib/lpp/lfr_management/lpp_lfr_management.vhd +25 0

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    13:04:01 07/02/2012
             -- Design Name:
             -- Module Name:    lpp_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             PACKAGE lpp_lfr_management IS
             --***************************
             -- APB_LFR_MANAGEMENT
               COMPONENT apb_lfr_management
                 GENERIC (
                   tech             : INTEGER;
                   pindex           : INTEGER;
                   paddr            : INTEGER;
                   pmask            : INTEGER;
             --      FIRST_DIVISION   : INTEGER;
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk25MHz         : IN  STD_LOGIC;
                   resetn_25MHz     : IN  STD_LOGIC;
             --      clk24_576MHz     : IN  STD_LOGIC;
             --      resetn_24_576MHz : IN  STD_LOGIC;
                   grspw_tick       : IN  STD_LOGIC;
                   apbi             : IN  apb_slv_in_type;
                   apbo             : OUT apb_slv_out_type;
                   HK_sample        : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   HK_val           : IN  STD_LOGIC;
                   HK_sel           : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   DAC_SDO          : OUT STD_LOGIC;
                   DAC_SCK          : OUT STD_LOGIC;
                   DAC_SYNC         : OUT STD_LOGIC;
                   DAC_CAL_EN       : OUT STD_LOGIC;
                   coarse_time      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time        : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   LFR_soft_rstn    : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lfr_time_management
                 GENERIC (
                   --FIRST_DIVISION   : INTEGER;
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   new_coarsetime  : IN  STD_LOGIC;
                   coarsetime_reg  : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new   : OUT STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT coarse_time_counter
                 GENERIC (
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   set_TCU         : IN  STD_LOGIC;
                   new_TCU         : IN  STD_LOGIC;
                   set_TCU_value   : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   CT_add1         : IN  STD_LOGIC;
                   fsm_desync      : IN  STD_LOGIC;
                   FT_max          : IN  STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fine_time_counter
                 GENERIC (
                   WAITING_TIME   : STD_LOGIC_VECTOR(15 DOWNTO 0));--;
             --      FIRST_DIVISION : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   tick           : IN  STD_LOGIC;
                   fsm_transition : IN  STD_LOGIC;
                   FT_max         : OUT STD_LOGIC;
                   FT_half        : OUT STD_LOGIC;
                   FT_wait        : OUT STD_LOGIC;
                   fine_time      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new  : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fine_time_max_value_gen
                 PORT (
                   clk                 : IN  STD_LOGIC;
                   rstn                : IN  STD_LOGIC;
                   tick                : IN  STD_LOGIC;
                   fine_time_add       : IN  STD_LOGIC;
                   fine_time_max_value : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
               END COMPONENT;
+              COMPONENT apb_lfr_management_nocal
+                GENERIC (
+                  tech             : INTEGER;
+                  pindex           : INTEGER;
+                  paddr            : INTEGER;
+                  pmask            : INTEGER;
+                  NB_SECOND_DESYNC : INTEGER);
+                PORT (
+                  clk25MHz      : IN  STD_LOGIC;
+                  resetn_25MHz  : IN  STD_LOGIC;
+                  grspw_tick    : IN  STD_LOGIC;
+                  apbi          : IN  apb_slv_in_type;
+                  apbo          : OUT apb_slv_out_type;
+                  HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  HK_val        : IN  STD_LOGIC;
+                  HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+                  DAC_SDO       : OUT STD_LOGIC;
+                  DAC_SCK       : OUT STD_LOGIC;
+                  DAC_SYNC      : OUT STD_LOGIC;
+                  DAC_CAL_EN    : OUT STD_LOGIC;
+                  coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  LFR_soft_rstn : OUT STD_LOGIC);
+              END COMPONENT;
             END lpp_lfr_management;

lib/lpp/lfr_management/vhdlsyn.txt +1 0

             lpp_lfr_management.vhd
             lpp_lfr_management_apbreg_pkg.vhd
             apb_lfr_management.vhd
+            apb_lfr_management_nocal.vhd
             lfr_time_management.vhd
             fine_time_counter.vhd
             coarse_time_counter.vhd
             fine_time_max_value_gen.vhd

lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +1 -2

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.general_purpose.SYNC_FF;
             ENTITY top_ad_conv_RHF1401_withFilter IS
               GENERIC(
                 ChanelCount     : INTEGER := 8;
                 ncycle_cnv_high : INTEGER := 13;
                 ncycle_cnv      : INTEGER := 25;
                 FILTER_ENABLED  : INTEGER := 16#FF#
                 );
               PORT (
                 cnv_clk  : IN STD_LOGIC;            -- 24Mhz
                 cnv_rstn : IN STD_LOGIC;
                 cnv : OUT STD_LOGIC;
                 clk        : IN  STD_LOGIC;         -- 25MHz
                 rstn       : IN  STD_LOGIC;
                 ADC_data   : IN  Samples14;
                 ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                 sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END top_ad_conv_RHF1401_withFilter;
             ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
-              SIGNAL cnv_cycle_counter : INTEGER;
+              SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1;
               SIGNAL cnv_s             : STD_LOGIC;
               SIGNAL cnv_s_reg         : STD_LOGIC;
               SIGNAL cnv_sync          : STD_LOGIC;
               SIGNAL cnv_sync_pre      : STD_LOGIC;
               SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
               SIGNAL enable_ADC : STD_LOGIC;
               SIGNAL sample_reg  : Samples14v(ChanelCount-1 DOWNTO 0);
               SIGNAL channel_counter : INTEGER;
               CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
               SIGNAL ADC_data_selected : Samples14;
               SIGNAL ADC_data_result   : Samples15;
               SIGNAL sample_counter : INTEGER;
               CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
               CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
             BEGIN
               -----------------------------------------------------------------------------
               -- CNV GEN
               -----------------------------------------------------------------------------
               PROCESS (cnv_clk, cnv_rstn)
               BEGIN  -- PROCESS
                 IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
                   cnv_cycle_counter <= 0;
                   cnv_s             <= '0';
                 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
                   IF cnv_cycle_counter < ncycle_cnv-1 THEN
                     cnv_cycle_counter <= cnv_cycle_counter + 1;
                     IF cnv_cycle_counter < ncycle_cnv_high THEN
                       cnv_s <= '1';
                     ELSE
                       cnv_s <= '0';
                     END IF;
                   ELSE
                     cnv_s             <= '1';
                     cnv_cycle_counter <= 0;
                   END IF;
                 END IF;
               END PROCESS;
               cnv <= cnv_s;
               PROCESS (cnv_clk, cnv_rstn)
               BEGIN  -- PROCESS
                 IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
                   cnv_s_reg             <= '0';
                 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
                   cnv_s_reg             <= cnv_s;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SYNC CNV
               -----------------------------------------------------------------------------
               SYNC_FF_cnv : SYNC_FF
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk    => clk,
                   rstn   => rstn,
                   A      => cnv_s_reg,
                   A_sync => cnv_sync);
               -----------------------------------------------------------------------------
               -- DATA GEN Output Enable
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
                   cnv_sync_pre                        <= '0';
                   enable_ADC <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   cnv_sync_pre                        <= cnv_sync;
                   IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
                     enable_ADC     <= '1';
                     ADC_nOE_reg(0) <= '0';
                     ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
                   ELSE
                     enable_ADC <= NOT enable_ADC;
                     IF enable_ADC = '0' THEN
                       ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
               -----------------------------------------------------------------------------
               -- ADC READ DATA
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   channel_counter <= MAX_COUNTER;
                   all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
                     sample_reg(I) <= (OTHERS => '0');
                   END LOOP all_sample_reg_init;
                   sample_val     <= '0';
                   sample_counter <= 0;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
                     channel_counter <= 0;
                   ELSE
                     IF channel_counter < MAX_COUNTER THEN
                       channel_counter <= channel_counter + 1;
                     END IF;
                   END IF;
                   sample_val     <= '0';
                   all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
                     IF channel_counter = I*2 THEN
                       IF FILTER_ENABLED_STDLOGIC(I) = '1'  THEN
                         sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
                       ELSE
                         sample_reg(I) <= ADC_data;
                       END IF;
                     END IF;
                   END LOOP all_sample_reg;
                   IF channel_counter = (ChanelCount-1)*2 THEN
                     IF sample_counter = MAX_SAMPLE_COUNTER THEN
                       sample_counter <= 0 ;
                       sample_val     <= '1';
                     ELSE
                       sample_counter <= sample_counter +1;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
             --  mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
             --  BEGIN  -- PROCESS mux_adc
             --    CASE channel_counter IS
             --      WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
             --    END CASE;
             --  END PROCESS mux_adc;
                -----------------------------------------------------------------------------
               -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
               -----------------------------------------------------------------------------
               WITH channel_counter SELECT
                 ADC_data_selected <= sample_reg(0) WHEN 0*2,
                                      sample_reg(1) WHEN 1*2,
                                      sample_reg(2) WHEN 2*2,
                                      sample_reg(3) WHEN 3*2,
                                      sample_reg(4) WHEN 4*2,
                                      sample_reg(5) WHEN 5*2,
                                      sample_reg(6) WHEN 6*2,
                                      sample_reg(7) WHEN 7*2,
                                      sample_reg(8) WHEN OTHERS ;
               -----------------------------------------------------------------------------
               -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
               -----------------------------------------------------------------------------
               ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
               sample <= sample_reg;
             END ar_top_ad_conv_RHF1401;

lib/lpp/lpp_cna/dynamic_freq_div.vhd +66 -65

@@ -1,99 +1,100
1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
3	-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4	--	4	--
5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
8	-- (at your option) any later version.	8	-- (at your option) any later version.
9	--	9	--
10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
14	--	14	--
15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
19	-- Author : Alexis Jeandet	19	-- Author : Alexis Jeandet
20	-- Mail : alexis.jeandet@member.fsf.org	20	-- Mail : alexis.jeandet@member.fsf.org
21	------------------------------------------------------------------------------	21	------------------------------------------------------------------------------
22	library IEEE;	22	LIBRARY IEEE;
23	~~use~~ IEEE.STD_LOGIC_1164.ALL;	23	USE IEEE.STD_LOGIC_1164.ALL;
24	~~use~~ IEEE.NUMERIC_STD.ALL;	24	USE IEEE.NUMERIC_STD.ALL;
25		25
26	~~entity~~ dynamic_freq_div is	26	ENTITY dynamic_freq_div IS
27	generic(	27	GENERIC(
28	PRESZ : integer range 1 to 32:=4;	28	PRESZ : INTEGER RANGE 1 TO 32 := 4;
29	PREMAX : ~~integer~~ := 16#FFFFFF#;	29	PREMAX : INTEGER := 16#FFFFFF#;
30	CPTSZ : integer range 1 to 32:=16	30	CPTSZ : INTEGER RANGE 1 TO 32 := 16
31	);	31	);
32	Port (	32	PORT (
33	clk : in STD_LOGIC;	33	clk : IN STD_LOGIC;
34	rstn : in STD_LOGIC;	34	rstn : IN STD_LOGIC;
35	pre : in STD_LOGIC_VECTOR(PRESZ-1 ~~downto~~ 0);	35	pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
36	N : in STD_LOGIC_VECTOR(CPTSZ-1 ~~downto~~ 0);	36	N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
37	Reload : in ~~std_logic~~;	37	Reload : IN STD_LOGIC;
38	clk_out : ~~out~~ STD_LOGIC	38	clk_out : OUT STD_LOGIC
39	);	39	);
40	~~end~~ dynamic_freq_div;	40	END dynamic_freq_div;
41		41
42	~~architecture~~ Behavioral of dynamic_freq_div is	42	ARCHITECTURE Behavioral OF dynamic_freq_div IS
43	constant prescaller_reg_sz : integer := 2**PRESZ;	43	CONSTANT prescaller_reg_sz : INTEGER := 2**PRESZ;
44	~~constant~~ PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 ~~downto~~ 0):=(~~others~~ => '1');	44	CONSTANT PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0) := (OTHERS => '1');
45	signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');	45	SIGNAL cpt_reg : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0) := (OTHERS => '0');
46	~~signal~~ prescaller_reg : ~~std_logic_vector~~(prescaller_reg_sz-1 ~~downto~~ 0);--:=(others => '0');	46	SIGNAL prescaller_reg : STD_LOGIC_VECTOR(prescaller_reg_sz-1 DOWNTO 0); --:=(others => '0');
47	signal internal_clk : std_logic:='0';	47	SIGNAL internal_clk : STD_LOGIC := '0';
48	signal internal_clk_reg : std_logic:='0';	48	SIGNAL internal_clk_reg : STD_LOGIC := '0';
49	signal clk_out_reg : std_logic:='0';	49	SIGNAL clk_out_reg : STD_LOGIC := '0';
		50
		51	BEGIN
50		52
51	begin	53	max0 : IF (UNSIGNED(PREMAX_max) < PREMAX) GENERATE
52		54
53	max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate	55	internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= UNSIGNED(PREMAX_max)) ELSE
54
55	internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
56	prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));	56	prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
57	end generate;	57	END GENERATE;
58	max1: if UNSIGNED(PREMAX_max) > PREMAX generate	58
59	internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else	59	max1 : IF UNSIGNED(PREMAX_max) > PREMAX GENERATE
		60	internal_clk <= prescaller_reg(to_integer(UNSIGNED(pre))) WHEN (to_integer(UNSIGNED(pre)) <= PREMAX) ELSE
60	prescaller_reg(PREMAX);	61	prescaller_reg(PREMAX);
61	end generate;	62	END GENERATE;
62		63
63		64
64		65
65	prescaller: ~~process~~(rstn, clk)	66	prescaller : PROCESS(rstn, clk)
66	begin	67	BEGIN
67	if rstn='0' then	68	IF rstn = '0' then
68	prescaller_reg <= (~~others~~ => '0');	69	prescaller_reg <= (OTHERS => '0');
69	elsif clk'event and clk = '1' then	70	ELSIF clk'EVENT AND clk = '1' THEN
70	prescaller_reg <= ~~std_logic_vector~~(UNSIGNED(prescaller_reg) + 1);	71	prescaller_reg <= STD_LOGIC_VECTOR(UNSIGNED(prescaller_reg) + 1);
71	end if;	72	END IF;
72	end process;	73	END PROCESS;
73		74
74		75
75	clk_out <= clk_out_reg;	76	clk_out <= clk_out_reg;
76		77
77	counter: ~~process~~(rstn, clk)	78	counter : PROCESS(rstn, clk)
78	begin	79	BEGIN
79	if rstn='0' then	80	IF rstn = '0' then
80	cpt_reg <= (~~others~~ => '0');	81	cpt_reg <= (OTHERS => '0');
81	internal_clk_reg <= '0';	82	internal_clk_reg <= '0';
82	clk_out_reg <= '0';	83	clk_out_reg <= '0';
83	elsif clk'event and clk = '1' then	84	ELSIF clk'EVENT AND clk = '1' THEN
84	internal_clk_reg <= internal_clk;	85	internal_clk_reg <= internal_clk;
85	if Reload = '1' ~~then~~	86	IF Reload = '1' THEN
86	clk_out_reg <= '0';	87	clk_out_reg <= '0';
87	cpt_reg <= (~~others~~ => '0');	88	cpt_reg <= (OTHERS => '0');
88	~~elsif~~ (internal_clk = '1' ~~and~~ internal_clk_reg = '0') ~~then~~	89	ELSIF (internal_clk = '1' AND internal_clk_reg = '0') THEN
89	if cpt_reg = N ~~then~~	90	IF cpt_reg = N THEN
90	clk_out_reg <= ~~not~~ clk_out_reg;	91	clk_out_reg <= NOT clk_out_reg;
91	cpt_reg <= (~~others~~ => '0');	92	cpt_reg <= (OTHERS => '0');
92	~~else~~	93	ELSE
93	cpt_reg <= ~~std_logic_vector~~(UNSIGNED(cpt_reg) + 1);	94	cpt_reg <= STD_LOGIC_VECTOR(UNSIGNED(cpt_reg) + 1);
94	~~end~~ if;	95	END IF;
95	end if;	96	END IF;
96	end if;	97	END IF;
97	end process;	98	END PROCESS;
98		99
99	~~end~~ Behavioral; No newline at end of file	100	END Behavioral;

lib/lpp/lpp_dma/DMA_SubSystem.vhd +2 -2

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             --USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             --USE lpp.lpp_top_lfr_pkg.ALL;
             --USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY DMA_SubSystem IS
               GENERIC (
                 hindex     : INTEGER := 2;
                 CUSTOM_DMA : INTEGER := 1);
               PORT (
                 clk                            : IN  STD_LOGIC;
                 rstn                           : IN  STD_LOGIC;
                 run                            : IN  STD_LOGIC;
                 -- AHB
                 ahbi                           : IN  AHB_Mst_In_Type;
                 ahbo                           : OUT AHB_Mst_Out_Type;
                 ---------------------------------------------------------------------------
                 fifo_burst_valid               : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 fifo_data                      : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 fifo_ren                       : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 buffer_new                     : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_addr                    : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 buffer_length                  : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
                 buffer_full                    : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_full_err                : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 grant_error                    : OUT STD_LOGIC;
                 ---------------------------------------------------------------------------
                 debug_vector                   : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
                 );
             END DMA_SubSystem;
             ARCHITECTURE beh OF DMA_SubSystem IS
               COMPONENT DMA_SubSystem_GestionBuffer
                 GENERIC (
                   BUFFER_ADDR_SIZE   : INTEGER;
                   BUFFER_LENGTH_SIZE : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  run             : IN  STD_LOGIC;
+            --      run             : IN  STD_LOGIC;
                   buffer_new      : IN  STD_LOGIC;
                   buffer_addr     : IN  STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
                   buffer_length   : IN  STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
                   buffer_full     : OUT STD_LOGIC;
                   buffer_full_err : OUT STD_LOGIC;
                   burst_send      : IN  STD_LOGIC;
                   burst_addr      : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_Arbiter
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   data_burst_valid       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_MUX
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   dma_send        : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_ren         : IN  STD_LOGIC;
                   dma_done        : IN  STD_LOGIC;
                   grant_error     : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL burst_send      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_grant      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_address    : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);  --
               SIGNAL ahbo_s          : AHB_Mst_Out_Type;
               SIGNAL fifo_ren_s      : STD_LOGIC_VECTOR(4 DOWNTO 0);
             BEGIN  -- beh
               debug_vector <= fifo_ren_s(0) &
                               dma_data(1 DOWNTO 0) &
                               ahbi.HREADY &
                               ahbo_s.HWDATA(1 DOWNTO 0) &
                               ahbi.HGRANT(hindex) &
                               ahbo_s.HTRANS(0) &
                               ahbo_s.HLOCK;
               ahbo     <= ahbo_s;
               fifo_ren <= fifo_ren_s;
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               GR_DMA : IF CUSTOM_DMA = 0 GENERATE
                 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                   GENERIC MAP (
                     tech   => inferred,
                     hindex => hindex)
                   PORT MAP (
                     HCLK           => clk,
                     HRESETn        => rstn,
                     run            => run,
                     AHB_Master_In  => ahbi,
                     AHB_Master_Out => ahbo_s,
                     send        => dma_send,
                     valid_burst => dma_valid_burst,
                     done        => dma_done,
                     ren         => dma_ren,
                     address     => dma_address,
                     data        => dma_data);
               END GENERATE GR_DMA;
               LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
                 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
                   GENERIC MAP (
                     hindex   => hindex,
                     vendorid => VENDOR_LPP,
                     deviceid => 10,
                     version  => 0)
                   PORT MAP (
                     clk            => clk,
                     rstn           => rstn,
                     AHB_Master_In  => ahbi,
                     AHB_Master_Out => ahbo_s,
                     ren         => dma_ren,
                     data        => dma_data,
                     send        => dma_send,
                     valid_burst => dma_valid_burst,
                     done        => dma_done,
                     address     => dma_address);
               END GENERATE LPP_DMA_IP;
               -----------------------------------------------------------------------------
               -- RoundRobin Selection Channel For DMA
               -----------------------------------------------------------------------------
               DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   data_burst_valid       => fifo_burst_valid,
                   data_burst_valid_grant => fifo_grant);
               -----------------------------------------------------------------------------
               -- Mux between the channel from Waveform Picker and Spectral Matrix
               -----------------------------------------------------------------------------
               DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
                 PORT MAP (
                   clk             => clk,
                   rstn            => rstn,
                   run             => run,
                   fifo_grant      => fifo_grant,
                   fifo_data       => fifo_data,
                   fifo_address    => fifo_address,
                   fifo_ren        => fifo_ren_s,
                   fifo_burst_done => burst_send,
                   dma_send        => dma_send,
                   dma_valid_burst => dma_valid_burst,
                   dma_address     => dma_address,
                   dma_data        => dma_data,
                   dma_ren         => dma_ren,
                   dma_done        => dma_done,
                   grant_error     => grant_error);
               -----------------------------------------------------------------------------
               -- GEN ADDR
               -----------------------------------------------------------------------------
               all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
                 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
                   GENERIC MAP (
                     BUFFER_ADDR_SIZE   => 32,
                     BUFFER_LENGTH_SIZE => 26)
                   PORT MAP (
                     clk  => clk,
                     rstn => rstn,
-                    run  => run,
+            --        run  => run,
                     buffer_new      => buffer_new(I),
                     buffer_addr     => buffer_addr(32*(I+1)-1 DOWNTO I*32),
                     buffer_length   => buffer_length(26*(I+1)-1 DOWNTO I*26),
                     buffer_full     => buffer_full(I),
                     buffer_full_err => buffer_full_err(I),
                     burst_send => burst_send(I),
                     burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
                     );
               END GENERATE all_buffer;
             END beh;

lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd +1 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             ENTITY DMA_SubSystem_GestionBuffer IS
               GENERIC (
                 BUFFER_ADDR_SIZE   : INTEGER := 32;
                 BUFFER_LENGTH_SIZE : INTEGER := 26);
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
-                run  : IN STD_LOGIC;
+            --    run  : IN STD_LOGIC;
                 --
                 buffer_new      : IN STD_LOGIC;
                 buffer_addr     : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1   DOWNTO 0);
                 buffer_length   : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);  --in 64B
                 buffer_full     : OUT STD_LOGIC;
                 buffer_full_err : OUT STD_LOGIC;
                 --
                 burst_send    : IN STD_LOGIC;
                 burst_addr    : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)
                 );
             END DMA_SubSystem_GestionBuffer;
             ARCHITECTURE beh OF DMA_SubSystem_GestionBuffer IS
               TYPE state_DMA_GestionBuffer IS (IDLE, ON_GOING);
               SIGNAL state : state_DMA_GestionBuffer;
               SIGNAL burst_send_counter      : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
               SIGNAL burst_send_counter_add1 : STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
               SIGNAL addr_shift              : STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
             BEGIN
               addr_shift <= burst_send_counter & "000000";
               burst_addr <= STD_LOGIC_VECTOR(unsigned(buffer_addr) + unsigned(addr_shift));
               burst_send_counter_add1 <= STD_LOGIC_VECTOR(unsigned(burst_send_counter) + 1);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   burst_send_counter <= (OTHERS => '0');
                   state       <= IDLE;
                   buffer_full     <= '0';
                   buffer_full_err <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   CASE state IS
                     WHEN IDLE     =>
                       burst_send_counter <= (OTHERS => '0');
                       buffer_full_err <= burst_send;
                       buffer_full     <= '0';
                       IF buffer_new = '1' THEN
                         state <= ON_GOING;
                       END IF;
                     WHEN ON_GOING =>
                       buffer_full_err <= '0';
                       buffer_full     <= '0';
                       IF burst_send = '1' THEN
                         IF unsigned(burst_send_counter_add1) < unsigned(buffer_length) THEN
                           burst_send_counter <= burst_send_counter_add1;
                         ELSE
                           buffer_full <= '1';
                           state       <= IDLE;
                         END IF;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +251 -255

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	@@ -1,255 +1,251
	1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com	21	-- jean-christophe.pellion@easii-ic.com
	22	-------------------------------------------------------------------------------	22	-------------------------------------------------------------------------------
	23	-- 1.0 - initial version	23	-- 1.0 - initial version
	24	-------------------------------------------------------------------------------	24	-------------------------------------------------------------------------------
	25	LIBRARY ieee;	25	LIBRARY ieee;
	26	USE ieee.std_logic_1164.ALL;	26	USE ieee.std_logic_1164.ALL;
	27	USE ieee.numeric_std.ALL;	27	USE ieee.numeric_std.ALL;
	28	LIBRARY grlib;	28	LIBRARY grlib;
	29	USE grlib.amba.ALL;	29	USE grlib.amba.ALL;
	30	USE grlib.stdlib.ALL;	30	USE grlib.stdlib.ALL;
	31	USE grlib.devices.ALL;	31	USE grlib.devices.ALL;
	32		32
	33	LIBRARY lpp;	33	LIBRARY lpp;
	34	USE lpp.lpp_amba.ALL;	34	USE lpp.lpp_amba.ALL;
	35	USE lpp.apb_devices_list.ALL;	35	USE lpp.apb_devices_list.ALL;
	36	USE lpp.lpp_memory.ALL;	36	USE lpp.lpp_memory.ALL;
	37	USE lpp.lpp_dma_pkg.ALL;	37	USE lpp.lpp_dma_pkg.ALL;
	38	USE lpp.general_purpose.ALL;	38	USE lpp.general_purpose.ALL;
	39	--USE lpp.lpp_waveform_pkg.ALL;	39	--USE lpp.lpp_waveform_pkg.ALL;
	40	LIBRARY techmap;	40	LIBRARY techmap;
	41	USE techmap.gencomp.ALL;	41	USE techmap.gencomp.ALL;
	42		42
	43		43
	44	ENTITY lpp_dma_SEND16B_FIFO2DMA IS	44	ENTITY lpp_dma_SEND16B_FIFO2DMA IS
	45	GENERIC (	45	GENERIC (
	46	hindex : INTEGER := 2;	46	hindex : INTEGER := 2;
	47	vendorid : IN INTEGER := 0;	47	vendorid : IN INTEGER := 0;
	48	deviceid : IN INTEGER := 0;	48	deviceid : IN INTEGER := 0;
	49	version : IN INTEGER := 0	49	version : IN INTEGER := 0
	50	);	50	);
	51	PORT (	51	PORT (
	52	clk : IN STD_LOGIC;	52	clk : IN STD_LOGIC;
	53	rstn : IN STD_LOGIC;	53	rstn : IN STD_LOGIC;
	54		54
	55	-- AMBA AHB Master Interface	55	-- AMBA AHB Master Interface
	56	AHB_Master_In : IN AHB_Mst_In_Type;	56	AHB_Master_In : IN AHB_Mst_In_Type;
	57	AHB_Master_Out : OUT AHB_Mst_Out_Type;	57	AHB_Master_Out : OUT AHB_Mst_Out_Type;
	58		58
	59	-- FIFO Interface	59	-- FIFO Interface
	60	ren : OUT STD_LOGIC;	60	ren : OUT STD_LOGIC;
	61	data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	61	data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	62		62
	63	-- Controls	63	-- Controls
	64	send : IN STD_LOGIC;	64	send : IN STD_LOGIC;
	65	valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)	65	valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
	66	done : OUT STD_LOGIC;	66	done : OUT STD_LOGIC;
	67	address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)	67	address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
	68	);	68	);
	69	END;	69	END;
	70		70
	71	ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS	71	ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
	72		72
	73	CONSTANT HConfig : AHB_Config_Type := (	73	CONSTANT HConfig : AHB_Config_Type := (
	74	0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),	74	0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
	75	OTHERS => (OTHERS => '0'));	75	OTHERS => (OTHERS => '0'));
	76		76
	77	TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);	77	TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
	78	SIGNAL state : AHB_DMA_FSM_STATE;	78	SIGNAL state : AHB_DMA_FSM_STATE;
	79		79
	80	SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);	80	SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
	81	SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);	81
	82		82	SIGNAL data_window : STD_LOGIC;
	83	SIGNAL ~~data~~_window : STD_LOGIC;	83	SIGNAL ctrl_window : STD_LOGIC;
	84	SIGNAL ctrl_window : STD_LOGIC;	84
	85		85	SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
	86	SIGNAL bus_request : STD_LOGIC;	86
	87	SIGNAL ~~bus_lock~~ : STD_LOGIC;	87	SIGNAL HREADY_pre : STD_LOGIC;
	88		88	SIGNAL HREADY_falling : STD_LOGIC;
	89	SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);	89
	90		90	SIGNAL inhib_ren : STD_LOGIC;
	91	SIGNAL HREADY_pre : STD_LOGIC;	91
	92	SIGNAL HREADY_falling : STD_LOGIC;	92	BEGIN
	93		93
	94	SIGNAL inhib_ren : STD_LOGIC;	94	-----------------------------------------------------------------------------
	95		95	AHB_Master_Out.HCONFIG <= HConfig;
	96	BEGIN	96	AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
	97		97	AHB_Master_Out.HINDEX <= hindex;
	98	-----------------------------------------------------------------------------	98	AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
	99	AHB_Master_Out.H~~CONFIG~~ <= ~~HConfig~~;	99	AHB_Master_Out.HIRQ <= (OTHERS => '0');
	100	AHB_Master_Out.H~~SIZE~~ <= "~~010~~"; ~~--WORDS 32b~~	100	AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
	101	AHB_Master_Out.H~~INDEX~~ <= ~~hindex~~;	101	AHB_Master_Out.HWRITE <= '1';
	102	AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS	102
	103	AHB_Master_Out.HIRQ <= (OTHERS => '0');	103	--AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
	104	AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16	104
	105	AHB_Master_Out.H~~WRITE~~ <= ~~'1'~~;	105	--AHB_Master_Out.HBUSREQ <= bus_request;
	106		106	--AHB_Master_Out.HLOCK <= data_window;
	107	--AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;	107
	108		108	--bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
	109	--AHB_Master_Out.HBUSREQ <= bus_request;	109	-- '1' WHEN ctrl_window = '1' ELSE
	110	--AHB_Master_Out.HLOCK <= data_window;	110	-- '0';
	111		111
	112	~~--bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE~~	112	--bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
	113	-- '1' WHEN ctrl_window = '1' ELSE	113	-- '1' WHEN ctrl_window = '1' ELSE '0';
	114	-- '0';	114
	115		115	-----------------------------------------------------------------------------
	116	--bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE	116	AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
	117	-- '1' WHEN ctrl_window = '1' ELSE '0';	117	AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
	118		118
	119	-----------------------------------------------------------------------------	119	-----------------------------------------------------------------------------
	120	AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";	120	--ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
	121	AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);	121	--ren <= NOT beat;
	122		122	-----------------------------------------------------------------------------
	123	-----------------------------------------------------------------------------	123
	124	--ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );	124	HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
	125	--ren <= NOT beat;	125
	126	-----------------------------------------------------------------------------	126
	127		127	PROCESS (clk, rstn)
	128	HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';	128	BEGIN -- PROCESS
	129		129	IF rstn = '0' THEN -- asynchronous reset (active low)
	130		130	state <= IDLE;
	131	PROCESS (clk, rstn)	131	done <= '0';
	132	BEGIN -- PROCESS	132	ren <= '1';
	133	IF rstn = '0' THEN -- asynchronous reset (active low)	133	address_counter_reg <= (OTHERS => '0');
	134	state <= IDLE;	134	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	135	done <= '0';	135	AHB_Master_Out.HBUSREQ <= '0';
	136	ren <= '1';	136	AHB_Master_Out.HLOCK <= '0';
	137	address_counter_reg <= (OTHERS => '0');	137
	138	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	138	data_reg <= (OTHERS => '0');
	139	AHB_Master_Out.HBUSREQ <= '0';	139
	140	AHB_Master_Out.HLOCK <= '0';	140	HREADY_pre <= '0';
	141		141	inhib_ren <= '0';
	142	data_reg <= (OTHERS => '0');	142	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	143		143	HREADY_pre <= AHB_Master_In.HREADY;
	144	HREADY_pre <= '0';	144
	145	inhib_ren <= '0';	145	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	146	ELSIF clk'event AND clk = '1' THEN -- rising clock edge	146	data_reg <= data;
	147	HREADY_pre <= AHB_Master_In.HREADY;	147	END IF;
	148		148
	149	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN	149	done <= '0';
	150	~~data_reg~~ <= ~~data~~;	150	ren <= '1';
	151	END IF;	151	inhib_ren <= '0';
	152		152	CASE state IS
	153	done <= '0';	153	WHEN IDLE =>
	154	ren <= '1';	154	AHB_Master_Out.HBUSREQ <= '0';
	155	inhib_ren <= '0';	155	AHB_Master_Out.HLOCK <= '0';
	156	CASE state IS	156	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	157	WHEN IDLE =>	157	address_counter_reg <= (OTHERS => '0');
	158	AHB_Master_Out.HBUSREQ <= '0';	158	IF send = '1' THEN
	159	AHB_Master_Out.HLOCK <= '0';	159	state <= s_INIT_TRANS;
	160	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	160	END IF;
	161	address_counter_reg <= (OTHERS => '0');	161
	162	IF send = '1' THEN	162	WHEN s_INIT_TRANS =>
	163	state <= s_INIT_TRANS;	163	AHB_Master_Out.HBUSREQ <= '1';
	164	END IF;	164	AHB_Master_Out.HLOCK <= '1';
	165		165	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	166	WHEN s_INIT_TRANS =>	166	state <= s_ARBITER;
	167	AHB_Master_Out.HBUSREQ <= '1';	167
	168	AHB_Master_Out.HLOCK <= '1';	168	WHEN s_ARBITER =>
	169	AHB_Master_Out.H~~TRANS~~ <= ~~HTRANS_IDLE~~;	169	AHB_Master_Out.HBUSREQ <= '1';
	170	state <= s_ARBITER;	170	AHB_Master_Out.HLOCK <= '1';
	171		171	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	172	WHEN s_ARBITER =>	172	address_counter_reg <= (OTHERS => '0');
	173	AHB_Master_Out.HBUSREQ <= '1';	173
	174	AHB_Master_Out.HLOCK <= '1';	174	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	175	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	175	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	176	address_counter_reg <= (OTHERS => '0');	176	state <= s_CTRL;
	177		177	END IF;
	178	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN	178
	179	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	179	WHEN s_CTRL =>
	180	state <= s_CTRL;	180	inhib_ren <= '1';
	181	END IF;	181	AHB_Master_Out.HBUSREQ <= '1';
	182		182	AHB_Master_Out.HLOCK <= '1';
	183	WHEN s_CTRL =>	183	AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
	184	inhib_ren <= '1';	184	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	185	AHB_Master_Out.H~~BUSREQ~~ <= ~~'1'~~;	185	--AHB_Master_Out.HTRANS <= HTRANS_SEQ;
	186	AHB_Master_Out.HLOCK <= '1';	186	state <= s_CTRL_DATA;
	187	AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;	187	--ren <= '0';
	188	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN	188	END IF;
	189	--AHB_Master_Out.HTRANS <= HTRANS_SEQ;	189
	190	~~state~~ <= s_CTRL_DATA;	190	WHEN s_CTRL_DATA =>
	191	--ren <= '0';	191	AHB_Master_Out.HBUSREQ <= '1';
	192	END IF;	192	AHB_Master_Out.HLOCK <= '1';
	193		193	AHB_Master_Out.HTRANS <= HTRANS_SEQ;
	194	WHEN s_CTRL_DATA =>	194	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	195	AHB_Master_Out.HBUSREQ <= '1';	195	address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
	196	AHB_Master_Out.HLOCK <= '1';	196	END IF;
	197	AHB_Master_Out.HTRANS <= HTRANS_SEQ;	197
	198	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN	198	IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
	199	address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);	199	AHB_Master_Out.HBUSREQ <= '0';
	200	END IF;	200	AHB_Master_Out.HLOCK <= '1';--'0';
	201		201	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	202	IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN	202	state <= s_DATA;
	203	AHB_Master_Out.HBUSREQ <= '0';	203	END IF;
	204	AHB_Master_Out.HLOCK <= '1';--'0';	204
	205	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	205	ren <= HREADY_falling;
	206	state <= s_DATA;	206
	207	END IF;	207	--IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
	208		208	-- ren <= '0';
	209	ren <= HREADY_falling;	209	--END IF;
	210		210
	211	--IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN	211
	212	-- ren <= '0';	212	WHEN s_DATA =>
	213	--END IF;	213	ren <= HREADY_falling;
	214		214
	215		215	AHB_Master_Out.HBUSREQ <= '0';
	216	WHEN s_DATA =>	216	--AHB_Master_Out.HLOCK <= '0';
	217	ren <= HREADY_falling;	217	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	218		218	IF AHB_Master_In.HREADY = '1' THEN
	219	AHB_Master_Out.H~~BUSREQ~~ <= '0';	219	AHB_Master_Out.HLOCK <= '0';
	220	--AHB_Master_Out.HLOCK <= '0';	220	state <= IDLE;
	221	AHB_Master_Out.HTRANS <= HTRANS_IDLE;	221	done <= '1';
	222	IF AHB_Master_In.HREADY = '1' THEN	222	END IF;
	223	AHB_Master_Out.HLOCK <= '0';	223
	224	state <= IDLE;	224	WHEN OTHERS => NULL;
	225	done <= '1';	225	END CASE;
	226	END IF;	226	END IF;
	227		227	END PROCESS;
	228	WHEN OTHERS => NULL;	228
	229	END CASE;	229	ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
	230	END IF;	230	data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
	231	END PROCESS;	231	-----------------------------------------------------------------------------
	232		232
	233	ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';	233
	234	data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';	234	--ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
	235	-----------------------------------------------------------------------------	235
	236		236	-----------------------------------------------------------------------------
	237		237	--PROCESS (clk, rstn)
	238	--ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';	238	--BEGIN -- PROCESS
	239		239	-- IF rstn = '0' THEN -- asynchronous reset (active low)
	240	-----------------------------------------------------------------------------	240	-- address_counter_reg <= (OTHERS => '0');
	241	--PROCESS (clk, rstn)	241	-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	242	--BEGIN -- PROCESS	242	-- address_counter_reg <= address_counter;
	243	-- IF rstn = '0' THEN -- asynchronous reset (active low)	243	-- END IF;
	244	-- address_counter_reg <= (OTHERS => '0');	244	--END PROCESS;
	245	-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge	245
	246	-- address_counter_reg <= address_counter;	246	--address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
	247	-- END IF;	247	-- address_counter_reg;
	248	--END PROCESS;	248	-----------------------------------------------------------------------------
	249		249
	250	--address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE	250
	251	-- address_counter_reg;	251	END Behavioral; No newline at end of file
	252	-----------------------------------------------------------------------------
	253
	254
	255	END Behavioral;

lib/lpp/lpp_dma/lpp_dma_pkg.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE std.textio.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             --LIBRARY lpp;
             --USE lpp.lpp_amba.ALL;
             --USE lpp.apb_devices_list.ALL;
             --USE lpp.lpp_memory.ALL;
             PACKAGE lpp_dma_pkg IS
               COMPONENT lpp_dma
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   apbi           : IN  apb_slv_in_type;
                   apbo           : OUT apb_slv_out_type;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   -- fifo interface
                   fifo_data      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty     : IN  STD_LOGIC;
                   fifo_ren       : OUT STD_LOGIC;
                   -- header
                   header         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val     : IN  STD_LOGIC;
                   header_ack     : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_test_dma
                 GENERIC (
                   tech   : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER);
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   apbi       : IN  apb_slv_in_type;
                   apbo       : OUT apb_slv_out_type;
                   -- fifo interface
                   fifo_data  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : OUT STD_LOGIC;
                   fifo_ren   : IN  STD_LOGIC;
                   -- header
                   header     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val : OUT STD_LOGIC;
                   header_ack : IN  STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT lpp_dma_apbreg
                 GENERIC (
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK                          : IN  STD_ULOGIC;
                   HRESETn                       : IN  STD_ULOGIC;
                   apbi                          : IN  apb_slv_in_type;
                   apbo                          : OUT apb_slv_out_type;
                   -- IN
                   ready_matrix_f0_0             : IN  STD_LOGIC;
                   ready_matrix_f0_1             : IN  STD_LOGIC;
                   ready_matrix_f1               : IN  STD_LOGIC;
                   ready_matrix_f2               : IN  STD_LOGIC;
                   error_anticipating_empty_fifo : IN  STD_LOGIC;
                   error_bad_component_error     : IN  STD_LOGIC;
                   debug_reg                     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                   -- OUT
                   status_ready_matrix_f0_0             : OUT STD_LOGIC;
                   status_ready_matrix_f0_1             : OUT STD_LOGIC;
                   status_ready_matrix_f1               : OUT STD_LOGIC;
                   status_ready_matrix_f2               : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo : OUT STD_LOGIC;
                   status_error_bad_component_error     : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_dma_send_1word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_send_16word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_latency_correction
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   fifo_data  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : IN  STD_LOGIC;
                   fifo_ren   : OUT STD_LOGIC;
                   dma_data   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_empty  : OUT STD_LOGIC;
                   dma_ren    : IN  STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_ip
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   AHB_Master_In                          : IN  AHB_Mst_In_Type;
                   AHB_Master_Out                         : OUT AHB_Mst_Out_Type;
                   fifo_data                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty                             : IN  STD_LOGIC;
                   fifo_ren                               : OUT STD_LOGIC;
                   header                                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val                             : IN  STD_LOGIC;
                   header_ack                             : OUT STD_LOGIC;
                   ready_matrix_f0_0                      : OUT STD_LOGIC;
                   ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
                   error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : IN  STD_LOGIC;
                   status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
                   status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
                   status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_dma_singleOrBurst
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   run            : IN  STD_LOGIC;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   send           : IN  STD_LOGIC;
                   valid_burst    : IN  STD_LOGIC;
                   done           : OUT STD_LOGIC;
                   ren            : OUT STD_LOGIC;
                   address        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data           : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_dmaout_okay : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- DMA_SubSystem
               -----------------------------------------------------------------------------
               COMPONENT DMA_SubSystem
                 GENERIC (
                   hindex : INTEGER;
                   CUSTOM_DMA : INTEGER := 1);
                 PORT (
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   run              : IN  STD_LOGIC;
                   ahbi             : IN  AHB_Mst_In_Type;
                   ahbo             : OUT AHB_Mst_Out_Type;
                   fifo_burst_valid : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data        : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren         : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_new       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_addr      : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   buffer_length    : IN  STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
                   buffer_full      : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_full_err  : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   grant_error      : OUT STD_LOGIC;
                   debug_vector                   : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT DMA_SubSystem_GestionBuffer
                 GENERIC (
                   BUFFER_ADDR_SIZE   : INTEGER;
                   BUFFER_LENGTH_SIZE : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
-                  run             : IN  STD_LOGIC;
+            --      run             : IN  STD_LOGIC;
                   buffer_new      : IN  STD_LOGIC;
                   buffer_addr     : IN  STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
                   buffer_length   : IN  STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
                   buffer_full     : OUT STD_LOGIC;
                   buffer_full_err : OUT STD_LOGIC;
                   burst_send      : IN  STD_LOGIC;
                   burst_addr      : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_Arbiter
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   data_burst_valid       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_MUX
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   dma_send        : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_ren         : IN  STD_LOGIC;
                   dma_done        : IN  STD_LOGIC;
                   grant_error     : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_SEND16B_FIFO2DMA
                 GENERIC (
                   hindex   :    INTEGER;
                   vendorid : in Integer;
                   deviceid : in Integer;
                   version  : in Integer);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   ren            : OUT STD_LOGIC;
                   data           : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   send           : IN  STD_LOGIC;
                   valid_burst    : IN  STD_LOGIC;
                   done           : OUT STD_LOGIC;
                   address        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
             END;

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +8 -8

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             LIBRARY iap;
             USE iap.memctrl.ALL;
             ENTITY leon3_soc IS
               GENERIC (
-                fabtech           : INTEGER := apa3e;
+                fabtech           : INTEGER := axcel;--apa3e;
-                memtech           : INTEGER := apa3e;
+                memtech           : INTEGER := axcel;--apa3e;
                 padtech           : INTEGER := inferred;
                 clktech           : INTEGER := inferred;
                 disas             : INTEGER := 0;      -- Enable disassembly to console
                 dbguart           : INTEGER := 0;      -- Print UART on console
                 pclow             : INTEGER := 2;
                 --
                 clk_freq          : INTEGER := 25000;  --kHz
                 --
-                IS_RADHARD        : INTEGER := 0;
+                IS_RADHARD        : INTEGER := 1;
                 --
                 NB_CPU            : INTEGER := 1;
                 ENABLE_FPU        : INTEGER := 1;
-                FPU_NETLIST       : INTEGER := 1;
+                FPU_NETLIST       : INTEGER := 0;
                 ENABLE_DSU        : INTEGER := 1;
                 ENABLE_AHB_UART   : INTEGER := 1;
                 ENABLE_APB_UART   : INTEGER := 1;
                 ENABLE_IRQMP      : INTEGER := 1;
                 ENABLE_GPT        : INTEGER := 1;
                 --
                 NB_AHB_MASTER     : INTEGER := 1;
                 NB_AHB_SLAVE      : INTEGER := 1;
                 NB_APB_SLAVE      : INTEGER := 1;
                 --
-                ADDRESS_SIZE      : INTEGER := 20;
+                ADDRESS_SIZE      : INTEGER := 19;
-                USES_IAP_MEMCTRLR : INTEGER := 0;
+                USES_IAP_MEMCTRLR : INTEGER := 1;
                 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
                 SRBANKSZ          : INTEGER := 8
                 );
               PORT (
                 clk   : IN STD_ULOGIC;
                 reset : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT   apb_slv_in_type;
                 apbo_ext    : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT   ahb_slv_in_type;
                 ahbo_s_ext  : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT   AHB_Mst_In_Type;
                 ahbo_m_ext  : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
               CONSTANT CFG_CLKMUL    : INTEGER := (1);
               CONSTANT CFG_CLKDIV    : INTEGER := (1);  -- divide 50MHz by 2 to get 25MHz
               CONSTANT CFG_OCLKDIV   : INTEGER := (1);
               CONSTANT CFG_CLK_NOFB  : INTEGER := 0;
               -- LEON3 processor core
               CONSTANT CFG_LEON3     : INTEGER := 1;
               CONSTANT CFG_NCPU      : INTEGER := NB_CPU;
               CONSTANT CFG_NWIN      : INTEGER := (8);  -- to be compatible with BCC and RCC
               CONSTANT CFG_V8        : INTEGER := 0;
               CONSTANT CFG_MAC       : INTEGER := 0;
               CONSTANT CFG_SVT       : INTEGER := 0;
               CONSTANT CFG_RSTADDR   : INTEGER := 16#00000#;
               CONSTANT CFG_LDDEL     : INTEGER := (1);
               CONSTANT CFG_NWP       : INTEGER := (0);
               CONSTANT CFG_PWD       : INTEGER := 1*2;
               CONSTANT CFG_FPU       : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
               CONSTANT CFG_ICEN      : INTEGER := 1;
               CONSTANT CFG_ISETS     : INTEGER := 1;
               CONSTANT CFG_ISETSZ    : INTEGER := 4;
               CONSTANT CFG_ILINE     : INTEGER := 4;
               CONSTANT CFG_IREPL     : INTEGER := 0;
               CONSTANT CFG_ILOCK     : INTEGER := 0;
               CONSTANT CFG_ILRAMEN   : INTEGER := 0;
               CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
               CONSTANT CFG_ILRAMSZ   : INTEGER := 1;
               CONSTANT CFG_DCEN      : INTEGER := 1;
               CONSTANT CFG_DSETS     : INTEGER := 1;
               CONSTANT CFG_DSETSZ    : INTEGER := 4;
               CONSTANT CFG_DLINE     : INTEGER := 4;
               CONSTANT CFG_DREPL     : INTEGER := 0;
               CONSTANT CFG_DLOCK     : INTEGER := 0;
               CONSTANT CFG_DSNOOP    : INTEGER := 0 + 0 + 4*0;
               CONSTANT CFG_DLRAMEN   : INTEGER := 0;
               CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
               CONSTANT CFG_DLRAMSZ   : INTEGER := 1;
               CONSTANT CFG_MMUEN     : INTEGER := 0;
               CONSTANT CFG_ITLBNUM   : INTEGER := 2;
               CONSTANT CFG_DTLBNUM   : INTEGER := 2;
               CONSTANT CFG_TLB_TYPE  : INTEGER := 1 + 0*2;
               CONSTANT CFG_TLB_REP   : INTEGER := 1;
               CONSTANT CFG_DSU   : INTEGER := ENABLE_DSU;
               CONSTANT CFG_ITBSZ : INTEGER := 0;
               CONSTANT CFG_ATBSZ : INTEGER := 0;
               -- AMBA settings
               CONSTANT CFG_DEFMST  : INTEGER := (0);
               CONSTANT CFG_RROBIN  : INTEGER := 1;
               CONSTANT CFG_SPLIT   : INTEGER := 0;
               CONSTANT CFG_AHBIO   : INTEGER := 16#FFF#;
               CONSTANT CFG_APBADDR : INTEGER := 16#800#;
               -- DSU UART
               CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
               -- LEON2 memory controller
               CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
               -- UART 1
               CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
               CONSTANT CFG_UART1_FIFO   : INTEGER := 1;
               -- LEON3 interrupt controller
               CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
               -- Modular timer
               CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
               CONSTANT CFG_GPT_NTIM   : INTEGER := (2);
               CONSTANT CFG_GPT_SW     : INTEGER := (8);
               CONSTANT CFG_GPT_TW     : INTEGER := (32);
               CONSTANT CFG_GPT_IRQ    : INTEGER := (8);
               CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
               CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
               CONSTANT CFG_GPT_WDOG   : INTEGER := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
               CONSTANT maxahbmsp  : INTEGER            := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
               SIGNAL   clk2x      : STD_ULOGIC;
               SIGNAL   clkmn      : STD_ULOGIC;
               SIGNAL   clkm       : STD_ULOGIC;
               SIGNAL   rstn       : STD_ULOGIC;
               SIGNAL   rstraw     : STD_ULOGIC;
               SIGNAL   pciclk     : STD_ULOGIC;
               SIGNAL   sdclkl     : STD_ULOGIC;
               SIGNAL   cgi        : clkgen_in_type;
               SIGNAL   cgo        : clkgen_out_type;
               --- AHB / APB
               SIGNAL   apbi       : apb_slv_in_type;
               SIGNAL   apbo       : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL   ahbsi      : ahb_slv_in_type;
               SIGNAL   ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL   ahbmi      : ahb_mst_in_type;
               SIGNAL   ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
               SIGNAL   ahbuarti   : uart_in_type;
               SIGNAL   ahbuarto   : uart_out_type;
               SIGNAL   apbuarti   : uart_in_type;
               SIGNAL   apbuarto   : uart_out_type;
               --MEM CTRLR
               SIGNAL   memi       : memory_in_type;
               SIGNAL   memo       : memory_out_type;
               SIGNAL   wpo        : wprot_out_type;
               SIGNAL   sdo        : sdram_out_type;
               SIGNAL   mbe        : STD_LOGIC;      -- enable memory programming
               SIGNAL   mbe_drive  : STD_LOGIC;      -- drive the MBE memory signal
               SIGNAL   nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL   nSRAM_OE_s : STD_LOGIC;
               --IRQ
               SIGNAL   irqi       : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   irqo       : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
               SIGNAL   gpti       : gptimer_in_type;
               SIGNAL   gpto       : gptimer_out_type;
               --DSU
               SIGNAL   dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
               SIGNAL   dsui       : dsu_in_type;
               SIGNAL   dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
                 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
-                    u0 : ENTITY gaisler.leon3s                       -- LEON3 processor
+                    u0 : leon3s                       -- LEON3 processor
                       GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
 , CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
                                    CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
                                    CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                                    CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                                    CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
                       PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                                 irqi(i), irqo(i), dbgi(i), dbgo(i));
                   END GENERATE leon3_non_radhard;
                   leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
-                    cpu : ENTITY gaisler.leon3ft
+                    cpu : leon3ft
                       GENERIC MAP (
                         HINDEX     => i,  --: integer;             --CPU_HINDEX,
                         FABTECH    => fabtech,        --CFG_TECH,
                         MEMTECH    => memtech,        --CFG_TECH,
                         NWINDOWS   => CFG_NWIN,       --CFG_NWIN,
                         DSU        => CFG_DSU,        --condSel (HAS_DEBUG, 1, 0),
                         FPU        => CFG_FPU,        --CFG_FPU,
                         V8         => CFG_V8,         --CFG_V8,
                         CP         => 0,              --CFG_CP,
                         MAC        => CFG_MAC,        --CFG_MAC,
                         PCLOW      => pclow,          --CFG_PCLOW,
                         NOTAG      => 0,              --CFG_NOTAG,
                         NWP        => CFG_NWP,        --CFG_NWP,
                         ICEN       => CFG_ICEN,       --CFG_ICEN,
                         IREPL      => CFG_IREPL,      --CFG_IREPL,
                         ISETS      => CFG_ISETS,      --CFG_ISETS,
                         ILINESIZE  => CFG_ILINE,      --CFG_ILINE,
                         ISETSIZE   => CFG_ISETSZ,     --CFG_ISETSZ,
                         ISETLOCK   => CFG_ILOCK,      --CFG_ILOCK,
                         DCEN       => CFG_DCEN,       --CFG_DCEN,
                         DREPL      => CFG_DREPL,      --CFG_DREPL,
                         DSETS      => CFG_DSETS,      --CFG_DSETS,
                         DLINESIZE  => CFG_DLINE,      --CFG_DLINE,
                         DSETSIZE   => CFG_DSETSZ,     --CFG_DSETSZ,
                         DSETLOCK   => CFG_DLOCK,      --CFG_DLOCK,
                         DSNOOP     => CFG_DSNOOP,     --CFG_DSNOOP,
                         ILRAM      => CFG_ILRAMEN,    --CFG_ILRAMEN,
                         ILRAMSIZE  => CFG_ILRAMSZ,    --CFG_ILRAMSZ,
                         ILRAMSTART => CFG_ILRAMADDR,  --CFG_ILRAMADDR,
                         DLRAM      => CFG_DLRAMEN,    --CFG_DLRAMEN,
                         DLRAMSIZE  => CFG_DLRAMSZ,    --CFG_DLRAMSZ,
                         DLRAMSTART => CFG_DLRAMADDR,  --CFG_DLRAMADDR,
                         MMUEN      => CFG_MMUEN,      --CFG_MMUEN,
                         ITLBNUM    => CFG_ITLBNUM,    --CFG_ITLBNUM,
                         DTLBNUM    => CFG_DTLBNUM,    --CFG_DTLBNUM,
                         TLB_TYPE   => CFG_TLB_TYPE,   --CFG_TLB_TYPE,
                         TLB_REP    => CFG_TLB_REP,    --CFG_TLB_REP,
                         LDDEL      => CFG_LDDEL,      --CFG_LDDEL,
                         DISAS      => disas,          --condSel (SIM_ENABLED, 1, 0),
                         TBUF       => CFG_ITBSZ,      --CFG_ITBSZ,
                         PWD        => CFG_PWD,        --CFG_PWD,
                         SVT        => CFG_SVT,        --CFG_SVT,
                         RSTADDR    => CFG_RSTADDR,    --CFG_RSTADDR,
                         SMP        => CFG_NCPU-1,     --CFG_NCPU-1,
                         IUFT       => 2,  --: integer range 0 to 4;--CFG_IUFT_EN,
                         FPFT       => 1,  --: integer range 0 to 4;--CFG_FPUFT_EN,
                         CMFT       => 1,  --: integer range 0 to 1;--CFG_CACHE_FT_EN,
                         IUINJ      => 0,  --: integer;             --CFG_RF_ERRINJ,
                         CEINJ      => 0,  --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
                         CACHED     => 0,  --: integer;             --CFG_DFIXED,
                         NETLIST    => 0,  --: integer;             --CFG_LEON3_NETLIST,
                         SCANTEST   => 0,  --: integer;             --CFG_SCANTEST,
                         MMUPGSZ    => 0,  --: integer range 0 to 5;--CFG_MMU_PAGE,
                         BP         => 1)              --CFG_BP
                       PORT MAP (                      --
                         rstn  => rstn,                --rst_n,
                         clk   => clkm,                --clk,
                         ahbi  => ahbmi,               --ahbmi,
                         ahbo  => ahbmo(i),             --ahbmo(CPU_HINDEX),
                         ahbsi => ahbsi,               --ahbsi,
                         ahbso => ahbso,               --ahbso,
                         irqi  => irqi(i),             --irqi(CPU_HINDEX),
                         irqo  => irqo(i),             --irqo(CPU_HINDEX),
                         dbgi  => dbgi(i),             --dbgi(CPU_HINDEX),
                         dbgo  => dbgo(i),             --dbgo(CPU_HINDEX),
                         gclk  => clkm                 --clk
                         );
                   END GENERATE leon3_radhard_i;
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
                     GENERIC MAP (hindex => 0,       --      TODO : hindex => 2
                                  haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech,
                                  irq => 0, kbytes => CFG_ATBSZ)
                     PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),--      TODO :ahbso(2)
                               dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
                 ahbso(0)    <= ahbs_none;
                 dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
               ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
                 memctrlr : mctrl GENERIC MAP (
                   hindex  => 2,
                   pindex  => 0,
                   paddr   => 0,
                   srbanks => 1
                   )
                   PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
                 memi.bexcn <= '1';
                 memi.brdyn <= '1';
                 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.ramoen(0);
               END GENERATE;
               IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
                 memctrlr : srctrle_0ws
                   GENERIC MAP(
                     hindex   => 2,                  -- TODO : hindex   => 0
                     pindex   => 0,
                     paddr    => 0,
                     srbanks  => 2,
                     banksz   => SRBANKSZ,                  --512k * 32
                     rmw      => 1,
                     --Aeroflex memory generics:
                     mbpedac  => BYPASS_EDAC_MEMCTRLR,
                     mprog    => 1,          -- program memory by default values after reset
                     mpsrate  => 15,                 -- default scrub rate period
                     mpb2s    => 14,                  -- default busy to scrub delay
                     mpapb    => 1,                  -- instantiate apb register
                     mchipcnt => 2,
                     mpenall  => 1  -- when 0 program only E1 chip, else program all dies
                     )
                   PORT MAP (
                     rst       => rstn,
                     clk       => clkm,
                     ahbsi     => ahbsi,
                     ahbso     => ahbso(2),          -- TODO :ahbso(0),
                     apbi      => apbi,
                     apbo      => apbo(0),
                     sri       => memi,
                     sro       => memo,
                     --Aeroflex memory signals:
                     ucerr     => OPEN,              -- uncorrectable error signal
                     mbe       => mbe,               -- enable memory programming
                     mbe_drive => mbe_drive          -- drive the MBE memory signal
                     );
                 memi.brdyn <= nSRAM_READY;
                 mbe_pad : iopad
                   GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP(pad => SRAM_MBE,
                            i   => mbe,
                            en  => mbe_drive,
                            o   => memi.bexcn);
                 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.oen;
               END GENERATE;
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
               rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
               oen_pad  : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
               nBWE_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
               apbi_ext <= apbi;
               all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
                 max_16_apb : IF I + 5 < 16 GENERATE
                   apbo(I+5) <= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
               all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
                 max_16_ahbs : IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
               all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
                 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
             END Behavioral;

lib/lpp/lpp_spectral_matrix/MS_calculation.vhd +1 -6

             LIBRARY IEEE;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.general_purpose.ALL;
             ENTITY MS_calculation IS
               PORT (
                 clk               : IN  STD_LOGIC;
                 rstn              : IN  STD_LOGIC;
                 -- IN
                 fifo_in_data      : IN  STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
                 fifo_in_ren       : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 fifo_in_empty     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                 -- OUT
                 fifo_out_data     : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
                 fifo_out_wen      : OUT STD_LOGIC;
                 fifo_out_full     : IN  STD_LOGIC;
                 --
                 correlation_start : IN  STD_LOGIC;
                 correlation_auto  : IN  STD_LOGIC;  -- 1 => auto correlation / 0 => inter correlation
                 correlation_begin : OUT STD_LOGIC;
                 correlation_done  : OUT STD_LOGIC
                 );
             END MS_calculation;
             ARCHITECTURE beh OF MS_calculation IS
               TYPE   fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
               SIGNAL state : fsm_calculation_MS;
               SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
               CONSTANT ALU_CTRL_NOP  : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
               CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
               CONSTANT ALU_CTRL_MAC  : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
               CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
               SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
               CONSTANT select_ctrl_NOP  : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
               CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
               CONSTANT select_ctrl_MAC  : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
               CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
               SIGNAL select_op1 : STD_LOGIC;
               SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
               CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
               CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
               CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
               CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
               SIGNAL res_wen      : STD_LOGIC;
               SIGNAL res_wen_reg1 : STD_LOGIC;
               SIGNAL res_wen_reg2 : STD_LOGIC;
               --SIGNAL res_wen_reg3 : STD_LOGIC;
               SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
-              SIGNAL fifo_in_empty_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN
               --PROCESS (clk, rstn)
               --BEGIN  -- PROCESS
               --  IF rstn = '0' THEN                  -- asynchronous reset (active low)
               --    fifo_in_ren <= "11";
               --  ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
               --    fifo_in_ren <= fifo_in_ren_s;
               --  END IF;
               --END PROCESS;
               fifo_in_ren <= fifo_in_ren_s;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   correlation_begin <= '0';
                   correlation_done <= '0';
                   state       <= IDLE;
                   fifo_in_ren_s <= "11";
                   select_ctrl <= select_ctrl_NOP;
                   --ALU_CTRL    <= ALU_CTRL_NOP;
                   select_op1  <= select_R0(0);
                   select_op2  <= select_R0;
                   res_wen <= '1';
-                  fifo_in_empty_reg <= "11";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_ctrl <= select_ctrl_NOP;
                   --ALU_CTRL    <= ALU_CTRL_NOP;
                   correlation_begin <= '0';
                   fifo_in_ren_s <= "11";
                   res_wen <= '1';
                   correlation_done <= '0';
-                  fifo_in_empty_reg <= fifo_in_empty;
                   CASE state IS
                     WHEN IDLE =>
                       IF correlation_start = '1' THEN
                         IF correlation_auto = '1' THEN
                           IF fifo_out_full = '1' THEN
                             state <= WFa;
                           ELSE
                             correlation_begin <= '1';
                             state       <= S1a;
                             --fifo_in_ren_s <= "10";
                           END IF;
                         ELSE
                           IF fifo_out_full = '1' THEN
                             state <= WF;
                           ELSE
                             correlation_begin <= '1';
                             state       <= S1;
                             --fifo_in_ren_s <= "00";
                           END IF;
                         END IF;
                       END IF;
                       ---------------------------------------------------------------------
                       -- INTER CORRELATION
                       ---------------------------------------------------------------------
                     WHEN WF =>
                       IF fifo_out_full = '0' THEN
                         correlation_begin <= '1';
                         state       <= S1;
                         --fifo_in_ren_s <= "00";
                       END IF;
                     WHEN S1 =>
                       select_ctrl <= select_ctrl_MULT;
                       --ALU_CTRL    <= ALU_CTRL_MULT;
                       select_op1  <= select_R0(0);
                       select_op2  <= select_R1;
                       state <= S2;
                     WHEN S2 =>
                       select_ctrl <= select_ctrl_MAC;
                       --ALU_CTRL    <= ALU_CTRL_MAC;
                       select_op1  <= select_I0(0);
                       select_op2  <= select_I1;
                       res_wen     <= '0';
                       state <= S3;
                     WHEN S3 =>
                       select_ctrl <= select_ctrl_MULT;
                       --ALU_CTRL    <= ALU_CTRL_MULT;
                       select_op1    <= select_I0(0);
                       select_op2    <= select_R1;
                       fifo_in_ren_s <= fifo_in_empty;
                       state <= S4;
                     WHEN S4 =>
                       select_ctrl <= select_ctrl_MACn;
                       --ALU_CTRL    <= ALU_CTRL_MACn;
                       select_op1  <= select_R0(0);
                       select_op2  <= select_I1;
                       res_wen     <= '0';
                       IF fifo_in_empty = "00" THEN
                         state       <= S1;
             --            fifo_in_ren_s <= "00";
                       ELSE
                         correlation_done <= '1';
                         state <= IDLE;
                       END IF;
                       ---------------------------------------------------------------------
                       -- AUTO CORRELATION
                       ---------------------------------------------------------------------
                     WHEN WFa =>
                       IF fifo_out_full = '0' THEN
                         correlation_begin <= '1';
                         state               <= S1a;
                         --fifo_in_ren_s         <= "10";
                       END IF;
                     WHEN S1a =>
                       select_ctrl <= select_ctrl_MULT;
                       --ALU_CTRL    <= ALU_CTRL_MULT;
                       select_op1  <= select_R0(0);
                       select_op2  <= select_R0;
                       fifo_in_ren_s(0) <= fifo_in_empty(0);
                       state <= S2a;
                     WHEN S2a =>
                       select_ctrl <= select_ctrl_MAC;
                       --ALU_CTRL    <= ALU_CTRL_MAC;
                       select_op1  <= select_I0(0);
                       select_op2  <= select_I0;
                       res_wen     <= '0';
                       IF fifo_in_empty(0) = '0' THEN
                         state       <= S1a;
                         --fifo_in_ren_s <= "10";
                       ELSE
                         correlation_done <= '1';
                         state <= IDLE;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               ALU_CTRL <= ALU_CTRL_NOP  WHEN select_ctrl = select_ctrl_NOP  ELSE
                           ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
                           ALU_CTRL_MAC  WHEN select_ctrl = select_ctrl_MAC  ELSE
                           ALU_CTRL_MACn;
               OP1 <= fifo_in_data(15 DOWNTO  0) WHEN select_op1 = select_R0(0) ELSE
                      fifo_in_data(31 DOWNTO 16);  -- WHEN select_op1 = select_I0(0) ELSE
               OP2 <= fifo_in_data(15 DOWNTO  0) WHEN select_op2 = select_R0 ELSE
                      fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
                      fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
                      fifo_in_data(63 DOWNTO 48);  -- WHEN select_op2 = select_I1 ELSE
               ALU_MS : ALU
                 GENERIC MAP (
                   Arith_en   => 1,
                   Logic_en   => 0,
                   Input_SZ_1 => 16,
                   Input_SZ_2 => 16,
                   COMP_EN    => 0)                  -- 0> Enable  and 1> Disable
                 PORT MAP (
                   clk   => clk,
                   reset => rstn,
                   ctrl => ALU_CTRL(2 DOWNTO 0),
                   comp => ALU_CTRL(4 DOWNTO 3),
                   OP1 => OP1,
                   OP2 => OP2,
                   RES => RES);
               fifo_out_data <= RES;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   res_wen_reg1 <= '1';
                   res_wen_reg2 <= '1';
                   --res_wen_reg3 <= '1';
                   fifo_out_wen <= '1';
                 ELSIF clk'event AND clk = '1' THEN
                   res_wen_reg1 <= res_wen;
                   res_wen_reg2 <= res_wen_reg1;
                   --res_wen_reg3 <= res_wen_reg2;
                   fifo_out_wen <= res_wen_reg2;
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +9 -12

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 tech                   : INTEGER := inferred;
-                nb_data_by_buffer_size : INTEGER := 11;
+                nb_data_by_buffer_size : INTEGER := 32;
-                nb_snapshot_param_size : INTEGER := 11;
+                nb_snapshot_param_size : INTEGER := 32;
-                delta_vector_size      : INTEGER := 20;
+                delta_vector_size      : INTEGER := 32;
                 delta_vector_size_f0_2 : INTEGER := 7;
-                pindex   : INTEGER := 4;
+                pindex   : INTEGER := 15;
-                paddr    : INTEGER := 4;
+                paddr    : INTEGER := 15;
                 pmask    : INTEGER := 16#fff#;
-                pirq_ms  : INTEGER := 0;
+                pirq_ms  : INTEGER := 6;
-                pirq_wfp : INTEGER := 1;
+                pirq_wfp : INTEGER := 14;
                 hindex : INTEGER := 2;
-                top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
+                top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
                 DEBUG_FORCE_DATA_DMA : INTEGER := 0
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               SIGNAL data_shaping_R2  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
-              SIGNAL sample_f_val       : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL sample_f_data      : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
-              --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
             --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
             --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL length_matrix_f0         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f1         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f2         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               -- WFP
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               --SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
             --  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
             --  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
             --  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
             --  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL wfp_error_buffer_full   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
             --  SIGNAL dma_sel_valid   : STD_LOGIC;
             --  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
             --  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
             --  SIGNAL ongoing_reg         : STD_LOGIC;
             --  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_send_reg        : STD_LOGIC;
             --  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
             --  SIGNAL dma_send        : STD_LOGIC;
             --  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_done        : STD_LOGIC;
             --  SIGNAL dma_ren         : STD_LOGIC;
             --  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
             --  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_valid       : STD_LOGIC;
             --  SIGNAL data_ms_valid_burst : STD_LOGIC;
             --  SIGNAL data_ms_ren         : STD_LOGIC;
             --  SIGNAL data_ms_done        : STD_LOGIC;
             --  SIGNAL dma_ms_ongoing      : STD_LOGIC;
             --  SIGNAL run_ms              : STD_LOGIC;
             --  SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full      : STD_LOGIC;
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
             --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_fifo_data        : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_data_debug  : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_ren         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_new       : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_addr      : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_buffer_length    : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
               SIGNAL dma_buffer_full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_grant_error      : STD_LOGIC;
               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_time        :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f0_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f1_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f2_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f3_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               --apb_reg_debug_vector;
               -----------------------------------------------------------------------------
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               sample_time <= coarse_time & fine_time;
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   sample_time      => sample_time,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   data_shaping_R2  => data_shaping_R2,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data,
                   sample_f0_time   => sample_f0_time,
                   sample_f1_time   => sample_f1_time,
                   sample_f2_time   => sample_f2_time,
                   sample_f3_time   => sample_f3_time
                   );
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
             --      nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => OPEN,--run_ms,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,       -- TODO
                   error_input_fifo_write => error_input_fifo_write,  -- TODO
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   length_matrix_f0  => length_matrix_f0,
                   length_matrix_f1  => length_matrix_f1,
                   length_matrix_f2  => length_matrix_f2,
                   -------------------------------------------------------------------------
                   --status_full       => status_full,       --      TODo
                   --status_full_ack   => status_full_ack,   --      TODo
                   --status_full_err   => status_full_err,   --      TODo
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   data_shaping_R2   => data_shaping_R2,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
             --      nb_word_by_buffer => nb_word_by_buffer, -- TODO
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => OPEN, --run,
                   start_date        => start_date,
             --      debug_signal      => debug_signal,
                   wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
                   wfp_addr_buffer         => wfp_addr_buffer,-- TODO
                   wfp_length_buffer       => wfp_length_buffer,-- TODO
                   wfp_ready_buffer        => wfp_ready_buffer,-- TODO
                   wfp_buffer_time         => wfp_buffer_time,-- TODO
                   wfp_error_buffer_full   => wfp_error_buffer_full, -- TODO
                   -------------------------------------------------------------------------
                   sample_f3_v     => sample_f3_data(1*16-1 DOWNTO 0*16),
                   sample_f3_e1    => sample_f3_data(2*16-1 DOWNTO 1*16),
                   sample_f3_e2    => sample_f3_data(3*16-1 DOWNTO 2*16),
                   sample_f3_valid => sample_f3_val,
                   debug_vector => apb_reg_debug_vector
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => tech,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => '1',--run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_new_err    => status_new_err,
                   status_buffer_ready => wfp_status_buffer_ready,
                   addr_buffer         => wfp_addr_buffer,
                   length_buffer       => wfp_length_buffer,
                   ready_buffer        => wfp_ready_buffer,
                   buffer_time         => wfp_buffer_time,
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
             --      fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
                   data_f0_time                 => sample_f0_time,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
                   data_f1_time                 => sample_f1_time,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
                   data_f2_time                 => sample_f2_time,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
                   data_f3_time                 => sample_f3_time,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   dma_fifo_data        => dma_fifo_data(32*4-1 DOWNTO 0),
                   dma_fifo_ren         => dma_fifo_ren(3 DOWNTO 0),
                   dma_buffer_new       => dma_buffer_new(3 DOWNTO 0),
                   dma_buffer_addr      => dma_buffer_addr(32*4-1 DOWNTO 0),
                   dma_buffer_length    => dma_buffer_length(26*4-1 DOWNTO 0),
                   dma_buffer_full      => dma_buffer_full(3 DOWNTO 0),
                   dma_buffer_full_err  => dma_buffer_full_err(3 DOWNTO 0)
                   );
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
                                NOT(sample_f2_val) & NOT(sample_f2_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               --ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   --rstn => ms_softandhard_rstn,      --rstn,
                   rstn => rstn,
                   run  => '1',--run_ms,
                   start_date => start_date,
                   coarse_time => coarse_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f0_time  => sample_f0_time,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f1_time  => sample_f1_time,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
                   sample_f2_time  => sample_f2_time,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   dma_fifo_data        => dma_fifo_data((4+1)*32-1 DOWNTO 4*32),    -- OUT
                   dma_fifo_ren         => dma_fifo_ren(4),                          -- IN
                   dma_buffer_new       => dma_buffer_new(4),                        -- OUT
                   dma_buffer_addr      => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32),  -- OUT
                   dma_buffer_length    => dma_buffer_length((4+1)*26-1 DOWNTO 4*26),  -- OUT
                   dma_buffer_full      => dma_buffer_full(4),                       -- IN
                   dma_buffer_full_err  => dma_buffer_full_err(4),                   -- IN
                   --REG
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0 => length_matrix_f0,
                   length_matrix_f1 => length_matrix_f1,
                   length_matrix_f2 => length_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   debug_vector   => debug_vector_ms);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   dma_fifo_data_forced_gen <= X"00040003";
                 ELSIF clk'event AND clk = '1' THEN
                   IF dma_fifo_ren(0) = '0' THEN
                     CASE dma_fifo_data_forced_gen IS
                       WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
                       WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
                       WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
                       WHEN OTHERS => NULL;
                     END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
               dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
               dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
               dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
               dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
               dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
               DMA_SubSystem_1 : DMA_SubSystem
                 GENERIC MAP (
                   hindex     => hindex,
                   CUSTOM_DMA => 1)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_dma,
                   ahbi => ahbi,
                   ahbo => ahbo,
                   fifo_burst_valid => dma_fifo_burst_valid,  --fifo_burst_valid,
                   fifo_data        => dma_fifo_data_debug,         --fifo_data,
                   fifo_ren         => dma_fifo_ren,          --fifo_ren,
                   buffer_new      => dma_buffer_new,       --buffer_new,
                   buffer_addr     => dma_buffer_addr,      --buffer_addr,
                   buffer_length   => dma_buffer_length,    --buffer_length,
                   buffer_full     => dma_buffer_full,      --buffer_full,
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error,
                   debug_vector    => debug_vector(8 DOWNTO 0)
                   );     --grant_error);
               -----------------------------------------------------------------------------
               -- OBSERVATION for SIMULATION
               all_channel_sim: FOR I IN 0 TO 5 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     sample_f0_data_sim(I) <= (OTHERS => '0');
                     sample_f1_data_sim(I) <= (OTHERS => '0');
                     sample_f2_data_sim(I) <= (OTHERS => '0');
                     sample_f3_data_sim(I) <= (OTHERS => '0');
                   ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                     IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_channel_sim;
               -----------------------------------------------------------------------------
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lpp_waveform/lpp_waveform.vhd +478 -485

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	@@ -1,485 +1,478
	1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com	21	-- jean-christophe.pellion@easii-ic.com
	22	-------------------------------------------------------------------------------	22	-------------------------------------------------------------------------------
	23	LIBRARY IEEE;	23	LIBRARY IEEE;
	24	USE IEEE.STD_LOGIC_1164.ALL;	24	USE IEEE.STD_LOGIC_1164.ALL;
	25	USE ieee.numeric_std.ALL;	25	USE ieee.numeric_std.ALL;
	26		26
	27	LIBRARY grlib;	27	LIBRARY grlib;
	28	USE grlib.amba.ALL;	28	USE grlib.amba.ALL;
	29	USE grlib.stdlib.ALL;	29	USE grlib.stdlib.ALL;
	30	USE grlib.devices.ALL;	30	USE grlib.devices.ALL;
	31	USE GRLIB.DMA2AHB_Package.ALL;	31	USE GRLIB.DMA2AHB_Package.ALL;
	32		32
	33	LIBRARY lpp;	33	LIBRARY lpp;
	34	USE lpp.lpp_waveform_pkg.ALL;	34	USE lpp.lpp_waveform_pkg.ALL;
	35	USE lpp.iir_filter.ALL;	35	USE lpp.iir_filter.ALL;
	36	USE lpp.lpp_memory.ALL;	36	USE lpp.lpp_memory.ALL;
	37		37
	38	LIBRARY techmap;	38	LIBRARY techmap;
	39	USE techmap.gencomp.ALL;	39	USE techmap.gencomp.ALL;
	40		40
	41	ENTITY lpp_waveform IS	41	ENTITY lpp_waveform IS
	42		42
	43	GENERIC (	43	GENERIC (
	44	tech : INTEGER := inferred;	44	tech : INTEGER := inferred;
	45	data_size : INTEGER := 96; --16*6	45	data_size : INTEGER := 96; --16*6
	46	nb_data_by_buffer_size : INTEGER := 11;	46	nb_data_by_buffer_size : INTEGER := 11;
	47	-- nb_word_by_buffer_size : INTEGER := 11;	47	-- nb_word_by_buffer_size : INTEGER := 11;
	48	nb_snapshot_param_size : INTEGER := 11;	48	nb_snapshot_param_size : INTEGER := 11;
	49	delta_vector_size : INTEGER := 20;	49	delta_vector_size : INTEGER := 20;
	50	delta_vector_size_f0_2 : INTEGER := 3);	50	delta_vector_size_f0_2 : INTEGER := 3);
	51		51
	52	PORT (	52	PORT (
	53	clk : IN STD_LOGIC;	53	clk : IN STD_LOGIC;
	54	rstn : IN STD_LOGIC;	54	rstn : IN STD_LOGIC;
	55		55
	56	---- AMBA AHB Master Interface	56	---- AMBA AHB Master Interface
	57	--AHB_Master_In : IN AHB_Mst_In_Type; -- TODO	57	--AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
	58	--AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO	58	--AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
	59		59
	60	--config	60	--config
	61	reg_run : IN STD_LOGIC;	61	reg_run : IN STD_LOGIC;
	62	reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);	62	reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
	63	reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	63	reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	64	reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	64	reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	65	reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);	65	reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
	66	reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	66	reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	67	reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	67	reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
	68		68
	69	enable_f0 : IN STD_LOGIC;	69	enable_f0 : IN STD_LOGIC;
	70	enable_f1 : IN STD_LOGIC;	70	enable_f1 : IN STD_LOGIC;
	71	enable_f2 : IN STD_LOGIC;	71	enable_f2 : IN STD_LOGIC;
	72	enable_f3 : IN STD_LOGIC;	72	enable_f3 : IN STD_LOGIC;
	73		73
	74	burst_f0 : IN STD_LOGIC;	74	burst_f0 : IN STD_LOGIC;
	75	burst_f1 : IN STD_LOGIC;	75	burst_f1 : IN STD_LOGIC;
	76	burst_f2 : IN STD_LOGIC;	76	burst_f2 : IN STD_LOGIC;
	77		77
	78	nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);	78	nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
	79	-- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);	79	-- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
	80	nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);	80	nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
	81		81
	82	status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma	82	status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
	83		83
	84		84
	85	-- REG DMA	85	-- REG DMA
	86	status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	86	status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	87	addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);	87	addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
	88	length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);	88	length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
	89		89
	90	ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	90	ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	91	buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	91	buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	92	error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	92	error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	93		93
	94	---------------------------------------------------------------------------	94	---------------------------------------------------------------------------
	95	-- INPUT	95	-- INPUT
	96	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	96	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	97	-- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);	97	-- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	98		98
	99	--f0	99	--f0
	100	data_f0_in_valid : IN STD_LOGIC;	100	data_f0_in_valid : IN STD_LOGIC;
	101	data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	101	data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	102	data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	102	data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	103	--f1	103	--f1
	104	data_f1_in_valid : IN STD_LOGIC;	104	data_f1_in_valid : IN STD_LOGIC;
	105	data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	105	data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	106	data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	106	data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	107	--f2	107	--f2
	108	data_f2_in_valid : IN STD_LOGIC;	108	data_f2_in_valid : IN STD_LOGIC;
	109	data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	109	data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	110	data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	110	data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	111	--f3	111	--f3
	112	data_f3_in_valid : IN STD_LOGIC;	112	data_f3_in_valid : IN STD_LOGIC;
	113	data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	113	data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	114	data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);	114	data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	115		115
	116	---------------------------------------------------------------------------	116	---------------------------------------------------------------------------
	117	-- DMA --------------------------------------------------------------------	117	-- DMA --------------------------------------------------------------------
	118		118
	119	dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	119	dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	120	dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);	120	dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
	121	dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	121	dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	122	dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	122	dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	123	dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);	123	dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
	124	dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);	124	dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
	125	dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);	125	dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	126	dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)	126	dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
	127		127
	128	);	128	);
	129		129
	130	END lpp_waveform;	130	END lpp_waveform;
	131		131
	132	ARCHITECTURE beh OF lpp_waveform IS	132	ARCHITECTURE beh OF lpp_waveform IS
	133	SIGNAL start_snapshot_f0 : STD_LOGIC;	133	SIGNAL start_snapshot_f0 : STD_LOGIC;
	134	SIGNAL start_snapshot_f1 : STD_LOGIC;	134	SIGNAL start_snapshot_f1 : STD_LOGIC;
	135	SIGNAL start_snapshot_f2 : STD_LOGIC;	135	SIGNAL start_snapshot_f2 : STD_LOGIC;
	136		136
	137	SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	137	SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	138	SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	138	SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	139	SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	139	SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	140	SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	140	SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	141		141
	142	SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	142	SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	143	SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	143	SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	144	SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	144	SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	145	SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);	145	SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
	146		146
	147	SIGNAL data_f0_out_valid : STD_LOGIC;	147	SIGNAL data_f0_out_valid : STD_LOGIC;
	148	SIGNAL data_f1_out_valid : STD_LOGIC;	148	SIGNAL data_f1_out_valid : STD_LOGIC;
	149	SIGNAL data_f2_out_valid : STD_LOGIC;	149	SIGNAL data_f2_out_valid : STD_LOGIC;
	150	SIGNAL data_f3_out_valid : STD_LOGIC;	150	SIGNAL data_f3_out_valid : STD_LOGIC;
	151	SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);	151	SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
	152	--	152	--
	153	SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);	153	SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
	154	SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);	154	SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
	155	SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);	155	SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
	156	SIGNAL ~~time_ready~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	156	SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
	157	SIGNAL ~~data_ready~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	157	SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	158	SIGNAL ~~ready_arb~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	158	SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
	159	SIGNAL ~~data_wen~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	159	SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
	160	SIGNAL ~~time_wen~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	160	SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
	161	SIGNAL ~~wdata~~ : STD_LOGIC_VECTOR(31 DOWNTO 0);	161	SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
	162	SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);	162	--
	163	SIGNAL ~~full~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	163	SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
	164	SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);	164	--
	165	SIGNAL ~~empty~~ : STD_LOGIC~~_VECTOR~~(3 ~~DOWNTO~~ 0);	165	SIGNAL run : STD_LOGIC;
	166	--	166	--
	167	SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);	167	TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
	168	SIGNAL ~~time_ren~~ : ~~STD_LOGIC_VECTOR~~(3 DOWNTO 0);	168	SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
	169	SIGNAL ~~rdata~~ : ~~STD_LOGIC_VECTOR~~(31 DOWNTO 0);	169	SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
	170	SIGNAL ~~enable~~ : ~~STD_LOGIC~~_VECTOR(3 DOWNTO 0);	170	SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
	171	--	171	SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
	172	SIGNAL ~~run~~ : STD_LOGIC;	172	SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	173	--	173	SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	174	TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);	174	--
	175	SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);	175
	176	SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);	176	SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
	177	SIGNAL ~~time_out~~ : ~~TIME~~_VECTOR(3 DOWNTO 0);	177	SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
	178	SIGNAL ~~time_out_debug~~ : ~~TIME~~_VECTOR(3 DOWNTO 0); ~~-- TODO : debug~~	178	SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
	179	SIGNAL ~~time_reg1~~ : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	179	-- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	180	SIGNAL ~~time_reg2~~ : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	180	SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
	181	--	181
	182		182	--
	183	SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b	183	SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
	184	SIGNAL ~~s_empty~~ : STD_LOGIC_VECTOR(3 DOWNTO 0);	184	SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
	185	SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);	185
	186	-- SIGNAL ~~s_rdata~~ : STD_LOGIC_VECTOR(31 DOWNTO 0);	186	SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	187	SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);	187
	188		188	SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
	189	--	189
	190	SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);	190	BEGIN -- beh
	191	SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);	191
	192		192	-----------------------------------------------------------------------------
	193	SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	193
	194		194	lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
	195	SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);	195	GENERIC MAP (
	196		196	delta_vector_size => delta_vector_size,
	197	BEGIN -- beh	197	delta_vector_size_f0_2 => delta_vector_size_f0_2
	198		198	)
	199	-----------------------------------------------------------------------------	199	PORT MAP (
	200		200	clk => clk,
	201	lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler	201	rstn => rstn,
	202	GENERIC MAP (	202	reg_run => reg_run,
	203	delta_vector_size => delta_vector_size,	203	reg_start_date => reg_start_date,
	204	delta_vector_size_f0_2 => delta_vector_size_f0_2	204	reg_delta_snapshot => reg_delta_snapshot,
	205	)	205	reg_delta_f0 => reg_delta_f0,
	206	PORT MAP (	206	reg_delta_f0_2 => reg_delta_f0_2,
	207	clk => clk,	207	reg_delta_f1 => reg_delta_f1,
	208	rstn => rstn,	208	reg_delta_f2 => reg_delta_f2,
	209	reg_run => reg_run,	209	coarse_time => coarse_time(30 DOWNTO 0),
	210	reg_start_date => reg_start_date,	210	data_f0_valid => data_f0_in_valid,
	211	reg_delta_snapshot => reg_delta_snapshot,	211	data_f2_valid => data_f2_in_valid,
	212	reg_delta_f0 => reg_delta_f0,	212	start_snapshot_f0 => start_snapshot_f0,
	213	reg_delta_f0_2 => reg_delta_f0_2,	213	start_snapshot_f1 => start_snapshot_f1,
	214	reg_delta_f1 => reg_delta_f1,	214	start_snapshot_f2 => start_snapshot_f2,
	215	reg_delta_f2 => reg_delta_f2,	215	wfp_on => run);
	216	coarse_time => coarse_time(30 DOWNTO 0),	216
	217	data_f0_valid => data_f0_in_valid,	217	lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
	218	data_f2_valid => data_f2_in_valid,	218	GENERIC MAP (
	219	start_snapshot_f0 => start_snapshot_f0,	219	data_size => data_size,
	220	start_snapshot_f1 => start_snapshot_f1,	220	nb_snapshot_param_size => nb_snapshot_param_size)
	221	start_snapshot_f2 => start_snapshot_f2,	221	PORT MAP (
	222	~~wfp_on~~ => ~~run~~);	222	clk => clk,
	223		223	rstn => rstn,
	224	lpp_waveform_snapshot_f0 : lpp_waveform_snapshot	224	run => run,
	225	GENERIC MAP (	225	enable => enable_f0,
	226	data_size => data_size,	226	burst_enable => burst_f0,
	227	nb_snapshot_param~~_size~~ => nb_snapshot_param~~_size~~)	227	nb_snapshot_param => nb_snapshot_param,
	228	PORT MAP (	228	start_snapshot => start_snapshot_f0,
	229	~~clk~~ => ~~clk~~,	229	data_in => data_f0_in,
	230	rstn => rstn,	230	data_in_valid => data_f0_in_valid,
	231	~~run~~ => ~~run~~,	231	data_out => data_f0_out,
	232	enable => enable_f0,	232	data_out_valid => data_f0_out_valid);
	233	burst_enable => burst_f0,	233
	234	nb_snapshot_param => nb_snapshot_param,	234	nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
	235	start_snapshot => start_snapshot_f0,	235
	236	data_in => data_f0_in,	236	lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
	237	data_in_valid => data_f0_in_valid,	237	GENERIC MAP (
	238	data_~~out~~ => data_~~f0_out~~,	238	data_size => data_size,
	239	data_out_valid => data_f0_out_valid);	239	nb_snapshot_param_size => nb_snapshot_param_size+1)
	240		240	PORT MAP (
	241	nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;	241	clk => clk,
	242		242	rstn => rstn,
	243	lpp_waveform_snapshot_f1 : lpp_waveform_snapshot	243	run => run,
	244	GENERIC MAP (	244	enable => enable_f1,
	245	data_size => data_size,	245	burst_enable => burst_f1,
	246	nb_snapshot_param~~_size~~ => nb_snapshot_param_~~size~~+1)	246	nb_snapshot_param => nb_snapshot_param_more_one,
	247	PORT MAP (	247	start_snapshot => start_snapshot_f1,
	248	~~clk~~ => ~~clk~~,	248	data_in => data_f1_in,
	249	rstn => rstn,	249	data_in_valid => data_f1_in_valid,
	250	~~run~~ => ~~run~~,	250	data_out => data_f1_out,
	251	enable => enable_f1,	251	data_out_valid => data_f1_out_valid);
	252	burst_enable => burst_f1,	252
	253	nb_snapshot_param => nb_snapshot_param_more_one,	253	lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
	254	start_snapshot => start_snapshot_f1,	254	GENERIC MAP (
	255	data_in => data_~~f1_in~~,	255	data_size => data_size,
	256	data_in_valid => data_f1_in_valid,	256	nb_snapshot_param_size => nb_snapshot_param_size+1)
	257	data_out => data_f1_out,	257	PORT MAP (
	258	data_out_valid => data_f1_out_valid);	258	clk => clk,
	259		259	rstn => rstn,
	260	lpp_waveform_snapshot_f2 : lpp_waveform_snapshot	260	run => run,
	261	GENERIC MAP (	261	enable => enable_f2,
	262	data_size => data_size,	262	burst_enable => burst_f2,
	263	nb_snapshot_param~~_size~~ => nb_snapshot_param_~~size~~+1)	263	nb_snapshot_param => nb_snapshot_param_more_one,
	264	PORT MAP (	264	start_snapshot => start_snapshot_f2,
	265	~~clk~~ => ~~clk~~,	265	data_in => data_f2_in,
	266	rstn => rstn,	266	data_in_valid => data_f2_in_valid,
	267	~~run~~ => ~~run~~,	267	data_out => data_f2_out,
	268	enable => enable_f2,	268	data_out_valid => data_f2_out_valid);
	269	burst_enable => burst_f2,	269
	270	nb_snapshot_param => nb_snapshot_param_more_one,	270	lpp_waveform_burst_f3 : lpp_waveform_burst
	271	start_snapshot => start_snapshot_f2,	271	GENERIC MAP (
	272	data_in => data_~~f2_in~~,	272	data_size => data_size)
	273	data_in_valid => data_f2_in_valid,	273	PORT MAP (
	274	data_out => data_f2_out,	274	clk => clk,
	275	data_out_valid => data_f2_out_valid);	275	rstn => rstn,
	276		276	run => run,
	277	lpp_waveform_burst_f3 : lpp_waveform_burst	277	enable => enable_f3,
	278	GENERIC MAP (	278	data_in => data_f3_in,
	279	data_~~size~~ => data_~~size~~)	279	data_in_valid => data_f3_in_valid,
	280	PORT MAP (	280	data_out => data_f3_out,
	281	clk => clk,	281	data_out_valid => data_f3_out_valid);
	282	rstn => rstn,	282
	283	run => run,	283	-----------------------------------------------------------------------------
	284	enable => enable_f3,	284	-- DEBUG -- SNAPSHOT OUT
	285	data_in => data_f3_in,	285	--debug_f0_data_valid <= data_f0_out_valid;
	286	data_in_valid => data_f3_in_valid,	286	--debug_f0_data <= data_f0_out;
	287	data_out => data_f3_out,	287	--debug_f1_data_valid <= data_f1_out_valid;
	288	data_out_valid => data_f3_out_valid);	288	--debug_f1_data <= data_f1_out;
	289		289	--debug_f2_data_valid <= data_f2_out_valid;
	290	-----------------------------------------------------------------------------	290	--debug_f2_data <= data_f2_out;
	291	-- DEBUG -- SNAPSHOT OUT	291	--debug_f3_data_valid <= data_f3_out_valid;
	292	--debug_f~~0_data_valid <= data_f0_out_valid~~;	292	--debug_f3_data <= data_f3_out;
	293	--debug_f0_data <= data_f0_out;	293	-----------------------------------------------------------------------------
	294	--debug_f1_data_valid <= data_f1_out_valid;	294
	295	--debug_f1_data <= data_f1_out;	295	PROCESS (clk, rstn)
	296	--debug_f2_data_valid <= data_f2_out_valid;	296	BEGIN -- PROCESS
	297	--debug_f2_data <= data_f2_out;	297	IF rstn = '0' THEN -- asynchronous reset (active low)
	298	--debug_f3_data_valid <= data_f3_out_valid;	298	time_reg1 <= (OTHERS => '0');
	299	--debug_f3_data <= data_f3_out;	299	time_reg2 <= (OTHERS => '0');
	300	-----------------------------------------------------------------------------	300	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	301		301	time_reg1(481-1 DOWNTO 480) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
	302	PROCESS (clk, rstn)	302	time_reg1(482-1 DOWNTO 481) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
	303	BEGIN -- PROCESS	303	time_reg1(483-1 DOWNTO 482) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
	304	IF rstn = '0' THEN -- asynchronous reset (active low)	304	time_reg1(484-1 DOWNTO 483) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
	305	time_reg1 <= (OTHERS => '0');	305	time_reg2 <= time_reg1;
	306	time_reg2 <= (OTHERS => '0');	306	END IF;
	307	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge	307	END PROCESS;
	308	time_reg1(481-1 DOWNTO 480) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);	308
	309	time_reg1(482-1 DOWNTO 481) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);	309	valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
	310	time_reg1(483-1 DOWNTO 482) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);	310	all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
	311	time_reg1(484-1 DOWNTO 483) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);	311	lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
	312	time_reg2 <= time_reg1;	312	PORT MAP (
	313	END IF;	313	HCLK => clk,
	314	END PROCESS;	314	HRESETn => rstn,
	315		315	run => run,
	316	valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;	316	valid_in => valid_in(I),
	317	all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE	317	ack_in => valid_ack(I),
	318	lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid	318	time_in => time_reg2(48(I+1)-1 DOWNTO 48I), -- Todo
	319	PORT MAP (	319	valid_out => valid_out(I),
	320	HCLK => clk,	320	time_out => time_out(I), -- Todo
	321	HRESETn => rstn,	321	error => status_new_err(I));
	322	run => run,	322	END GENERATE all_input_valid;
	323	valid_in => valid_in(I),	323
	324	ack_in => valid_ack(I),	324	data_f0_out_swap <= data_f0_out((165)-1 DOWNTO 164) &
	325	time_in => time_reg2(48(I+1)-1 DOWNTO 48I), -- Todo	325	data_f0_out((166)-1 DOWNTO 165) &
	326	valid_out => valid_out(I),	326	data_f0_out((163)-1 DOWNTO 162) &
	327	time_out => time_out(I), -- Todo	327	data_f0_out((164)-1 DOWNTO 163) &
	328	error => status_new_err(I));	328	data_f0_out((161)-1 DOWNTO 160) &
	329	END GENERATE all_input_valid;	329	data_f0_out((162)-1 DOWNTO 161) ;
	330		330
	331	data_f0_out_swap <= data_f0_out((165)-1 DOWNTO 164) &	331	data_f1_out_swap <= data_f1_out((165)-1 DOWNTO 164) &
	332	data_f0_out((166)-1 DOWNTO 165) &	332	data_f1_out((166)-1 DOWNTO 165) &
	333	data_f0_out((163)-1 DOWNTO 162) &	333	data_f1_out((163)-1 DOWNTO 162) &
	334	data_f0_out((164)-1 DOWNTO 163) &	334	data_f1_out((164)-1 DOWNTO 163) &
	335	data_f0_out((161)-1 DOWNTO 160) &	335	data_f1_out((161)-1 DOWNTO 160) &
	336	data_f0_out((162)-1 DOWNTO 161) ;	336	data_f1_out((162)-1 DOWNTO 161) ;
	337		337
	338	data_f1_out_swap <= data_f1_out((165)-1 DOWNTO 164) &	338	data_f2_out_swap <= data_f2_out((165)-1 DOWNTO 164) &
	339	data_f1_out((166)-1 DOWNTO 165) &	339	data_f2_out((166)-1 DOWNTO 165) &
	340	data_f1_out((163)-1 DOWNTO 162) &	340	data_f2_out((163)-1 DOWNTO 162) &
	341	data_f1_out((164)-1 DOWNTO 163) &	341	data_f2_out((164)-1 DOWNTO 163) &
	342	data_f1_out((161)-1 DOWNTO 160) &	342	data_f2_out((161)-1 DOWNTO 160) &
	343	data_f1_out((162)-1 DOWNTO 161) ;	343	data_f2_out((162)-1 DOWNTO 161) ;
	344		344
	345	data_f2_out_swap <= data_f2_out((165)-1 DOWNTO 164) &	345	data_f3_out_swap <= data_f3_out((165)-1 DOWNTO 164) &
	346	data_f2_out((166)-1 DOWNTO 165) &	346	data_f3_out((166)-1 DOWNTO 165) &
	347	data_f2_out((163)-1 DOWNTO 162) &	347	data_f3_out((163)-1 DOWNTO 162) &
	348	data_f2_out((164)-1 DOWNTO 163) &	348	data_f3_out((164)-1 DOWNTO 163) &
	349	data_f2_out((161)-1 DOWNTO 160) &	349	data_f3_out((161)-1 DOWNTO 160) &
	350	data_f2_out((162)-1 DOWNTO 161) ;	350	data_f3_out((162)-1 DOWNTO 161) ;
	351		351
	352	data_f3_out_swap <= data_f3_out((165)-1 DOWNTO 164) &	352	all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
	353	data_f3_out((166)-1 DOWNTO 165) &	353	data_out(0, I) <= data_f0_out_swap(I);
	354	data_f3_out((163)-1 DOWNTO 162) &	354	data_out(1, I) <= data_f1_out_swap(I);
	355	data_f3_out((164)-1 DOWNTO 163) &	355	data_out(2, I) <= data_f2_out_swap(I);
	356	data_f3_out((161)-1 DOWNTO 160) &	356	data_out(3, I) <= data_f3_out_swap(I);
	357	data_f3_out((162)-1 DOWNTO 161) ;	357	END GENERATE all_bit_of_data_out;
	358		358
	359	all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE	359	-----------------------------------------------------------------------------
	360	data_out(0, I) <= data_f0_out_swap(I);	360	-- TODO : debug
	361	data_out(1, I) <= data_f1_out_swap(I);	361	-----------------------------------------------------------------------------
	362	data_out(2, I) <= data_f2_out_swap(I);	362	all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
	363	data_out(3, I) <= data_f3_out_swap(I);	363	all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
	364	END GENERATE all_bit_of_data_out;	364	time_out_2(J, I) <= time_out(J)(I);
	365		365	END GENERATE all_sample_of_time_out;
	366	-----------------------------------------------------------------------------	366	END GENERATE all_bit_of_time_out;
	367	-- TODO : debug	367
	368	-----------------------------------------------------------------------------	368	lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
	369	all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE	369	GENERIC MAP (tech => tech,
	370	all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE	370	nb_data_by_buffer_size => nb_data_by_buffer_size)
	371	time_out_2(J, I) <= time_out(J)(I);	371	PORT MAP (
	372	END GENERATE all_sample_of_time_out;	372	clk => clk,
	373	END GENERATE all_bit_of_time_out;	373	rstn => rstn,
	374		374	run => run,
	375	lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter	375	nb_data_by_buffer => nb_data_by_buffer,
	376	GENERIC MAP (tech => tech,	376	data_in_valid => valid_out,
	377	nb_data_by_buffer_size => nb_data_by_buffer_size)	377	data_in_ack => valid_ack,
	378	PORT MAP (	378	data_in => data_out,
	379	~~clk~~ => ~~clk~~,	379	time_in => time_out_2,
	380	rstn => rstn,	380
	381	run => run,	381	data_out => wdata,
	382	~~nb_data_by_buffer~~ => ~~nb_data_by_buffer~~,	382	data_out_wen => data_wen,
	383	data_in_valid => valid_out,	383	full_almost => full_almost,
	384	data_in_ack => valid_ack,	384	full => full,
	385	data_in => data_out,	385
	386	time_in => time_out_2,	386	time_out => arbiter_time_out,
	387		387	time_out_new => arbiter_time_out_new
	388	data_out => wdata,	388
	389	data_out_wen => data_wen,	389	);
	390	full_almost => full_almost,	390
	391	full => full,	391	-----------------------------------------------------------------------------
	392		392	-----------------------------------------------------------------------------
	393	time_out => arbiter_time_out,	393
	394	time_out_new => arbiter_time_out_new	394	generate_all_fifo: FOR I IN 0 TO 3 GENERATE
	395		395	lpp_fifo_1: lpp_fifo
	396	);	396	GENERIC MAP (
	397		397	tech => 0,
	398	-----------------------------------------------------------------------------	398	Mem_use => use_RAM,
	399	-----------------------------------------------------------------------------	399	EMPTY_THRESHOLD_LIMIT => 15,
	400		400	FULL_THRESHOLD_LIMIT => 3,
	401	generate_all_fifo: FOR I IN 0 TO 3 GENERATE	401	DataSz => 32,
	402	lpp_fifo_1: lpp_fifo	402	AddrSz => 7)
	403	~~GENERIC~~ MAP (	403	PORT MAP (
	404	~~tech~~ => 0,	404	clk => clk,
	405	~~Mem_use~~ => ~~use_RAM~~,	405	rstn => rstn,
	406	EMPTY_THRESHOLD_LIMIT => 15,	406	reUse => '0',
	407	FULL_THRESHOLD_LIMIT => 3,	407	run => run,
	408	~~DataSz~~ => 32,	408	ren => data_ren(I),
	409	AddrSz => 7)	409	rdata => s_rdata_v((I+1)32-1 downto I32),
	410	PORT MAP (	410	wen => data_wen(I),
	411	~~clk~~ => ~~clk~~,	411	wdata => wdata,
	412	~~rstn~~ => ~~rstn~~,	412	empty => empty(I),
	413	~~reUse~~ => ~~'0'~~,	413	full => full(I),
	414	run => run,	414	full_almost => OPEN,
	415	ren => data_ren(I),	415	empty_threshold => empty_almost(I),
	416	rdata => s_rdata_v((I+1)32-1 downto I32),	416	full_threshold => full_almost(I) );
	417	wen => data_wen(I),	417
	418	wdata => wdata,	418	END GENERATE generate_all_fifo;
	419	empty => empty(I),	419
	420	full => full(I),	420	-----------------------------------------------------------------------------
	421	full_almost => OPEN,	421	--
	422	empty_threshold => empty_almost(I),	422	-----------------------------------------------------------------------------
	423	full_threshold => full_almost(I) );	423
	424		424	all_channel: FOR I IN 3 DOWNTO 0 GENERATE
	425	END GENERATE generate_all_fifo;	425
	426		426	PROCESS (clk, rstn)
	427	-----------------------------------------------------------------------------	427	BEGIN
	428	--	428	IF rstn = '0' THEN
	429	-----------------------------------------------------------------------------	429	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= (OTHERS => '0');
	430		430	ELSIF clk'event AND clk = '1' THEN
	431	all_channel: FOR I IN 3 DOWNTO 0 GENERATE	431	IF run = '0' THEN
	432		432	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= (OTHERS => '0');
	433	PROCESS (clk, rstn)	433	ELSE
	434	BEGIN	434	IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
	435	IF rstn = '0' THEN	435	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= arbiter_time_out;
	436	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= (OTHERS => '0');	436	END IF;
	437	ELSIF clk'event AND clk = '1' THEN	437	END IF;
	438	IF run = '0' THEN	438	END IF;
	439	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= (OTHERS => '0');	439	END PROCESS;
	440	ELSE	440
	441	IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015	441	fifo_buffer_time_s(48(I+1)-1 DOWNTO 48I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
	442	fifo_buffer_time(48(I+1)-1 DOWNTO 48I) <= ~~arbiter_time_out~~;	442	fifo_buffer_time(48(I+1)-1 DOWNTO 48I);
	443	~~END~~ IF;	443
	444	END IF;	444	lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
	445	END IF;	445	PORT MAP (
	446	END PROCESS;	446	clk => clk,
	447		447	rstn => rstn,
	448	fifo_buffer_time_s(48(I+1)-1 DOWNTO 48I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE	448	run => run,
	449	fifo_buffer_time(48(I+1)-1 DOWNTO 48I);	449
	450		450	fifo_buffer_time => fifo_buffer_time_s(48(I+1)-1 DOWNTO 48I),
	451	lpp_waveform_fsmdma_I: lpp_waveform_fsmdma	451
	452	PORT MAP (	452	fifo_data => s_rdata_v(32(I+1)-1 DOWNTO 32I),
	453	clk => clk,	453	fifo_empty => empty(I),
	454	rstn => rstn,	454	fifo_empty_threshold => empty_almost(I),
	455	~~run~~ => ~~run~~,	455	fifo_ren => data_ren(I),
	456		456
	457	fifo_buffer_time => fifo_buffer_time_s(48(I+1)-1 DOWNTO 48I),	457	dma_fifo_valid_burst => dma_fifo_valid_burst(I),
	458		458	dma_fifo_data => dma_fifo_data(32(I+1)-1 DOWNTO 32I),
	459	fifo_data => s_rdata_v(32(I+1)-1 DOWNTO 32I),	459	dma_fifo_ren => dma_fifo_ren(I),
	460	fifo_empty => empty(I),	460	dma_buffer_new => dma_buffer_new(I),
	461	fifo_empty_threshold => empty_almost(I),	461	dma_buffer_addr => dma_buffer_addr(32(I+1)-1 DOWNTO 32I),
	462	fifo_ren => data_ren(I),	462	dma_buffer_length => dma_buffer_length(26(I+1)-1 DOWNTO 26I),
	463		463	dma_buffer_full => dma_buffer_full(I),
	464	dma_fifo_valid_burst => dma_fifo_valid_burst(I),	464	dma_buffer_full_err => dma_buffer_full_err(I),
	465	dma_fifo_data => dma_fifo_data(32(I+1)-1 DOWNTO 32I),	465
	466	dma_fifo_ren => dma_fifo_ren(I),	466	status_buffer_ready => status_buffer_ready(I), -- TODO
	467	dma_buffer_new => dma_buffer_new(I),	467	addr_buffer => addr_buffer(32(I+1)-1 DOWNTO 32I), -- TODO
	468	~~dma_buffer_addr~~ => ~~dma~~_buffer~~_addr~~(32(I+1)-1 ~~DOWNTO~~ 32I),	468	length_buffer => length_buffer,--(26(I+1)-1 DOWNTO 26I), -- TODO
	469	dma_buffer_length => dma_buffer_length(26(I+1)-1 DOWNTO 26I),	469	ready_buffer => ready_buffer(I), -- TODO
	470	dma_buffer_full => dma_buffer_full(I),	470	buffer_time => OPEN,--buffer_time(48(I+1)-1 DOWNTO 48I), -- TODO
	471	dma_buffer_full_err => dma_buffer_full_err(I),	471	error_buffer_full => error_buffer_full(I)); -- TODO
	472		472
	473	status_buffer_ready => status_buffer_ready(I), -- TODO	473	buffer_time(48(I+1)-1 DOWNTO 48I) <= fifo_buffer_time(48(I+1)-1 DOWNTO 48I);
	474	addr_buffer => addr_buffer(32(I+1)-1 DOWNTO 32I), -- TODO	474
	475	length_buffer => length_buffer,--(26(I+1)-1 DOWNTO 26I), -- TODO	475	END GENERATE all_channel;
	476	ready_buffer => ready_buffer(I), -- TODO	476
	477	buffer_time => OPEN,--buffer_time(48(I+1)-1 DOWNTO 48I), -- TODO	477
	478	error_buffer_full => error_buffer_full(I)); -- TODO	478	END beh; No newline at end of file
	479
	480	buffer_time(48(I+1)-1 DOWNTO 48I) <= fifo_buffer_time(48(I+1)-1 DOWNTO 48I);
	481
	482	END GENERATE all_channel;
	483
	484
	485	END beh;

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