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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Updated LFR EM design....
Alexis Jeandet -
r651:bc7dd8a54a19 default draft
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1 SUBDIRS := $(shell find ./ -maxdepth 1 -mindepth 1 -type d)
2
3 all :
4
5 .PHONY: force
6
7
8 %:
9 -for d in $(SUBDIRS); do (cd $$d; $(MAKE) $@ ); done
10
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@@ -1,33 +1,34
1 SCRIPTSDIR=scripts/
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7 .PHONY:doc
7 .PHONY:doc
8
8
9
9
10 all: help
10 all: help
11
11
12 help:
12 help:
13 @echo
13 @echo
14 @echo " batch targets:"
14 @echo " batch targets:"
15 @echo
15 @echo
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
17 @echo " make test : run all tests /!\\ might take a lot of time."
17 @echo " make test : run all tests /!\\ might take a lot of time."
18
18
19
19
20 APB_devs:
20 APB_devs:
21 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
21 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
22
22
23 link:
23 link:
24 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
24 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
25
25
26
26
27 test:
27 test:
28 $(MAKE) -C tests test
28 $(MAKE) -C tests test
29
29
30
30
31 distclean:
31 distclean:
32 $(MAKE) -C tests distclean
32 $(MAKE) -C tests distclean
33 $(MAKE) -C designs distclean
33
34
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@@ -1,127 +1,127
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
80
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
81 #set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
103
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
108
108
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
123
123
124 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
124 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
125 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
125 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
126 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
126 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
127 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
127 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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@@ -1,596 +1,597
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
48
49 --library proasic3l;
49 --library proasic3l;
50 --use proasic3l.all;
50 --use proasic3l.all;
51
51
52 ENTITY LFR_EQM IS
52 ENTITY LFR_EQM IS
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER := use_RAM;
54 Mem_use : INTEGER := use_RAM;
55 USE_BOOTLOADER : INTEGER := 0;
55 USE_BOOTLOADER : INTEGER := 0;
56 USE_ADCDRIVER : INTEGER := 1;
56 USE_ADCDRIVER : INTEGER := 1;
57 tech : INTEGER := inferred;
57 tech : INTEGER := inferred;
58 tech_leon : INTEGER := inferred;
58 tech_leon : INTEGER := inferred;
59 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
59 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
60 USE_DEBUG_VECTOR : INTEGER := 0
60 USE_DEBUG_VECTOR : INTEGER := 0
61 );
61 );
62
62
63 PORT (
63 PORT (
64 clk50MHz : IN STD_ULOGIC;
64 clk50MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
65 clk49_152MHz : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
66 reset : IN STD_ULOGIC;
67
67
68 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
68 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69
69
70 -- TAG --------------------------------------------------------------------
70 -- TAG --------------------------------------------------------------------
71 --TAG1 : IN STD_ULOGIC; -- DSU rx data
71 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
72 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 -- UART APB ---------------------------------------------------------------
73 -- UART APB ---------------------------------------------------------------
74 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
74 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
75 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 -- RAM --------------------------------------------------------------------
76 -- RAM --------------------------------------------------------------------
77 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
77 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
79
80 nSRAM_MBE : INOUT STD_LOGIC; -- new
80 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_E1 : OUT STD_LOGIC; -- new
81 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E2 : OUT STD_LOGIC; -- new
82 nSRAM_E2 : OUT STD_LOGIC; -- new
83 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
83 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 nSRAM_W : OUT STD_LOGIC; -- new
84 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_G : OUT STD_LOGIC; -- new
85 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_BUSY : IN STD_LOGIC; -- new
86 nSRAM_BUSY : IN STD_LOGIC; -- new
87 -- SPW --------------------------------------------------------------------
87 -- SPW --------------------------------------------------------------------
88 spw1_en : OUT STD_LOGIC; -- new
88 spw1_en : OUT STD_LOGIC; -- new
89 spw1_din : IN STD_LOGIC;
89 spw1_din : IN STD_LOGIC;
90 spw1_sin : IN STD_LOGIC;
90 spw1_sin : IN STD_LOGIC;
91 spw1_dout : OUT STD_LOGIC;
91 spw1_dout : OUT STD_LOGIC;
92 spw1_sout : OUT STD_LOGIC;
92 spw1_sout : OUT STD_LOGIC;
93 spw2_en : OUT STD_LOGIC; -- new
93 spw2_en : OUT STD_LOGIC; -- new
94 spw2_din : IN STD_LOGIC;
94 spw2_din : IN STD_LOGIC;
95 spw2_sin : IN STD_LOGIC;
95 spw2_sin : IN STD_LOGIC;
96 spw2_dout : OUT STD_LOGIC;
96 spw2_dout : OUT STD_LOGIC;
97 spw2_sout : OUT STD_LOGIC;
97 spw2_sout : OUT STD_LOGIC;
98 -- ADC --------------------------------------------------------------------
98 -- ADC --------------------------------------------------------------------
99 bias_fail_sw : OUT STD_LOGIC;
99 bias_fail_sw : OUT STD_LOGIC;
100 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
100 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_smpclk : OUT STD_LOGIC;
101 ADC_smpclk : OUT STD_LOGIC;
102 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
102 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 -- DAC --------------------------------------------------------------------
103 -- DAC --------------------------------------------------------------------
104 DAC_SDO : OUT STD_LOGIC;
104 DAC_SDO : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
108 -- HK ---------------------------------------------------------------------
108 -- HK ---------------------------------------------------------------------
109 HK_smpclk : OUT STD_LOGIC;
109 HK_smpclk : OUT STD_LOGIC;
110 ADC_OEB_bar_HK : OUT STD_LOGIC;
110 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
111 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 ---------------------------------------------------------------------------
112 ---------------------------------------------------------------------------
113 -- TAG8 : OUT STD_LOGIC
113 -- TAG8 : OUT STD_LOGIC
114 );
114 );
115
115
116 END LFR_EQM;
116 END LFR_EQM;
117
117
118
118
119 ARCHITECTURE beh OF LFR_EQM IS
119 ARCHITECTURE beh OF LFR_EQM IS
120
120
121 SIGNAL clk_25 : STD_LOGIC := '0';
121 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_24 : STD_LOGIC := '0';
122 SIGNAL clk_24 : STD_LOGIC := '0';
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126
126
127 -- CONSTANTS
127 -- CONSTANTS
128 CONSTANT CFG_PADTECH : INTEGER := inferred;
128 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
129 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
130 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
131 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132
132
133 SIGNAL apbi_ext : apb_slv_in_type;
133 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
134 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL ahbi_s_ext : ahb_slv_in_type;
135 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
136 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
137 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
138 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139
139
140 -- Spacewire signals
140 -- Spacewire signals
141 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
141 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL swni : grspw_in_type;
144 SIGNAL swni : grspw_in_type;
145 SIGNAL swno : grspw_out_type;
145 SIGNAL swno : grspw_out_type;
146
146
147 --GPIO
147 --GPIO
148 SIGNAL gpioi : gpio_in_type;
148 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioo : gpio_out_type;
149 SIGNAL gpioo : gpio_out_type;
150
150
151 -- AD Converter ADS7886
151 -- AD Converter ADS7886
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_val : STD_LOGIC;
154 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156
156
157 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
158 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_25 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
160
160
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
163
163
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
165
165
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
167
167
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
169
169
170 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
170 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171
171
172 SIGNAL rstn_50 : STD_LOGIC;
172 SIGNAL rstn_50 : STD_LOGIC;
173 SIGNAL clk_lock : STD_LOGIC;
173 SIGNAL clk_lock : STD_LOGIC;
174 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
175 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
176
176
177 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 SIGNAL ahbrxd: STD_LOGIC;
178 SIGNAL ahbrxd: STD_LOGIC;
179 SIGNAL ahbtxd: STD_LOGIC;
179 SIGNAL ahbtxd: STD_LOGIC;
180 SIGNAL urxd1 : STD_LOGIC;
180 SIGNAL urxd1 : STD_LOGIC;
181 SIGNAL utxd1 : STD_LOGIC;
181 SIGNAL utxd1 : STD_LOGIC;
182 BEGIN -- beh
182 BEGIN -- beh
183
183
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185 -- CLK_LOCK
185 -- CLK_LOCK
186 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
187 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
187 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
188
188
189 PROCESS (clk50MHz_int, rstn_50)
189 PROCESS (clk50MHz_int, rstn_50)
190 BEGIN -- PROCESS
190 BEGIN -- PROCESS
191 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
191 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
192 clk_lock <= '0';
192 clk_lock <= '0';
193 clk_busy_counter <= (OTHERS => '0');
193 clk_busy_counter <= (OTHERS => '0');
194 nSRAM_BUSY_reg <= '0';
194 nSRAM_BUSY_reg <= '0';
195 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
195 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
196 nSRAM_BUSY_reg <= nSRAM_BUSY;
196 nSRAM_BUSY_reg <= nSRAM_BUSY;
197 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
197 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
198 IF clk_busy_counter = "1111" THEN
198 IF clk_busy_counter = "1111" THEN
199 clk_lock <= '1';
199 clk_lock <= '1';
200 ELSE
200 ELSE
201 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
201 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
202 END IF;
202 END IF;
203 END IF;
203 END IF;
204 END IF;
204 END IF;
205 END PROCESS;
205 END PROCESS;
206
206
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208 -- CLK
208 -- CLK
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
210 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
211 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
211 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
212
212
213 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
213 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
214 clk50MHz_int <= clk50MHz;
214 clk50MHz_int <= clk50MHz;
215
215
216 PROCESS(clk50MHz_int)
216 PROCESS(clk50MHz_int)
217 BEGIN
217 BEGIN
218 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
218 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
219 --clk_25_int <= NOT clk_25_int;
219 --clk_25_int <= NOT clk_25_int;
220 clk_25 <= NOT clk_25;
220 clk_25 <= NOT clk_25;
221 END IF;
221 END IF;
222 END PROCESS;
222 END PROCESS;
223 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
223 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
224
224
225 PROCESS(clk49_152MHz)
225 PROCESS(clk49_152MHz)
226 BEGIN
226 BEGIN
227 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
227 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
228 clk_24 <= NOT clk_24;
228 clk_24 <= NOT clk_24;
229 END IF;
229 END IF;
230 END PROCESS;
230 END PROCESS;
231 -- clk_49 <= clk49_152MHz;
231 -- clk_49 <= clk49_152MHz;
232
232
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 --
234 --
235 leon3_soc_1 : leon3_soc
235 leon3_soc_1 : leon3_soc
236 GENERIC MAP (
236 GENERIC MAP (
237 fabtech => axcel,--inferred,--axdsp,
237 fabtech => axcel,--inferred,--axdsp,
238 memtech => axcel,--inferred,--tech_leon,
238 memtech => axcel,--inferred,--tech_leon,
239 padtech => axcel,--inferred,
239 padtech => axcel,--inferred,
240 clktech => axcel,--inferred,
240 clktech => axcel,--inferred,
241 disas => 0,
241 disas => 0,
242 dbguart => 0,
242 dbguart => 0,
243 pclow => 2,
243 pclow => 2,
244 clk_freq => 25000,
244 clk_freq => 25000,
245 IS_RADHARD => 1,
245 IS_RADHARD => 1,
246 NB_CPU => 1,
246 NB_CPU => 1,
247 ENABLE_FPU => 1,
247 ENABLE_FPU => 1,
248 FPU_NETLIST => 1,
248 FPU_NETLIST => 1,
249 ENABLE_DSU => 1,
249 ENABLE_DSU => 1,
250 ENABLE_AHB_UART => 1,
250 ENABLE_AHB_UART => 1,
251 ENABLE_APB_UART => 1,
251 ENABLE_APB_UART => 1,
252 ENABLE_IRQMP => 1,
252 ENABLE_IRQMP => 1,
253 ENABLE_GPT => 1,
253 ENABLE_GPT => 1,
254 NB_AHB_MASTER => NB_AHB_MASTER,
254 NB_AHB_MASTER => NB_AHB_MASTER,
255 NB_AHB_SLAVE => NB_AHB_SLAVE,
255 NB_AHB_SLAVE => NB_AHB_SLAVE,
256 NB_APB_SLAVE => NB_APB_SLAVE,
256 NB_APB_SLAVE => NB_APB_SLAVE,
257 ADDRESS_SIZE => 19,
257 ADDRESS_SIZE => 19,
258 USES_IAP_MEMCTRLR => 1,
258 USES_IAP_MEMCTRLR => 1,
259 USES_MBE_PIN => 1,
259 BYPASS_EDAC_MEMCTRLR => '0',
260 BYPASS_EDAC_MEMCTRLR => '0',
260 SRBANKSZ => 8)
261 SRBANKSZ => 8)
261 PORT MAP (
262 PORT MAP (
262 clk => clk_25,
263 clk => clk_25,
263 reset => rstn_25,
264 reset => rstn_25,
264 errorn => OPEN,
265 errorn => OPEN,
265
266
266 ahbrxd => ahbrxd, -- INPUT
267 ahbrxd => ahbrxd, -- INPUT
267 ahbtxd => ahbtxd, -- OUTPUT
268 ahbtxd => ahbtxd, -- OUTPUT
268 urxd1 => urxd1, -- INPUT
269 urxd1 => urxd1, -- INPUT
269 utxd1 => utxd1, -- OUTPUT
270 utxd1 => utxd1, -- OUTPUT
270
271
271 address => address,
272 address => address,
272 data => data,
273 data => data,
273 nSRAM_BE0 => OPEN,
274 nSRAM_BE0 => OPEN,
274 nSRAM_BE1 => OPEN,
275 nSRAM_BE1 => OPEN,
275 nSRAM_BE2 => OPEN,
276 nSRAM_BE2 => OPEN,
276 nSRAM_BE3 => OPEN,
277 nSRAM_BE3 => OPEN,
277 nSRAM_WE => nSRAM_W,
278 nSRAM_WE => nSRAM_W,
278 nSRAM_CE => nSRAM_CE,
279 nSRAM_CE => nSRAM_CE,
279 nSRAM_OE => nSRAM_G,
280 nSRAM_OE => nSRAM_G,
280 nSRAM_READY => nSRAM_BUSY,
281 nSRAM_READY => nSRAM_BUSY,
281 SRAM_MBE => nSRAM_MBE,
282 SRAM_MBE => nSRAM_MBE,
282
283
283 apbi_ext => apbi_ext,
284 apbi_ext => apbi_ext,
284 apbo_ext => apbo_ext,
285 apbo_ext => apbo_ext,
285 ahbi_s_ext => ahbi_s_ext,
286 ahbi_s_ext => ahbi_s_ext,
286 ahbo_s_ext => ahbo_s_ext,
287 ahbo_s_ext => ahbo_s_ext,
287 ahbi_m_ext => ahbi_m_ext,
288 ahbi_m_ext => ahbi_m_ext,
288 ahbo_m_ext => ahbo_m_ext);
289 ahbo_m_ext => ahbo_m_ext);
289
290
290
291
291 nSRAM_E1 <= nSRAM_CE(0);
292 nSRAM_E1 <= nSRAM_CE(0);
292 nSRAM_E2 <= nSRAM_CE(1);
293 nSRAM_E2 <= nSRAM_CE(1);
293
294
294 -------------------------------------------------------------------------------
295 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
297 -------------------------------------------------------------------------------
297 apb_lfr_management_1 : apb_lfr_management
298 apb_lfr_management_1 : apb_lfr_management
298 GENERIC MAP (
299 GENERIC MAP (
299 tech => tech,
300 tech => tech,
300 pindex => 6,
301 pindex => 6,
301 paddr => 6,
302 paddr => 6,
302 pmask => 16#fff#,
303 pmask => 16#fff#,
303 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
304 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
304 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
305 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
305 PORT MAP (
306 PORT MAP (
306 clk25MHz => clk_25,
307 clk25MHz => clk_25,
307 resetn_25MHz => rstn_25, -- TODO
308 resetn_25MHz => rstn_25, -- TODO
308 --clk24_576MHz => clk_24, -- 49.152MHz/2
309 --clk24_576MHz => clk_24, -- 49.152MHz/2
309 --resetn_24_576MHz => rstn_24, -- TODO
310 --resetn_24_576MHz => rstn_24, -- TODO
310
311
311 grspw_tick => swno.tickout,
312 grspw_tick => swno.tickout,
312 apbi => apbi_ext,
313 apbi => apbi_ext,
313 apbo => apbo_ext(6),
314 apbo => apbo_ext(6),
314
315
315 HK_sample => sample_s(8),
316 HK_sample => sample_s(8),
316 HK_val => sample_val,
317 HK_val => sample_val,
317 HK_sel => HK_SEL,
318 HK_sel => HK_SEL,
318
319
319 DAC_SDO => DAC_SDO,
320 DAC_SDO => DAC_SDO,
320 DAC_SCK => DAC_SCK,
321 DAC_SCK => DAC_SCK,
321 DAC_SYNC => DAC_SYNC,
322 DAC_SYNC => DAC_SYNC,
322 DAC_CAL_EN => DAC_CAL_EN,
323 DAC_CAL_EN => DAC_CAL_EN,
323
324
324 coarse_time => coarse_time,
325 coarse_time => coarse_time,
325 fine_time => fine_time,
326 fine_time => fine_time,
326 LFR_soft_rstn => LFR_soft_rstn
327 LFR_soft_rstn => LFR_soft_rstn
327 );
328 );
328
329
329 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
330 --- SpaceWire --------------------------------------------------------
331 --- SpaceWire --------------------------------------------------------
331 -----------------------------------------------------------------------
332 -----------------------------------------------------------------------
332
333
333 ------------------------------------------------------------------------------
334 ------------------------------------------------------------------------------
334 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
335 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
335 ------------------------------------------------------------------------------
336 ------------------------------------------------------------------------------
336 spw1_en <= '1';
337 spw1_en <= '1';
337 spw2_en <= '1';
338 spw2_en <= '1';
338 ------------------------------------------------------------------------------
339 ------------------------------------------------------------------------------
339 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
340 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
340 ------------------------------------------------------------------------------
341 ------------------------------------------------------------------------------
341
342
342 --spw_clk <= clk50MHz;
343 --spw_clk <= clk50MHz;
343 --spw_rxtxclk <= spw_clk;
344 --spw_rxtxclk <= spw_clk;
344 --spw_rxclkn <= NOT spw_rxtxclk;
345 --spw_rxclkn <= NOT spw_rxtxclk;
345
346
346 -- PADS for SPW1
347 -- PADS for SPW1
347 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
348 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
348 PORT MAP (spw1_din, dtmp(0));
349 PORT MAP (spw1_din, dtmp(0));
349 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
350 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
350 PORT MAP (spw1_sin, stmp(0));
351 PORT MAP (spw1_sin, stmp(0));
351 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_dout, swno.d(0));
353 PORT MAP (spw1_dout, swno.d(0));
353 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sout, swno.s(0));
355 PORT MAP (spw1_sout, swno.s(0));
355 -- PADS FOR SPW2
356 -- PADS FOR SPW2
356 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 PORT MAP (spw2_din, dtmp(1));
358 PORT MAP (spw2_din, dtmp(1));
358 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
359 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
359 PORT MAP (spw2_sin, stmp(1));
360 PORT MAP (spw2_sin, stmp(1));
360 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
361 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (spw2_dout, swno.d(1));
362 PORT MAP (spw2_dout, swno.d(1));
362 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
363 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
363 PORT MAP (spw2_sout, swno.s(1));
364 PORT MAP (spw2_sout, swno.s(1));
364
365
365 -- GRSPW PHY
366 -- GRSPW PHY
366 --spw1_input: if CFG_SPW_GRSPW = 1 generate
367 --spw1_input: if CFG_SPW_GRSPW = 1 generate
367 spw_inputloop : FOR j IN 0 TO 1 GENERATE
368 spw_inputloop : FOR j IN 0 TO 1 GENERATE
368 spw_phy0 : grspw_phy
369 spw_phy0 : grspw_phy
369 GENERIC MAP(
370 GENERIC MAP(
370 tech => axcel,-- inferred,--axdsp,--tech_leon,
371 tech => axcel,-- inferred,--axdsp,--tech_leon,
371 rxclkbuftype => 1,
372 rxclkbuftype => 1,
372 scantest => 0)
373 scantest => 0)
373 PORT MAP(
374 PORT MAP(
374 rxrst => swno.rxrst,
375 rxrst => swno.rxrst,
375 di => dtmp(j),
376 di => dtmp(j),
376 si => stmp(j),
377 si => stmp(j),
377 rxclko => spw_rxclk(j),
378 rxclko => spw_rxclk(j),
378 do => swni.d(j),
379 do => swni.d(j),
379 ndo => swni.nd(j*5+4 DOWNTO j*5),
380 ndo => swni.nd(j*5+4 DOWNTO j*5),
380 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
381 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
381 END GENERATE spw_inputloop;
382 END GENERATE spw_inputloop;
382
383
383 -- SPW core
384 -- SPW core
384 sw0 : grspwm GENERIC MAP(
385 sw0 : grspwm GENERIC MAP(
385 tech => axcel,--inferred,--axdsp,--tech_leon,
386 tech => axcel,--inferred,--axdsp,--tech_leon,
386 hindex => 1,
387 hindex => 1,
387 pindex => 5,
388 pindex => 5,
388 paddr => 5,
389 paddr => 5,
389 pirq => 11,
390 pirq => 11,
390 sysfreq => 25000, -- CPU_FREQ
391 sysfreq => 25000, -- CPU_FREQ
391 rmap => 1,
392 rmap => 1,
392 rmapcrc => 1,
393 rmapcrc => 1,
393 fifosize1 => 16,
394 fifosize1 => 16,
394 fifosize2 => 16,
395 fifosize2 => 16,
395 rxclkbuftype => 1,
396 rxclkbuftype => 1,
396 rxunaligned => 0,
397 rxunaligned => 0,
397 rmapbufs => 4,
398 rmapbufs => 4,
398 ft => 1,
399 ft => 1,
399 netlist => 0,
400 netlist => 0,
400 ports => 2,
401 ports => 2,
401 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
402 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
402 memtech => axcel,--inferred,--tech_leon,
403 memtech => axcel,--inferred,--tech_leon,
403 destkey => 2,
404 destkey => 2,
404 spwcore => 1
405 spwcore => 1
405 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
406 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
406 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
407 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
407 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
408 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
408 )
409 )
409 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
410 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
410 spw_rxclk(1),
411 spw_rxclk(1),
411 clk50MHz_int,
412 clk50MHz_int,
412 clk50MHz_int,
413 clk50MHz_int,
413 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
414 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
414 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
415 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
415 swni, swno);
416 swni, swno);
416
417
417 swni.tickin <= '0';
418 swni.tickin <= '0';
418 swni.rmapen <= '1';
419 swni.rmapen <= '1';
419 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
420 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
420 swni.tickinraw <= '0';
421 swni.tickinraw <= '0';
421 swni.timein <= (OTHERS => '0');
422 swni.timein <= (OTHERS => '0');
422 swni.dcrstval <= (OTHERS => '0');
423 swni.dcrstval <= (OTHERS => '0');
423 swni.timerrstval <= (OTHERS => '0');
424 swni.timerrstval <= (OTHERS => '0');
424
425
425 -------------------------------------------------------------------------------
426 -------------------------------------------------------------------------------
426 -- LFR ------------------------------------------------------------------------
427 -- LFR ------------------------------------------------------------------------
427 -------------------------------------------------------------------------------
428 -------------------------------------------------------------------------------
428 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
429 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
429 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
430 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
430
431
431 lpp_lfr_1 : lpp_lfr
432 lpp_lfr_1 : lpp_lfr
432 GENERIC MAP (
433 GENERIC MAP (
433 Mem_use => Mem_use,
434 Mem_use => Mem_use,
434 tech => inferred,--tech,
435 tech => inferred,--tech,
435 nb_data_by_buffer_size => 32,
436 nb_data_by_buffer_size => 32,
436 --nb_word_by_buffer_size => 30,
437 --nb_word_by_buffer_size => 30,
437 nb_snapshot_param_size => 32,
438 nb_snapshot_param_size => 32,
438 delta_vector_size => 32,
439 delta_vector_size => 32,
439 delta_vector_size_f0_2 => 7, -- log2(96)
440 delta_vector_size_f0_2 => 7, -- log2(96)
440 pindex => 15,
441 pindex => 15,
441 paddr => 15,
442 paddr => 15,
442 pmask => 16#fff#,
443 pmask => 16#fff#,
443 pirq_ms => 6,
444 pirq_ms => 6,
444 pirq_wfp => 14,
445 pirq_wfp => 14,
445 hindex => 2,
446 hindex => 2,
446 top_lfr_version => X"020153", -- aa.bb.cc version
447 top_lfr_version => X"020153", -- aa.bb.cc version
447 -- AA : BOARD NUMBER
448 -- AA : BOARD NUMBER
448 -- 0 => MINI_LFR
449 -- 0 => MINI_LFR
449 -- 1 => EM
450 -- 1 => EM
450 -- 2 => EQM (with A3PE3000)
451 -- 2 => EQM (with A3PE3000)
451 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
452 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
452 PORT MAP (
453 PORT MAP (
453 clk => clk_25,
454 clk => clk_25,
454 rstn => rstn_25,--LFR_rstn,
455 rstn => rstn_25,--LFR_rstn,
455 sample_B => sample_s(2 DOWNTO 0),
456 sample_B => sample_s(2 DOWNTO 0),
456 sample_E => sample_s(7 DOWNTO 3),
457 sample_E => sample_s(7 DOWNTO 3),
457 sample_val => sample_val,
458 sample_val => sample_val,
458 apbi => apbi_ext,
459 apbi => apbi_ext,
459 apbo => apbo_ext(15),
460 apbo => apbo_ext(15),
460 ahbi => ahbi_m_ext,
461 ahbi => ahbi_m_ext,
461 ahbo => ahbo_m_ext(2),
462 ahbo => ahbo_m_ext(2),
462 coarse_time => coarse_time,
463 coarse_time => coarse_time,
463 fine_time => fine_time,
464 fine_time => fine_time,
464 data_shaping_BW => bias_fail_sw,
465 data_shaping_BW => bias_fail_sw,
465 debug_vector => debug_vector,
466 debug_vector => debug_vector,
466 debug_vector_ms => OPEN); --,
467 debug_vector_ms => OPEN); --,
467 --observation_vector_0 => OPEN,
468 --observation_vector_0 => OPEN,
468 --observation_vector_1 => OPEN,
469 --observation_vector_1 => OPEN,
469 --observation_reg => observation_reg);
470 --observation_reg => observation_reg);
470
471
471
472
472 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
473 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
473 sample_s(I) <= sample(I) & '0' & '0';
474 sample_s(I) <= sample(I) & '0' & '0';
474 END GENERATE all_sample;
475 END GENERATE all_sample;
475 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
476 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
476
477
477 -----------------------------------------------------------------------------
478 -----------------------------------------------------------------------------
478 --
479 --
479 -----------------------------------------------------------------------------
480 -----------------------------------------------------------------------------
480 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
481 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
481 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
482 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
482 GENERIC MAP (
483 GENERIC MAP (
483 ChanelCount => 9,
484 ChanelCount => 9,
484 ncycle_cnv_high => 12,
485 ncycle_cnv_high => 12,
485 ncycle_cnv => 25,
486 ncycle_cnv => 25,
486 FILTER_ENABLED => 16#FF#)
487 FILTER_ENABLED => 16#FF#)
487 PORT MAP (
488 PORT MAP (
488 cnv_clk => clk_24,
489 cnv_clk => clk_24,
489 cnv_rstn => rstn_24,
490 cnv_rstn => rstn_24,
490 cnv => ADC_smpclk_s,
491 cnv => ADC_smpclk_s,
491 clk => clk_25,
492 clk => clk_25,
492 rstn => rstn_25,
493 rstn => rstn_25,
493 ADC_data => ADC_data,
494 ADC_data => ADC_data,
494 ADC_nOE => ADC_OEB_bar_CH_s,
495 ADC_nOE => ADC_OEB_bar_CH_s,
495 sample => sample,
496 sample => sample,
496 sample_val => sample_val);
497 sample_val => sample_val);
497
498
498 END GENERATE USE_ADCDRIVER_true;
499 END GENERATE USE_ADCDRIVER_true;
499
500
500 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
501 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
501 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
502 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
502 GENERIC MAP (
503 GENERIC MAP (
503 ChanelCount => 9,
504 ChanelCount => 9,
504 ncycle_cnv_high => 25,
505 ncycle_cnv_high => 25,
505 ncycle_cnv => 50,
506 ncycle_cnv => 50,
506 FILTER_ENABLED => 16#FF#)
507 FILTER_ENABLED => 16#FF#)
507 PORT MAP (
508 PORT MAP (
508 cnv_clk => clk_24,
509 cnv_clk => clk_24,
509 cnv_rstn => rstn_24,
510 cnv_rstn => rstn_24,
510 cnv => ADC_smpclk_s,
511 cnv => ADC_smpclk_s,
511 clk => clk_25,
512 clk => clk_25,
512 rstn => rstn_25,
513 rstn => rstn_25,
513 ADC_data => ADC_data,
514 ADC_data => ADC_data,
514 ADC_nOE => OPEN,
515 ADC_nOE => OPEN,
515 sample => OPEN,
516 sample => OPEN,
516 sample_val => sample_val);
517 sample_val => sample_val);
517
518
518 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
519 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
519
520
520 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
521 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
521 ramp_generator_1: ramp_generator
522 ramp_generator_1: ramp_generator
522 GENERIC MAP (
523 GENERIC MAP (
523 DATA_SIZE => 14,
524 DATA_SIZE => 14,
524 VALUE_UNSIGNED_INIT => 2**I,
525 VALUE_UNSIGNED_INIT => 2**I,
525 VALUE_UNSIGNED_INCR => 0,
526 VALUE_UNSIGNED_INCR => 0,
526 VALUE_UNSIGNED_MASK => 16#3FFF#)
527 VALUE_UNSIGNED_MASK => 16#3FFF#)
527 PORT MAP (
528 PORT MAP (
528 clk => clk_25,
529 clk => clk_25,
529 rstn => rstn_25,
530 rstn => rstn_25,
530 new_data => sample_val,
531 new_data => sample_val,
531 output_data => sample(I) );
532 output_data => sample(I) );
532 END GENERATE all_sample;
533 END GENERATE all_sample;
533
534
534
535
535 END GENERATE USE_ADCDRIVER_false;
536 END GENERATE USE_ADCDRIVER_false;
536
537
537
538
538
539
539
540
540 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
541 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
541
542
542 ADC_smpclk <= ADC_smpclk_s;
543 ADC_smpclk <= ADC_smpclk_s;
543 HK_smpclk <= ADC_smpclk_s;
544 HK_smpclk <= ADC_smpclk_s;
544
545
545
546
546 -----------------------------------------------------------------------------
547 -----------------------------------------------------------------------------
547 -- HK
548 -- HK
548 -----------------------------------------------------------------------------
549 -----------------------------------------------------------------------------
549 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
550 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
550
551
551 -----------------------------------------------------------------------------
552 -----------------------------------------------------------------------------
552 --
553 --
553 -----------------------------------------------------------------------------
554 -----------------------------------------------------------------------------
554 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
555 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
555 -- lpp_bootloader_1: lpp_bootloader
556 -- lpp_bootloader_1: lpp_bootloader
556 -- GENERIC MAP (
557 -- GENERIC MAP (
557 -- pindex => 13,
558 -- pindex => 13,
558 -- paddr => 13,
559 -- paddr => 13,
559 -- pmask => 16#fff#,
560 -- pmask => 16#fff#,
560 -- hindex => 3,
561 -- hindex => 3,
561 -- haddr => 0,
562 -- haddr => 0,
562 -- hmask => 16#fff#)
563 -- hmask => 16#fff#)
563 -- PORT MAP (
564 -- PORT MAP (
564 -- HCLK => clk_25,
565 -- HCLK => clk_25,
565 -- HRESETn => rstn_25,
566 -- HRESETn => rstn_25,
566 -- apbi => apbi_ext,
567 -- apbi => apbi_ext,
567 -- apbo => apbo_ext(13),
568 -- apbo => apbo_ext(13),
568 -- ahbsi => ahbi_s_ext,
569 -- ahbsi => ahbi_s_ext,
569 -- ahbso => ahbo_s_ext(3));
570 -- ahbso => ahbo_s_ext(3));
570 --END GENERATE inst_bootloader;
571 --END GENERATE inst_bootloader;
571
572
572 -----------------------------------------------------------------------------
573 -----------------------------------------------------------------------------
573 --
574 --
574 -----------------------------------------------------------------------------
575 -----------------------------------------------------------------------------
575 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
576 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
576 PROCESS (clk_25, rstn_25)
577 PROCESS (clk_25, rstn_25)
577 BEGIN -- PROCESS
578 BEGIN -- PROCESS
578 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
579 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
579 TAG <= (OTHERS => '0');
580 TAG <= (OTHERS => '0');
580 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
581 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
581 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
582 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
582 END IF;
583 END IF;
583 END PROCESS;
584 END PROCESS;
584
585
585
586
586 END GENERATE USE_DEBUG_VECTOR_IF;
587 END GENERATE USE_DEBUG_VECTOR_IF;
587
588
588 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
589 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
589 ahbrxd <= TAG(1);
590 ahbrxd <= TAG(1);
590 TAG(3) <= ahbtxd;
591 TAG(3) <= ahbtxd;
591 urxd1 <= TAG(2);
592 urxd1 <= TAG(2);
592 TAG(4) <= utxd1;
593 TAG(4) <= utxd1;
593 TAG(8) <= nSRAM_BUSY;
594 TAG(8) <= nSRAM_BUSY;
594 END GENERATE USE_DEBUG_VECTOR_IF2;
595 END GENERATE USE_DEBUG_VECTOR_IF2;
595
596
596 END beh;
597 END beh;
Show file before | Show file after | Hide comments
@@ -1,605 +1,606
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 USE techmap.axcomp.ALL;
30 USE techmap.axcomp.ALL;
31
31
32 LIBRARY gaisler;
32 LIBRARY gaisler;
33 USE gaisler.sim.ALL;
33 USE gaisler.sim.ALL;
34 USE gaisler.memctrl.ALL;
34 USE gaisler.memctrl.ALL;
35 USE gaisler.leon3.ALL;
35 USE gaisler.leon3.ALL;
36 USE gaisler.uart.ALL;
36 USE gaisler.uart.ALL;
37 USE gaisler.misc.ALL;
37 USE gaisler.misc.ALL;
38 USE gaisler.spacewire.ALL;
38 USE gaisler.spacewire.ALL;
39 LIBRARY esa;
39 LIBRARY esa;
40 USE esa.memoryctrl.ALL;
40 USE esa.memoryctrl.ALL;
41 LIBRARY lpp;
41 LIBRARY lpp;
42 USE lpp.lpp_memory.ALL;
42 USE lpp.lpp_memory.ALL;
43 USE lpp.lpp_ad_conv.ALL;
43 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 USE lpp.iir_filter.ALL;
46 USE lpp.iir_filter.ALL;
47 USE lpp.general_purpose.ALL;
47 USE lpp.general_purpose.ALL;
48 USE lpp.lpp_lfr_management.ALL;
48 USE lpp.lpp_lfr_management.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
50
50
51 --library proasic3l;
51 --library proasic3l;
52 --use proasic3l.all;
52 --use proasic3l.all;
53
53
54 ENTITY LFR_EQM IS
54 ENTITY LFR_EQM IS
55 GENERIC (
55 GENERIC (
56 Mem_use : INTEGER := use_RAM;
56 Mem_use : INTEGER := use_RAM;
57 USE_BOOTLOADER : INTEGER := 0;
57 USE_BOOTLOADER : INTEGER := 0;
58 USE_ADCDRIVER : INTEGER := 1;
58 USE_ADCDRIVER : INTEGER := 1;
59 tech : INTEGER := inferred;
59 tech : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
62 USE_DEBUG_VECTOR : INTEGER := 0
62 USE_DEBUG_VECTOR : INTEGER := 0
63 );
63 );
64
64
65 PORT (
65 PORT (
66 clk50MHz : IN STD_ULOGIC;
66 clk50MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
69
69
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
71
71
72 -- TAG --------------------------------------------------------------------
72 -- TAG --------------------------------------------------------------------
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
75 -- UART APB ---------------------------------------------------------------
75 -- UART APB ---------------------------------------------------------------
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
78 -- RAM --------------------------------------------------------------------
78 -- RAM --------------------------------------------------------------------
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81
81
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
89 -- SPW --------------------------------------------------------------------
89 -- SPW --------------------------------------------------------------------
90 spw1_en : OUT STD_LOGIC; -- new
90 spw1_en : OUT STD_LOGIC; -- new
91 spw1_din : IN STD_LOGIC;
91 spw1_din : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
95 spw2_en : OUT STD_LOGIC; -- new
95 spw2_en : OUT STD_LOGIC; -- new
96 spw2_din : IN STD_LOGIC;
96 spw2_din : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
100 -- ADC --------------------------------------------------------------------
100 -- ADC --------------------------------------------------------------------
101 bias_fail_sw : OUT STD_LOGIC;
101 bias_fail_sw : OUT STD_LOGIC;
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 ADC_smpclk : OUT STD_LOGIC;
103 ADC_smpclk : OUT STD_LOGIC;
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105 -- DAC --------------------------------------------------------------------
105 -- DAC --------------------------------------------------------------------
106 DAC_SDO : OUT STD_LOGIC;
106 DAC_SDO : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
110 -- HK ---------------------------------------------------------------------
110 -- HK ---------------------------------------------------------------------
111 HK_smpclk : OUT STD_LOGIC;
111 HK_smpclk : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
114 );
114 );
115
115
116 END LFR_EQM;
116 END LFR_EQM;
117
117
118
118
119 ARCHITECTURE beh OF LFR_EQM IS
119 ARCHITECTURE beh OF LFR_EQM IS
120
120
121 SIGNAL clk_25_int : STD_LOGIC := '0';
121 SIGNAL clk_25_int : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
127
128 -- CONSTANTS
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
133
134 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
140
141 -- Spacewire signals
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL swni : grspw_in_type;
145 SIGNAL swni : grspw_in_type;
146 SIGNAL swno : grspw_out_type;
146 SIGNAL swno : grspw_out_type;
147
147
148 --GPIO
148 --GPIO
149 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioi : gpio_in_type;
150 SIGNAL gpioo : gpio_out_type;
150 SIGNAL gpioo : gpio_out_type;
151
151
152 -- AD Converter ADS7886
152 -- AD Converter ADS7886
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
155 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL sample_val : STD_LOGIC;
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
157
157
158 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
161 SIGNAL rstn_25 : STD_LOGIC;
161 SIGNAL rstn_25 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
163
163
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
166
166
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
168
168
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
170
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172
172
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174
174
175 SIGNAL rstn_50 : STD_LOGIC;
175 SIGNAL rstn_50 : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179
179
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 SIGNAL ahbrxd: STD_LOGIC;
181 SIGNAL ahbrxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
185 BEGIN -- beh
185 BEGIN -- beh
186
186
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188 -- CLK_LOCK
188 -- CLK_LOCK
189 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191
191
192 PROCESS (clk50MHz_int, rstn_50)
192 PROCESS (clk50MHz_int, rstn_50)
193 BEGIN -- PROCESS
193 BEGIN -- PROCESS
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 clk_lock <= '0';
195 clk_lock <= '0';
196 clk_busy_counter <= (OTHERS => '0');
196 clk_busy_counter <= (OTHERS => '0');
197 nSRAM_BUSY_reg <= '0';
197 nSRAM_BUSY_reg <= '0';
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 IF clk_busy_counter = "1111" THEN
201 IF clk_busy_counter = "1111" THEN
202 clk_lock <= '1';
202 clk_lock <= '1';
203 ELSE
203 ELSE
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 END IF;
205 END IF;
206 END IF;
206 END IF;
207 END IF;
207 END IF;
208 END PROCESS;
208 END PROCESS;
209
209
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 -- CLK
211 -- CLK
212 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215
215
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217
217
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 clk50MHz_int <= clk50MHz;
219 clk50MHz_int <= clk50MHz;
220
220
221 PROCESS(clk50MHz_int)
221 PROCESS(clk50MHz_int)
222 BEGIN
222 BEGIN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 clk_25_int <= NOT clk_25_int;
224 clk_25_int <= NOT clk_25_int;
225 --clk_25 <= NOT clk_25;
225 --clk_25 <= NOT clk_25;
226 END IF;
226 END IF;
227 END PROCESS;
227 END PROCESS;
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229
229
230 PROCESS(clk49_152MHz)
230 PROCESS(clk49_152MHz)
231 BEGIN
231 BEGIN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 clk_24 <= NOT clk_24;
233 clk_24 <= NOT clk_24;
234 END IF;
234 END IF;
235 END PROCESS;
235 END PROCESS;
236 -- clk_49 <= clk49_152MHz;
236 -- clk_49 <= clk49_152MHz;
237
237
238 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
239 leon3_soc_1 : leon3_soc
239 leon3_soc_1 : leon3_soc
240 GENERIC MAP (
240 GENERIC MAP (
241 fabtech => axcel,--inferred,--axdsp,
241 fabtech => axcel,--inferred,--axdsp,
242 memtech => axcel,--inferred,--tech_leon,
242 memtech => axcel,--inferred,--tech_leon,
243 padtech => axcel,--inferred,
243 padtech => axcel,--inferred,
244 clktech => axcel,--inferred,
244 clktech => axcel,--inferred,
245 disas => 0,
245 disas => 0,
246 dbguart => 0,
246 dbguart => 0,
247 pclow => 2,
247 pclow => 2,
248 clk_freq => 25000,
248 clk_freq => 25000,
249 IS_RADHARD => 1,
249 IS_RADHARD => 1,
250 NB_CPU => 1,
250 NB_CPU => 1,
251 ENABLE_FPU => 1,
251 ENABLE_FPU => 1,
252 FPU_NETLIST => 0,
252 FPU_NETLIST => 0,
253 ENABLE_DSU => 1,
253 ENABLE_DSU => 1,
254 ENABLE_AHB_UART => 0,
254 ENABLE_AHB_UART => 0,
255 ENABLE_APB_UART => 1,
255 ENABLE_APB_UART => 1,
256 ENABLE_IRQMP => 1,
256 ENABLE_IRQMP => 1,
257 ENABLE_GPT => 1,
257 ENABLE_GPT => 1,
258 NB_AHB_MASTER => NB_AHB_MASTER,
258 NB_AHB_MASTER => NB_AHB_MASTER,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
261 ADDRESS_SIZE => 19,
261 ADDRESS_SIZE => 19,
262 USES_IAP_MEMCTRLR => 1,
262 USES_IAP_MEMCTRLR => 1,
263 USES_MBE_PIN => 1,
263 BYPASS_EDAC_MEMCTRLR => '0',
264 BYPASS_EDAC_MEMCTRLR => '0',
264 SRBANKSZ => 8)
265 SRBANKSZ => 8)
265 PORT MAP (
266 PORT MAP (
266 clk => clk_25,
267 clk => clk_25,
267 reset => rstn_25,
268 reset => rstn_25,
268 errorn => OPEN,
269 errorn => OPEN,
269
270
270 ahbrxd => ahbrxd, -- INPUT
271 ahbrxd => ahbrxd, -- INPUT
271 ahbtxd => ahbtxd, -- OUTPUT
272 ahbtxd => ahbtxd, -- OUTPUT
272 urxd1 => urxd1, -- INPUT
273 urxd1 => urxd1, -- INPUT
273 utxd1 => utxd1, -- OUTPUT
274 utxd1 => utxd1, -- OUTPUT
274
275
275 address => address,
276 address => address,
276 data => data,
277 data => data,
277 nSRAM_BE0 => OPEN,
278 nSRAM_BE0 => OPEN,
278 nSRAM_BE1 => OPEN,
279 nSRAM_BE1 => OPEN,
279 nSRAM_BE2 => OPEN,
280 nSRAM_BE2 => OPEN,
280 nSRAM_BE3 => OPEN,
281 nSRAM_BE3 => OPEN,
281 nSRAM_WE => nSRAM_W,
282 nSRAM_WE => nSRAM_W,
282 nSRAM_CE => nSRAM_CE,
283 nSRAM_CE => nSRAM_CE,
283 nSRAM_OE => nSRAM_G,
284 nSRAM_OE => nSRAM_G,
284 nSRAM_READY => nSRAM_BUSY,
285 nSRAM_READY => nSRAM_BUSY,
285 SRAM_MBE => nSRAM_MBE,
286 SRAM_MBE => nSRAM_MBE,
286
287
287 apbi_ext => apbi_ext,
288 apbi_ext => apbi_ext,
288 apbo_ext => apbo_ext,
289 apbo_ext => apbo_ext,
289 ahbi_s_ext => ahbi_s_ext,
290 ahbi_s_ext => ahbi_s_ext,
290 ahbo_s_ext => ahbo_s_ext,
291 ahbo_s_ext => ahbo_s_ext,
291 ahbi_m_ext => ahbi_m_ext,
292 ahbi_m_ext => ahbi_m_ext,
292 ahbo_m_ext => ahbo_m_ext);
293 ahbo_m_ext => ahbo_m_ext);
293
294
294
295
295 nSRAM_E1 <= nSRAM_CE(0);
296 nSRAM_E1 <= nSRAM_CE(0);
296 nSRAM_E2 <= nSRAM_CE(1);
297 nSRAM_E2 <= nSRAM_CE(1);
297
298
298 -------------------------------------------------------------------------------
299 -------------------------------------------------------------------------------
299 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
300 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
300 -------------------------------------------------------------------------------
301 -------------------------------------------------------------------------------
301 apb_lfr_management_1 : apb_lfr_management
302 apb_lfr_management_1 : apb_lfr_management
302 GENERIC MAP (
303 GENERIC MAP (
303 tech => tech,
304 tech => tech,
304 pindex => 6,
305 pindex => 6,
305 paddr => 6,
306 paddr => 6,
306 pmask => 16#fff#,
307 pmask => 16#fff#,
307 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
308 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
308 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
309 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
309 PORT MAP (
310 PORT MAP (
310 clk25MHz => clk_25,
311 clk25MHz => clk_25,
311 resetn_25MHz => rstn_25, -- TODO
312 resetn_25MHz => rstn_25, -- TODO
312 --clk24_576MHz => clk_24, -- 49.152MHz/2
313 --clk24_576MHz => clk_24, -- 49.152MHz/2
313 --resetn_24_576MHz => rstn_24, -- TODO
314 --resetn_24_576MHz => rstn_24, -- TODO
314
315
315 grspw_tick => swno.tickout,
316 grspw_tick => swno.tickout,
316 apbi => apbi_ext,
317 apbi => apbi_ext,
317 apbo => apbo_ext(6),
318 apbo => apbo_ext(6),
318
319
319 HK_sample => sample_s(8),
320 HK_sample => sample_s(8),
320 HK_val => sample_val,
321 HK_val => sample_val,
321 HK_sel => HK_SEL,
322 HK_sel => HK_SEL,
322
323
323 DAC_SDO => DAC_SDO,
324 DAC_SDO => DAC_SDO,
324 DAC_SCK => DAC_SCK,
325 DAC_SCK => DAC_SCK,
325 DAC_SYNC => DAC_SYNC,
326 DAC_SYNC => DAC_SYNC,
326 DAC_CAL_EN => DAC_CAL_EN,
327 DAC_CAL_EN => DAC_CAL_EN,
327
328
328 coarse_time => coarse_time,
329 coarse_time => coarse_time,
329 fine_time => fine_time,
330 fine_time => fine_time,
330 LFR_soft_rstn => LFR_soft_rstn
331 LFR_soft_rstn => LFR_soft_rstn
331 );
332 );
332
333
333 -----------------------------------------------------------------------
334 -----------------------------------------------------------------------
334 --- SpaceWire --------------------------------------------------------
335 --- SpaceWire --------------------------------------------------------
335 -----------------------------------------------------------------------
336 -----------------------------------------------------------------------
336
337
337 ------------------------------------------------------------------------------
338 ------------------------------------------------------------------------------
338 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
339 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
339 ------------------------------------------------------------------------------
340 ------------------------------------------------------------------------------
340 spw1_en <= '1';
341 spw1_en <= '1';
341 spw2_en <= '1';
342 spw2_en <= '1';
342 ------------------------------------------------------------------------------
343 ------------------------------------------------------------------------------
343 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
344 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
344 ------------------------------------------------------------------------------
345 ------------------------------------------------------------------------------
345
346
346 --spw_clk <= clk50MHz;
347 --spw_clk <= clk50MHz;
347 --spw_rxtxclk <= spw_clk;
348 --spw_rxtxclk <= spw_clk;
348 --spw_rxclkn <= NOT spw_rxtxclk;
349 --spw_rxclkn <= NOT spw_rxtxclk;
349
350
350 -- PADS for SPW1
351 -- PADS for SPW1
351 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
352 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_din, dtmp(0));
353 PORT MAP (spw1_din, dtmp(0));
353 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
354 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sin, stmp(0));
355 PORT MAP (spw1_sin, stmp(0));
355 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
356 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
356 PORT MAP (spw1_dout, swno.d(0));
357 PORT MAP (spw1_dout, swno.d(0));
357 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
358 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
358 PORT MAP (spw1_sout, swno.s(0));
359 PORT MAP (spw1_sout, swno.s(0));
359 -- PADS FOR SPW2
360 -- PADS FOR SPW2
360 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
361 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
361 PORT MAP (spw2_din, dtmp(1));
362 PORT MAP (spw2_din, dtmp(1));
362 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 PORT MAP (spw2_sin, stmp(1));
364 PORT MAP (spw2_sin, stmp(1));
364 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
365 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
365 PORT MAP (spw2_dout, swno.d(1));
366 PORT MAP (spw2_dout, swno.d(1));
366 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
367 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
367 PORT MAP (spw2_sout, swno.s(1));
368 PORT MAP (spw2_sout, swno.s(1));
368
369
369 -- GRSPW PHY
370 -- GRSPW PHY
370 --spw1_input: if CFG_SPW_GRSPW = 1 generate
371 --spw1_input: if CFG_SPW_GRSPW = 1 generate
371 spw_inputloop : FOR j IN 0 TO 1 GENERATE
372 spw_inputloop : FOR j IN 0 TO 1 GENERATE
372 spw_phy0 : grspw_phy
373 spw_phy0 : grspw_phy
373 GENERIC MAP(
374 GENERIC MAP(
374 tech => axcel,-- inferred,--axdsp,--tech_leon,
375 tech => axcel,-- inferred,--axdsp,--tech_leon,
375 rxclkbuftype => 1,
376 rxclkbuftype => 1,
376 scantest => 0)
377 scantest => 0)
377 PORT MAP(
378 PORT MAP(
378 rxrst => swno.rxrst,
379 rxrst => swno.rxrst,
379 di => dtmp(j),
380 di => dtmp(j),
380 si => stmp(j),
381 si => stmp(j),
381 rxclko => spw_rxclk(j),
382 rxclko => spw_rxclk(j),
382 do => swni.d(j),
383 do => swni.d(j),
383 ndo => swni.nd(j*5+4 DOWNTO j*5),
384 ndo => swni.nd(j*5+4 DOWNTO j*5),
384 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
385 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
385 END GENERATE spw_inputloop;
386 END GENERATE spw_inputloop;
386
387
387 -- SPW core
388 -- SPW core
388 sw0 : grspwm GENERIC MAP(
389 sw0 : grspwm GENERIC MAP(
389 tech => axcel,--inferred,--axdsp,--tech_leon,
390 tech => axcel,--inferred,--axdsp,--tech_leon,
390 hindex => 1,
391 hindex => 1,
391 pindex => 5,
392 pindex => 5,
392 paddr => 5,
393 paddr => 5,
393 pirq => 11,
394 pirq => 11,
394 sysfreq => 25000, -- CPU_FREQ
395 sysfreq => 25000, -- CPU_FREQ
395 rmap => 1,
396 rmap => 1,
396 rmapcrc => 1,
397 rmapcrc => 1,
397 fifosize1 => 16,
398 fifosize1 => 16,
398 fifosize2 => 16,
399 fifosize2 => 16,
399 rxclkbuftype => 1,
400 rxclkbuftype => 1,
400 rxunaligned => 0,
401 rxunaligned => 0,
401 rmapbufs => 4,
402 rmapbufs => 4,
402 ft => 1,
403 ft => 1,
403 netlist => 0,
404 netlist => 0,
404 ports => 2,
405 ports => 2,
405 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
406 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
406 memtech => axcel,--inferred,--tech_leon,
407 memtech => axcel,--inferred,--tech_leon,
407 destkey => 2,
408 destkey => 2,
408 spwcore => 1
409 spwcore => 1
409 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
410 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
410 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
411 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
411 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
412 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
412 )
413 )
413 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
414 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
414 spw_rxclk(1),
415 spw_rxclk(1),
415 clk50MHz_int,
416 clk50MHz_int,
416 clk50MHz_int,
417 clk50MHz_int,
417 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
418 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
418 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
419 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
419 swni, swno);
420 swni, swno);
420
421
421 swni.tickin <= '0';
422 swni.tickin <= '0';
422 swni.rmapen <= '1';
423 swni.rmapen <= '1';
423 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
424 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
424 swni.tickinraw <= '0';
425 swni.tickinraw <= '0';
425 swni.timein <= (OTHERS => '0');
426 swni.timein <= (OTHERS => '0');
426 swni.dcrstval <= (OTHERS => '0');
427 swni.dcrstval <= (OTHERS => '0');
427 swni.timerrstval <= (OTHERS => '0');
428 swni.timerrstval <= (OTHERS => '0');
428
429
429 -------------------------------------------------------------------------------
430 -------------------------------------------------------------------------------
430 -- LFR ------------------------------------------------------------------------
431 -- LFR ------------------------------------------------------------------------
431 -------------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
432 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
433 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
433 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
434 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
434
435
435 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
436 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
436
437
437 lpp_lfr_1 : lpp_lfr
438 lpp_lfr_1 : lpp_lfr
438 GENERIC MAP (
439 GENERIC MAP (
439 Mem_use => Mem_use,
440 Mem_use => Mem_use,
440 tech => inferred,--tech,
441 tech => inferred,--tech,
441 nb_data_by_buffer_size => 32,
442 nb_data_by_buffer_size => 32,
442 --nb_word_by_buffer_size => 30,
443 --nb_word_by_buffer_size => 30,
443 nb_snapshot_param_size => 32,
444 nb_snapshot_param_size => 32,
444 delta_vector_size => 32,
445 delta_vector_size => 32,
445 delta_vector_size_f0_2 => 7, -- log2(96)
446 delta_vector_size_f0_2 => 7, -- log2(96)
446 pindex => 15,
447 pindex => 15,
447 paddr => 15,
448 paddr => 15,
448 pmask => 16#fff#,
449 pmask => 16#fff#,
449 pirq_ms => 6,
450 pirq_ms => 6,
450 pirq_wfp => 14,
451 pirq_wfp => 14,
451 hindex => 2,
452 hindex => 2,
452 top_lfr_version => X"030159", -- aa.bb.cc version
453 top_lfr_version => X"030159", -- aa.bb.cc version
453 -- AA : BOARD NUMBER
454 -- AA : BOARD NUMBER
454 -- 0 => MINI_LFR
455 -- 0 => MINI_LFR
455 -- 1 => EM
456 -- 1 => EM
456 -- 2 => EQM (with A3PE3000)
457 -- 2 => EQM (with A3PE3000)
457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
458 RTL_DESIGN_LIGHT =>0,
459 RTL_DESIGN_LIGHT =>0,
459 WINDOWS_HAANNING_PARAM_SIZE => 15)
460 WINDOWS_HAANNING_PARAM_SIZE => 15)
460 PORT MAP (
461 PORT MAP (
461 clk => clk_25,
462 clk => clk_25,
462 rstn => LFR_rstn,
463 rstn => LFR_rstn,
463 sample_B => sample_s(2 DOWNTO 0),
464 sample_B => sample_s(2 DOWNTO 0),
464 sample_E => sample_s(7 DOWNTO 3),
465 sample_E => sample_s(7 DOWNTO 3),
465 sample_val => sample_val,
466 sample_val => sample_val,
466 apbi => apbi_ext,
467 apbi => apbi_ext,
467 apbo => apbo_ext(15),
468 apbo => apbo_ext(15),
468 ahbi => ahbi_m_ext,
469 ahbi => ahbi_m_ext,
469 ahbo => ahbo_m_ext(2),
470 ahbo => ahbo_m_ext(2),
470 coarse_time => coarse_time,
471 coarse_time => coarse_time,
471 fine_time => fine_time,
472 fine_time => fine_time,
472 data_shaping_BW => bias_fail_sw,
473 data_shaping_BW => bias_fail_sw,
473 debug_vector => debug_vector,
474 debug_vector => debug_vector,
474 debug_vector_ms => OPEN); --,
475 debug_vector_ms => OPEN); --,
475 --observation_vector_0 => OPEN,
476 --observation_vector_0 => OPEN,
476 --observation_vector_1 => OPEN,
477 --observation_vector_1 => OPEN,
477 --observation_reg => observation_reg);
478 --observation_reg => observation_reg);
478
479
479
480
480 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
481 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
481 sample_s(I) <= sample(I) & '0' & '0';
482 sample_s(I) <= sample(I) & '0' & '0';
482 END GENERATE all_sample;
483 END GENERATE all_sample;
483 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
484 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
484
485
485 -----------------------------------------------------------------------------
486 -----------------------------------------------------------------------------
486 --
487 --
487 -----------------------------------------------------------------------------
488 -----------------------------------------------------------------------------
488 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
489 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
489 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
490 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
490 GENERIC MAP (
491 GENERIC MAP (
491 ChanelCount => 9,
492 ChanelCount => 9,
492 ncycle_cnv_high => 12,
493 ncycle_cnv_high => 12,
493 ncycle_cnv => 25,
494 ncycle_cnv => 25,
494 FILTER_ENABLED => 16#FF#)
495 FILTER_ENABLED => 16#FF#)
495 PORT MAP (
496 PORT MAP (
496 cnv_clk => clk_24,
497 cnv_clk => clk_24,
497 cnv_rstn => rstn_24,
498 cnv_rstn => rstn_24,
498 cnv => ADC_smpclk_s,
499 cnv => ADC_smpclk_s,
499 clk => clk_25,
500 clk => clk_25,
500 rstn => rstn_25,
501 rstn => rstn_25,
501 ADC_data => ADC_data,
502 ADC_data => ADC_data,
502 ADC_nOE => ADC_OEB_bar_CH_s,
503 ADC_nOE => ADC_OEB_bar_CH_s,
503 sample => sample,
504 sample => sample,
504 sample_val => sample_val);
505 sample_val => sample_val);
505
506
506 END GENERATE USE_ADCDRIVER_true;
507 END GENERATE USE_ADCDRIVER_true;
507
508
508 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
509 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
509 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
510 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
510 GENERIC MAP (
511 GENERIC MAP (
511 ChanelCount => 9,
512 ChanelCount => 9,
512 ncycle_cnv_high => 25,
513 ncycle_cnv_high => 25,
513 ncycle_cnv => 50,
514 ncycle_cnv => 50,
514 FILTER_ENABLED => 16#FF#)
515 FILTER_ENABLED => 16#FF#)
515 PORT MAP (
516 PORT MAP (
516 cnv_clk => clk_24,
517 cnv_clk => clk_24,
517 cnv_rstn => rstn_24,
518 cnv_rstn => rstn_24,
518 cnv => ADC_smpclk_s,
519 cnv => ADC_smpclk_s,
519 clk => clk_25,
520 clk => clk_25,
520 rstn => rstn_25,
521 rstn => rstn_25,
521 ADC_data => ADC_data,
522 ADC_data => ADC_data,
522 ADC_nOE => OPEN,
523 ADC_nOE => OPEN,
523 sample => OPEN,
524 sample => OPEN,
524 sample_val => sample_val);
525 sample_val => sample_val);
525
526
526 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
527 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
527
528
528 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
529 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
529 ramp_generator_1: ramp_generator
530 ramp_generator_1: ramp_generator
530 GENERIC MAP (
531 GENERIC MAP (
531 DATA_SIZE => 14,
532 DATA_SIZE => 14,
532 VALUE_UNSIGNED_INIT => 2**I,
533 VALUE_UNSIGNED_INIT => 2**I,
533 VALUE_UNSIGNED_INCR => 0,
534 VALUE_UNSIGNED_INCR => 0,
534 VALUE_UNSIGNED_MASK => 16#3FFF#)
535 VALUE_UNSIGNED_MASK => 16#3FFF#)
535 PORT MAP (
536 PORT MAP (
536 clk => clk_25,
537 clk => clk_25,
537 rstn => rstn_25,
538 rstn => rstn_25,
538 new_data => sample_val,
539 new_data => sample_val,
539 output_data => sample(I) );
540 output_data => sample(I) );
540 END GENERATE all_sample;
541 END GENERATE all_sample;
541
542
542
543
543 END GENERATE USE_ADCDRIVER_false;
544 END GENERATE USE_ADCDRIVER_false;
544
545
545
546
546
547
547
548
548 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
549 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
549
550
550 ADC_smpclk <= ADC_smpclk_s;
551 ADC_smpclk <= ADC_smpclk_s;
551 HK_smpclk <= ADC_smpclk_s;
552 HK_smpclk <= ADC_smpclk_s;
552
553
553
554
554 -----------------------------------------------------------------------------
555 -----------------------------------------------------------------------------
555 -- HK
556 -- HK
556 -----------------------------------------------------------------------------
557 -----------------------------------------------------------------------------
557 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
558 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
558
559
559 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
560 --
561 --
561 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
562 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
563 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
563 -- lpp_bootloader_1: lpp_bootloader
564 -- lpp_bootloader_1: lpp_bootloader
564 -- GENERIC MAP (
565 -- GENERIC MAP (
565 -- pindex => 13,
566 -- pindex => 13,
566 -- paddr => 13,
567 -- paddr => 13,
567 -- pmask => 16#fff#,
568 -- pmask => 16#fff#,
568 -- hindex => 3,
569 -- hindex => 3,
569 -- haddr => 0,
570 -- haddr => 0,
570 -- hmask => 16#fff#)
571 -- hmask => 16#fff#)
571 -- PORT MAP (
572 -- PORT MAP (
572 -- HCLK => clk_25,
573 -- HCLK => clk_25,
573 -- HRESETn => rstn_25,
574 -- HRESETn => rstn_25,
574 -- apbi => apbi_ext,
575 -- apbi => apbi_ext,
575 -- apbo => apbo_ext(13),
576 -- apbo => apbo_ext(13),
576 -- ahbsi => ahbi_s_ext,
577 -- ahbsi => ahbi_s_ext,
577 -- ahbso => ahbo_s_ext(3));
578 -- ahbso => ahbo_s_ext(3));
578 --END GENERATE inst_bootloader;
579 --END GENERATE inst_bootloader;
579
580
580 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
581 --
582 --
582 -----------------------------------------------------------------------------
583 -----------------------------------------------------------------------------
583 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
584 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
584 PROCESS (clk_25, rstn_25)
585 PROCESS (clk_25, rstn_25)
585 BEGIN -- PROCESS
586 BEGIN -- PROCESS
586 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 TAG <= (OTHERS => '0');
588 TAG <= (OTHERS => '0');
588 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
589 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
589 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
590 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
590 END IF;
591 END IF;
591 END PROCESS;
592 END PROCESS;
592
593
593
594
594 END GENERATE USE_DEBUG_VECTOR_IF;
595 END GENERATE USE_DEBUG_VECTOR_IF;
595
596
596 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
597 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
597 --ahbrxd <= TAG(1); -- AHB UART
598 --ahbrxd <= TAG(1); -- AHB UART
598 --TAG(3) <= ahbtxd;
599 --TAG(3) <= ahbtxd;
599
600
600 urxd1 <= TAG(2); -- APB UART
601 urxd1 <= TAG(2); -- APB UART
601 TAG(4) <= utxd1;
602 TAG(4) <= utxd1;
602 --TAG(8) <= nSRAM_BUSY;
603 --TAG(8) <= nSRAM_BUSY;
603 END GENERATE USE_DEBUG_VECTOR_IF2;
604 END GENERATE USE_DEBUG_VECTOR_IF2;
604
605
605 END beh; No newline at end of file
606 END beh;
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@@ -1,488 +1,490
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 TAG8 : OUT STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
97 );
98
98
99 END LFR_em;
99 END LFR_em;
100
100
101
101
102 ARCHITECTURE beh OF LFR_em IS
102 ARCHITECTURE beh OF LFR_em IS
103
103
104 --==========================================================================
104 --==========================================================================
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 -- when enabled, chip enable polarity should be reversed and bank size also
106 -- when enabled, chip enable polarity should be reversed and bank size also
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 --==========================================================================
109 --==========================================================================
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 --==========================================================================
111 --==========================================================================
112
112
113 SIGNAL clk_50_s : STD_LOGIC := '0';
113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119
119
120 -- CONSTANTS
120 -- CONSTANTS
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125
125
126 SIGNAL apbi_ext : apb_slv_in_type;
126 SIGNAL apbi_ext : apb_slv_in_type;
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132
132
133 -- Spacewire signals
133 -- Spacewire signals
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
140 SIGNAL swni : grspw_in_type;
140 SIGNAL swni : grspw_in_type;
141 SIGNAL swno : grspw_out_type;
141 SIGNAL swno : grspw_out_type;
142
142
143 --GPIO
143 --GPIO
144 SIGNAL gpioi : gpio_in_type;
144 SIGNAL gpioi : gpio_in_type;
145 SIGNAL gpioo : gpio_out_type;
145 SIGNAL gpioo : gpio_out_type;
146
146
147 -- AD Converter ADS7886
147 -- AD Converter ADS7886
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 SIGNAL sample_val : STD_LOGIC;
150 SIGNAL sample_val : STD_LOGIC;
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
157 SIGNAL rstn_25 : STD_LOGIC;
157 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
159
159
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
162
162
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 ----------------------------------------------------------------------------
164 ----------------------------------------------------------------------------
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_READY : STD_LOGIC;
166 SIGNAL nSRAM_READY : STD_LOGIC;
167 SIGNAL SRAM_MBE : STD_LOGIC;
167
168
168 BEGIN -- beh
169 BEGIN -- beh
169
170
170 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
171 -- CLK
172 -- CLK
172 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175
176
176 PROCESS(clk100MHz)
177 PROCESS(clk100MHz)
177 BEGIN
178 BEGIN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 clk_50_s <= NOT clk_50_s;
180 clk_50_s <= NOT clk_50_s;
180 END IF;
181 END IF;
181 END PROCESS;
182 END PROCESS;
182
183
183 PROCESS(clk_50_s)
184 PROCESS(clk_50_s)
184 BEGIN
185 BEGIN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 clk_25 <= NOT clk_25;
187 clk_25 <= NOT clk_25;
187 END IF;
188 END IF;
188 END PROCESS;
189 END PROCESS;
189
190
190 PROCESS(clk49_152MHz)
191 PROCESS(clk49_152MHz)
191 BEGIN
192 BEGIN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 clk_24 <= NOT clk_24;
194 clk_24 <= NOT clk_24;
194 END IF;
195 END IF;
195 END PROCESS;
196 END PROCESS;
196
197
197 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
198
199
199 PROCESS (clk_25, rstn_25)
200 PROCESS (clk_25, rstn_25)
200 BEGIN -- PROCESS
201 BEGIN -- PROCESS
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 led(0) <= '0';
203 led(0) <= '0';
203 led(1) <= '0';
204 led(1) <= '0';
204 led(2) <= '0';
205 led(2) <= '0';
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 led(0) <= '0';
207 led(0) <= '0';
207 led(1) <= '1';
208 led(1) <= '1';
208 led(2) <= '1';
209 led(2) <= '1';
209 END IF;
210 END IF;
210 END PROCESS;
211 END PROCESS;
211
212
212 --
213 --
213 leon3_soc_1 : leon3_soc
214 leon3_soc_1 : leon3_soc
214 GENERIC MAP (
215 GENERIC MAP (
215 fabtech => apa3e,
216 fabtech => apa3e,
216 memtech => apa3e,
217 memtech => apa3e,
217 padtech => inferred,
218 padtech => inferred,
218 clktech => inferred,
219 clktech => inferred,
219 disas => 0,
220 disas => 0,
220 dbguart => 0,
221 dbguart => 0,
221 pclow => 2,
222 pclow => 2,
222 clk_freq => 25000,
223 clk_freq => 25000,
223 IS_RADHARD => 0,
224 IS_RADHARD => 0,
224 NB_CPU => 1,
225 NB_CPU => 1,
225 ENABLE_FPU => 1,
226 ENABLE_FPU => 1,
226 FPU_NETLIST => 0,
227 FPU_NETLIST => 0,
227 ENABLE_DSU => 1,
228 ENABLE_DSU => 1,
228 ENABLE_AHB_UART => 0,
229 ENABLE_AHB_UART => 0,
229 ENABLE_APB_UART => 1,
230 ENABLE_APB_UART => 1,
230 ENABLE_IRQMP => 1,
231 ENABLE_IRQMP => 1,
231 ENABLE_GPT => 1,
232 ENABLE_GPT => 1,
232 NB_AHB_MASTER => NB_AHB_MASTER,
233 NB_AHB_MASTER => NB_AHB_MASTER,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
235 NB_APB_SLAVE => NB_APB_SLAVE,
235 ADDRESS_SIZE => 20,
236 ADDRESS_SIZE => 20,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
238 USES_MBE_PIN => 0,
237 BYPASS_EDAC_MEMCTRLR => '0',
239 BYPASS_EDAC_MEMCTRLR => '0',
238 SRBANKSZ => 9)
240 SRBANKSZ => 9)
239 PORT MAP (
241 PORT MAP (
240 clk => clk_25,
242 clk => clk_25,
241 reset => rstn_25,
243 reset => rstn_25,
242 errorn => OPEN,
244 errorn => OPEN,
243
245
244 ahbrxd => TAG1,
246 ahbrxd => TAG1,
245 ahbtxd => TAG3,
247 ahbtxd => TAG3,
246 urxd1 => TAG2,
248 urxd1 => TAG2,
247 utxd1 => TAG4,
249 utxd1 => TAG4,
248
250
249 address => address,
251 address => address,
250 data => data,
252 data => data,
251 nSRAM_BE0 => nSRAM_BE0,
253 nSRAM_BE0 => nSRAM_BE0,
252 nSRAM_BE1 => nSRAM_BE1,
254 nSRAM_BE1 => nSRAM_BE1,
253 nSRAM_BE2 => nSRAM_BE2,
255 nSRAM_BE2 => nSRAM_BE2,
254 nSRAM_BE3 => nSRAM_BE3,
256 nSRAM_BE3 => nSRAM_BE3,
255 nSRAM_WE => nSRAM_WE,
257 nSRAM_WE => nSRAM_WE,
256 nSRAM_CE => nSRAM_CE_s,
258 nSRAM_CE => nSRAM_CE_s,
257 nSRAM_OE => nSRAM_OE,
259 nSRAM_OE => nSRAM_OE,
258 nSRAM_READY => nSRAM_READY,
260 nSRAM_READY => nSRAM_READY,
259 SRAM_MBE => '0',
261 SRAM_MBE => SRAM_MBE,
260
262
261 apbi_ext => apbi_ext,
263 apbi_ext => apbi_ext,
262 apbo_ext => apbo_ext,
264 apbo_ext => apbo_ext,
263 ahbi_s_ext => ahbi_s_ext,
265 ahbi_s_ext => ahbi_s_ext,
264 ahbo_s_ext => ahbo_s_ext,
266 ahbo_s_ext => ahbo_s_ext,
265 ahbi_m_ext => ahbi_m_ext,
267 ahbi_m_ext => ahbi_m_ext,
266 ahbo_m_ext => ahbo_m_ext);
268 ahbo_m_ext => ahbo_m_ext);
267
269
268 PROCESS (clk_25, rstn_25)
270 PROCESS (clk_25, rstn_25)
269 BEGIN -- PROCESS
271 BEGIN -- PROCESS
270 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
271 nSRAM_READY <= '1';
273 nSRAM_READY <= '1';
272 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
274 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
273 nSRAM_READY <= '1';
275 nSRAM_READY <= '1';
274 END IF;
276 END IF;
275 END PROCESS;
277 END PROCESS;
276
278
277 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
279 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
278 nSRAM_CE <= not nSRAM_CE_s(0);
280 nSRAM_CE <= not nSRAM_CE_s(0);
279 END GENERATE;
281 END GENERATE;
280
282
281 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
283 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
282 nSRAM_CE <= nSRAM_CE_s(0);
284 nSRAM_CE <= nSRAM_CE_s(0);
283 END GENERATE;
285 END GENERATE;
284
286
285 -------------------------------------------------------------------------------
287 -------------------------------------------------------------------------------
286 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
288 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
287 -------------------------------------------------------------------------------
289 -------------------------------------------------------------------------------
288 apb_lfr_management_1 : apb_lfr_management
290 apb_lfr_management_1 : apb_lfr_management
289 GENERIC MAP (
291 GENERIC MAP (
290 tech => apa3e,
292 tech => apa3e,
291 pindex => 6,
293 pindex => 6,
292 paddr => 6,
294 paddr => 6,
293 pmask => 16#fff#,
295 pmask => 16#fff#,
294 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
296 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
295 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
297 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
296 PORT MAP (
298 PORT MAP (
297 clk25MHz => clk_25,
299 clk25MHz => clk_25,
298 resetn_25MHz => rstn_25, -- TODO
300 resetn_25MHz => rstn_25, -- TODO
299 -- clk24_576MHz => clk_24, -- 49.152MHz/2
301 -- clk24_576MHz => clk_24, -- 49.152MHz/2
300 -- resetn_24_576MHz => rstn_24, -- TODO
302 -- resetn_24_576MHz => rstn_24, -- TODO
301
303
302 grspw_tick => swno.tickout,
304 grspw_tick => swno.tickout,
303 apbi => apbi_ext,
305 apbi => apbi_ext,
304 apbo => apbo_ext(6),
306 apbo => apbo_ext(6),
305
307
306 HK_sample => sample_s(8),
308 HK_sample => sample_s(8),
307 HK_val => sample_val,
309 HK_val => sample_val,
308 HK_sel => HK_SEL,
310 HK_sel => HK_SEL,
309
311
310 DAC_SDO => DAC_SDO,
312 DAC_SDO => DAC_SDO,
311 DAC_SCK => DAC_SCK,
313 DAC_SCK => DAC_SCK,
312 DAC_SYNC => DAC_SYNC,
314 DAC_SYNC => DAC_SYNC,
313 DAC_CAL_EN => DAC_CAL_EN,
315 DAC_CAL_EN => DAC_CAL_EN,
314
316
315 coarse_time => coarse_time,
317 coarse_time => coarse_time,
316 fine_time => fine_time,
318 fine_time => fine_time,
317 LFR_soft_rstn => LFR_soft_rstn
319 LFR_soft_rstn => LFR_soft_rstn
318 );
320 );
319
321
320 -----------------------------------------------------------------------
322 -----------------------------------------------------------------------
321 --- SpaceWire --------------------------------------------------------
323 --- SpaceWire --------------------------------------------------------
322 -----------------------------------------------------------------------
324 -----------------------------------------------------------------------
323
325
324 -- SPW_EN <= '1';
326 -- SPW_EN <= '1';
325
327
326 spw_clk <= clk_50_s;
328 spw_clk <= clk_50_s;
327 spw_rxtxclk <= spw_clk;
329 spw_rxtxclk <= spw_clk;
328 spw_rxclkn <= NOT spw_rxtxclk;
330 spw_rxclkn <= NOT spw_rxtxclk;
329
331
330 -- PADS for SPW1
332 -- PADS for SPW1
331 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
333 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
332 PORT MAP (spw1_din, dtmp(0));
334 PORT MAP (spw1_din, dtmp(0));
333 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
335 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
334 PORT MAP (spw1_sin, stmp(0));
336 PORT MAP (spw1_sin, stmp(0));
335 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
337 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
336 PORT MAP (spw1_dout, swno.d(0));
338 PORT MAP (spw1_dout, swno.d(0));
337 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
339 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
338 PORT MAP (spw1_sout, swno.s(0));
340 PORT MAP (spw1_sout, swno.s(0));
339 -- PADS FOR SPW2
341 -- PADS FOR SPW2
340 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
342 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
341 PORT MAP (spw2_din, dtmp(1));
343 PORT MAP (spw2_din, dtmp(1));
342 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
344 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
343 PORT MAP (spw2_sin, stmp(1));
345 PORT MAP (spw2_sin, stmp(1));
344 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
346 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
345 PORT MAP (spw2_dout, swno.d(1));
347 PORT MAP (spw2_dout, swno.d(1));
346 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
348 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
347 PORT MAP (spw2_sout, swno.s(1));
349 PORT MAP (spw2_sout, swno.s(1));
348
350
349 -- GRSPW PHY
351 -- GRSPW PHY
350 --spw1_input: if CFG_SPW_GRSPW = 1 generate
352 --spw1_input: if CFG_SPW_GRSPW = 1 generate
351 spw_inputloop : FOR j IN 0 TO 1 GENERATE
353 spw_inputloop : FOR j IN 0 TO 1 GENERATE
352 spw_phy0 : grspw_phy
354 spw_phy0 : grspw_phy
353 GENERIC MAP(
355 GENERIC MAP(
354 tech => apa3e,
356 tech => apa3e,
355 rxclkbuftype => 1,
357 rxclkbuftype => 1,
356 scantest => 0)
358 scantest => 0)
357 PORT MAP(
359 PORT MAP(
358 rxrst => swno.rxrst,
360 rxrst => swno.rxrst,
359 di => dtmp(j),
361 di => dtmp(j),
360 si => stmp(j),
362 si => stmp(j),
361 rxclko => spw_rxclk(j),
363 rxclko => spw_rxclk(j),
362 do => swni.d(j),
364 do => swni.d(j),
363 ndo => swni.nd(j*5+4 DOWNTO j*5),
365 ndo => swni.nd(j*5+4 DOWNTO j*5),
364 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
366 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
365 END GENERATE spw_inputloop;
367 END GENERATE spw_inputloop;
366
368
367 -- SPW core
369 -- SPW core
368 sw0 : grspwm GENERIC MAP(
370 sw0 : grspwm GENERIC MAP(
369 tech => apa3e,
371 tech => apa3e,
370 hindex => 1,
372 hindex => 1,
371 pindex => 5,
373 pindex => 5,
372 paddr => 5,
374 paddr => 5,
373 pirq => 11,
375 pirq => 11,
374 sysfreq => 25000, -- CPU_FREQ
376 sysfreq => 25000, -- CPU_FREQ
375 rmap => 1,
377 rmap => 1,
376 rmapcrc => 1,
378 rmapcrc => 1,
377 fifosize1 => 16,
379 fifosize1 => 16,
378 fifosize2 => 16,
380 fifosize2 => 16,
379 rxclkbuftype => 1,
381 rxclkbuftype => 1,
380 rxunaligned => 0,
382 rxunaligned => 0,
381 rmapbufs => 4,
383 rmapbufs => 4,
382 ft => 0,
384 ft => 0,
383 netlist => 0,
385 netlist => 0,
384 ports => 2,
386 ports => 2,
385 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
387 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
386 memtech => apa3e,
388 memtech => apa3e,
387 destkey => 2,
389 destkey => 2,
388 spwcore => 1
390 spwcore => 1
389 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
391 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
390 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
392 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
391 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
393 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
392 )
394 )
393 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
395 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
394 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
396 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
395 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
397 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
396 swni, swno);
398 swni, swno);
397
399
398 swni.tickin <= '0';
400 swni.tickin <= '0';
399 swni.rmapen <= '1';
401 swni.rmapen <= '1';
400 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
402 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
401 swni.tickinraw <= '0';
403 swni.tickinraw <= '0';
402 swni.timein <= (OTHERS => '0');
404 swni.timein <= (OTHERS => '0');
403 swni.dcrstval <= (OTHERS => '0');
405 swni.dcrstval <= (OTHERS => '0');
404 swni.timerrstval <= (OTHERS => '0');
406 swni.timerrstval <= (OTHERS => '0');
405
407
406 -------------------------------------------------------------------------------
408 -------------------------------------------------------------------------------
407 -- LFR ------------------------------------------------------------------------
409 -- LFR ------------------------------------------------------------------------
408 -------------------------------------------------------------------------------
410 -------------------------------------------------------------------------------
409 LFR_rstn <= LFR_soft_rstn AND rstn_25;
411 LFR_rstn <= LFR_soft_rstn AND rstn_25;
410
412
411 lpp_lfr_1 : lpp_lfr
413 lpp_lfr_1 : lpp_lfr
412 GENERIC MAP (
414 GENERIC MAP (
413 Mem_use => use_RAM,
415 Mem_use => use_RAM,
414 tech => inferred,
416 tech => inferred,
415 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
416 --nb_word_by_buffer_size => 30,
418 --nb_word_by_buffer_size => 30,
417 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
418 delta_vector_size => 32,
420 delta_vector_size => 32,
419 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
420 pindex => 15,
422 pindex => 15,
421 paddr => 15,
423 paddr => 15,
422 pmask => 16#fff#,
424 pmask => 16#fff#,
423 pirq_ms => 6,
425 pirq_ms => 6,
424 pirq_wfp => 14,
426 pirq_wfp => 14,
425 hindex => 2,
427 hindex => 2,
426 top_lfr_version => X"010153", -- aa.bb.cc version
428 top_lfr_version => X"010153", -- aa.bb.cc version
427 -- AA : BOARD NUMBER
429 -- AA : BOARD NUMBER
428 -- 0 => MINI_LFR
430 -- 0 => MINI_LFR
429 -- 1 => EM
431 -- 1 => EM
430 DEBUG_FORCE_DATA_DMA => 0)
432 DEBUG_FORCE_DATA_DMA => 0)
431 PORT MAP (
433 PORT MAP (
432 clk => clk_25,
434 clk => clk_25,
433 rstn => LFR_rstn,
435 rstn => LFR_rstn,
434 sample_B => sample_s(2 DOWNTO 0),
436 sample_B => sample_s(2 DOWNTO 0),
435 sample_E => sample_s(7 DOWNTO 3),
437 sample_E => sample_s(7 DOWNTO 3),
436 sample_val => sample_val,
438 sample_val => sample_val,
437 apbi => apbi_ext,
439 apbi => apbi_ext,
438 apbo => apbo_ext(15),
440 apbo => apbo_ext(15),
439 ahbi => ahbi_m_ext,
441 ahbi => ahbi_m_ext,
440 ahbo => ahbo_m_ext(2),
442 ahbo => ahbo_m_ext(2),
441 coarse_time => coarse_time,
443 coarse_time => coarse_time,
442 fine_time => fine_time,
444 fine_time => fine_time,
443 data_shaping_BW => bias_fail_sw,
445 data_shaping_BW => bias_fail_sw,
444 debug_vector => OPEN,
446 debug_vector => OPEN,
445 debug_vector_ms => OPEN); --,
447 debug_vector_ms => OPEN); --,
446 --observation_vector_0 => OPEN,
448 --observation_vector_0 => OPEN,
447 --observation_vector_1 => OPEN,
449 --observation_vector_1 => OPEN,
448 --observation_reg => observation_reg);
450 --observation_reg => observation_reg);
449
451
450
452
451 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
453 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
452 sample_s(I) <= sample(I) & '0' & '0';
454 sample_s(I) <= sample(I) & '0' & '0';
453 END GENERATE all_sample;
455 END GENERATE all_sample;
454 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
456 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
455
457
456 -----------------------------------------------------------------------------
458 -----------------------------------------------------------------------------
457 --
459 --
458 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
459 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
461 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
460 GENERIC MAP (
462 GENERIC MAP (
461 ChanelCount => 9,
463 ChanelCount => 9,
462 ncycle_cnv_high => 12,
464 ncycle_cnv_high => 12,
463 ncycle_cnv => 25,
465 ncycle_cnv => 25,
464 FILTER_ENABLED => 16#FF#)
466 FILTER_ENABLED => 16#FF#)
465 PORT MAP (
467 PORT MAP (
466 cnv_clk => clk_24,
468 cnv_clk => clk_24,
467 cnv_rstn => rstn_24,
469 cnv_rstn => rstn_24,
468 cnv => ADC_smpclk_s,
470 cnv => ADC_smpclk_s,
469 clk => clk_25,
471 clk => clk_25,
470 rstn => rstn_25,
472 rstn => rstn_25,
471 ADC_data => ADC_data,
473 ADC_data => ADC_data,
472 ADC_nOE => ADC_OEB_bar_CH_s,
474 ADC_nOE => ADC_OEB_bar_CH_s,
473 sample => sample,
475 sample => sample,
474 sample_val => sample_val);
476 sample_val => sample_val);
475
477
476 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
478 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
477
479
478 ADC_smpclk <= ADC_smpclk_s;
480 ADC_smpclk <= ADC_smpclk_s;
479 HK_smpclk <= ADC_smpclk_s;
481 HK_smpclk <= ADC_smpclk_s;
480
482
481 TAG8 <= ADC_smpclk_s;
483 TAG8 <= ADC_smpclk_s;
482
484
483 -----------------------------------------------------------------------------
485 -----------------------------------------------------------------------------
484 -- HK
486 -- HK
485 -----------------------------------------------------------------------------
487 -----------------------------------------------------------------------------
486 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
488 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
487
489
488 END beh;
490 END beh;
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@@ -1,58 +1,53
1 #GRLIB=../..
2 VHDLIB=../..
1 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
4 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
5 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
10 EFFORT=high
12 XSTOPT=
11 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
13 VHDLSYNFILES=LFR-em.vhd
17 VHDLSIMFILES=testbench.vhd
14 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
15
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
22
17
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25
20
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 CLEAN=soft-clean
22 CLEAN=soft-clean
28
23
29 TECHLIBS = proasic3e
24 TECHLIBS = proasic3e
30
25
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth
33
28
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 ./amba_lcd_16x2_ctrlr \
31 ./amba_lcd_16x2_ctrlr \
37 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_AMR \
38 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_balise \
39 ./general_purpose/lpp_delay \
34 ./general_purpose/lpp_delay \
40 ./lpp_bootloader \
35 ./lpp_bootloader \
41 ./dsp/lpp_fft_rtax \
36 ./dsp/lpp_fft_rtax \
42 ./lpp_uart \
37 ./lpp_uart \
43 ./lpp_usb \
38 ./lpp_usb \
44 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_sim/CY7C1061DV33 \
45
40
46 FILESKIP = i2cmst.vhd \
41 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
50 APB_FFT.vhd\
45 APB_FFT.vhd\
51 CoreFFT_simu.vhd \
46 CoreFFT_simu.vhd \
52 lpp_lfr_apbreg_simu.vhd
47 lpp_lfr_apbreg_simu.vhd
53
48
54 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/software/leon3/Makefile
50 include $(GRLIB)/software/leon3/Makefile
56
51
57 ################## project specific targets ##########################
52 ################## project specific targets ##########################
58
53
Show file before | Show file after | Hide comments
@@ -1,593 +1,601
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := axcel;--apa3e;
49 fabtech : INTEGER := axcel;--apa3e;
50 memtech : INTEGER := axcel;--apa3e;
50 memtech : INTEGER := axcel;--apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 1;
59 IS_RADHARD : INTEGER := 1;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 0;
63 FPU_NETLIST : INTEGER := 0;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 19;
74 ADDRESS_SIZE : INTEGER := 19;
75 USES_IAP_MEMCTRLR : INTEGER := 1;
75 USES_IAP_MEMCTRLR : INTEGER := 1;
76 USES_MBE_PIN : INTEGER := 1;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8;
78 SRBANKSZ : INTEGER := 8;
78 SLOW_TIMING_EMULATION : integer := 0
79 SLOW_TIMING_EMULATION : integer := 0
79
80
80 );
81 );
81 PORT (
82 PORT (
82 clk : IN STD_ULOGIC;
83 clk : IN STD_ULOGIC;
83 reset : IN STD_ULOGIC;
84 reset : IN STD_ULOGIC;
84
85
85 errorn : OUT STD_ULOGIC;
86 errorn : OUT STD_ULOGIC;
86
87
87 -- UART AHB ---------------------------------------------------------------
88 -- UART AHB ---------------------------------------------------------------
88 ahbrxd : IN STD_ULOGIC; -- DSU rx data
89 ahbrxd : IN STD_ULOGIC; -- DSU rx data
89 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
90 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
90
91
91 -- UART APB ---------------------------------------------------------------
92 -- UART APB ---------------------------------------------------------------
92 urxd1 : IN STD_ULOGIC; -- UART1 rx data
93 urxd1 : IN STD_ULOGIC; -- UART1 rx data
93 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
94 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
94
95
95 -- RAM --------------------------------------------------------------------
96 -- RAM --------------------------------------------------------------------
96 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
97 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
97 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 nSRAM_BE0 : OUT STD_LOGIC;
99 nSRAM_BE0 : OUT STD_LOGIC;
99 nSRAM_BE1 : OUT STD_LOGIC;
100 nSRAM_BE1 : OUT STD_LOGIC;
100 nSRAM_BE2 : OUT STD_LOGIC;
101 nSRAM_BE2 : OUT STD_LOGIC;
101 nSRAM_BE3 : OUT STD_LOGIC;
102 nSRAM_BE3 : OUT STD_LOGIC;
102 nSRAM_WE : OUT STD_LOGIC;
103 nSRAM_WE : OUT STD_LOGIC;
103 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
104 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
104 nSRAM_OE : OUT STD_LOGIC;
105 nSRAM_OE : OUT STD_LOGIC;
105 nSRAM_READY : IN STD_LOGIC;
106 nSRAM_READY : IN STD_LOGIC;
106 SRAM_MBE : INOUT STD_LOGIC;
107 SRAM_MBE : INOUT STD_LOGIC;
107 -- APB --------------------------------------------------------------------
108 -- APB --------------------------------------------------------------------
108 apbi_ext : OUT apb_slv_in_type;
109 apbi_ext : OUT apb_slv_in_type;
109 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
110 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
110 -- AHB_Slave --------------------------------------------------------------
111 -- AHB_Slave --------------------------------------------------------------
111 ahbi_s_ext : OUT ahb_slv_in_type;
112 ahbi_s_ext : OUT ahb_slv_in_type;
112 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
113 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
113 -- AHB_Master -------------------------------------------------------------
114 -- AHB_Master -------------------------------------------------------------
114 ahbi_m_ext : OUT AHB_Mst_In_Type;
115 ahbi_m_ext : OUT AHB_Mst_In_Type;
115 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
116 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
116
117
117 );
118 );
118 END;
119 END;
119
120
120 ARCHITECTURE Behavioral OF leon3_soc IS
121 ARCHITECTURE Behavioral OF leon3_soc IS
121
122
122 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
123 -- CONFIG -------------------------------------------------------------------
124 -- CONFIG -------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
125
126
126 -- Clock generator
127 -- Clock generator
127 CONSTANT CFG_CLKMUL : INTEGER := (1);
128 CONSTANT CFG_CLKMUL : INTEGER := (1);
128 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
129 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
129 CONSTANT CFG_OCLKDIV : INTEGER := (1);
130 CONSTANT CFG_OCLKDIV : INTEGER := (1);
130 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
131 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
131 -- LEON3 processor core
132 -- LEON3 processor core
132 CONSTANT CFG_LEON3 : INTEGER := 1;
133 CONSTANT CFG_LEON3 : INTEGER := 1;
133 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
134 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
134 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
135 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
135 CONSTANT CFG_V8 : INTEGER := 0;
136 CONSTANT CFG_V8 : INTEGER := 0;
136 CONSTANT CFG_MAC : INTEGER := 0;
137 CONSTANT CFG_MAC : INTEGER := 0;
137 CONSTANT CFG_SVT : INTEGER := 0;
138 CONSTANT CFG_SVT : INTEGER := 0;
138 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
139 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
139 CONSTANT CFG_LDDEL : INTEGER := (1);
140 CONSTANT CFG_LDDEL : INTEGER := (1);
140 CONSTANT CFG_NWP : INTEGER := (0);
141 CONSTANT CFG_NWP : INTEGER := (0);
141 CONSTANT CFG_PWD : INTEGER := 1*2;
142 CONSTANT CFG_PWD : INTEGER := 1*2;
142 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
143 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
143 -- 1*(8 + 16 * 0) => grfpu-light
144 -- 1*(8 + 16 * 0) => grfpu-light
144 -- 1*(8 + 16 * 1) => netlist
145 -- 1*(8 + 16 * 1) => netlist
145 -- 0*(8 + 16 * 0) => No FPU
146 -- 0*(8 + 16 * 0) => No FPU
146 -- 0*(8 + 16 * 1) => No FPU;
147 -- 0*(8 + 16 * 1) => No FPU;
147 CONSTANT CFG_ICEN : INTEGER := 1;
148 CONSTANT CFG_ICEN : INTEGER := 1;
148 CONSTANT CFG_ISETS : INTEGER := 1;
149 CONSTANT CFG_ISETS : INTEGER := 1;
149 CONSTANT CFG_ISETSZ : INTEGER := 4;
150 CONSTANT CFG_ISETSZ : INTEGER := 4;
150 CONSTANT CFG_ILINE : INTEGER := 4;
151 CONSTANT CFG_ILINE : INTEGER := 4;
151 CONSTANT CFG_IREPL : INTEGER := 0;
152 CONSTANT CFG_IREPL : INTEGER := 0;
152 CONSTANT CFG_ILOCK : INTEGER := 0;
153 CONSTANT CFG_ILOCK : INTEGER := 0;
153 CONSTANT CFG_ILRAMEN : INTEGER := 0;
154 CONSTANT CFG_ILRAMEN : INTEGER := 0;
154 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
155 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
155 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
156 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
156 CONSTANT CFG_DCEN : INTEGER := 1;
157 CONSTANT CFG_DCEN : INTEGER := 1;
157 CONSTANT CFG_DSETS : INTEGER := 1;
158 CONSTANT CFG_DSETS : INTEGER := 1;
158 CONSTANT CFG_DSETSZ : INTEGER := 4;
159 CONSTANT CFG_DSETSZ : INTEGER := 4;
159 CONSTANT CFG_DLINE : INTEGER := 4;
160 CONSTANT CFG_DLINE : INTEGER := 4;
160 CONSTANT CFG_DREPL : INTEGER := 0;
161 CONSTANT CFG_DREPL : INTEGER := 0;
161 CONSTANT CFG_DLOCK : INTEGER := 0;
162 CONSTANT CFG_DLOCK : INTEGER := 0;
162 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
163 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
163 CONSTANT CFG_DLRAMEN : INTEGER := 0;
164 CONSTANT CFG_DLRAMEN : INTEGER := 0;
164 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
165 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
165 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
166 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
166 CONSTANT CFG_MMUEN : INTEGER := 0;
167 CONSTANT CFG_MMUEN : INTEGER := 0;
167 CONSTANT CFG_ITLBNUM : INTEGER := 2;
168 CONSTANT CFG_ITLBNUM : INTEGER := 2;
168 CONSTANT CFG_DTLBNUM : INTEGER := 2;
169 CONSTANT CFG_DTLBNUM : INTEGER := 2;
169 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
170 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
170 CONSTANT CFG_TLB_REP : INTEGER := 1;
171 CONSTANT CFG_TLB_REP : INTEGER := 1;
171
172
172 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
173 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
173 CONSTANT CFG_ITBSZ : INTEGER := 0;
174 CONSTANT CFG_ITBSZ : INTEGER := 0;
174 CONSTANT CFG_ATBSZ : INTEGER := 0;
175 CONSTANT CFG_ATBSZ : INTEGER := 0;
175
176
176 -- AMBA settings
177 -- AMBA settings
177 CONSTANT CFG_DEFMST : INTEGER := (0);
178 CONSTANT CFG_DEFMST : INTEGER := (0);
178 CONSTANT CFG_RROBIN : INTEGER := 1;
179 CONSTANT CFG_RROBIN : INTEGER := 1;
179 CONSTANT CFG_SPLIT : INTEGER := 0;
180 CONSTANT CFG_SPLIT : INTEGER := 0;
180 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
181 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
181 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
182 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
182
183
183 -- DSU UART
184 -- DSU UART
184 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
185 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
185
186
186 -- LEON2 memory controller
187 -- LEON2 memory controller
187 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
188 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
188
189
189 -- UART 1
190 -- UART 1
190 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
191 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
191 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
192 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
192
193
193 -- LEON3 interrupt controller
194 -- LEON3 interrupt controller
194 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
195 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
195
196
196 -- Modular timer
197 -- Modular timer
197 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
198 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
198 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
199 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
199 CONSTANT CFG_GPT_SW : INTEGER := (8);
200 CONSTANT CFG_GPT_SW : INTEGER := (8);
200 CONSTANT CFG_GPT_TW : INTEGER := (32);
201 CONSTANT CFG_GPT_TW : INTEGER := (32);
201 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
202 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
202 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
203 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
203 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
204 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
204 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
205 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
205 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
206
207
207 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
208 -- SIGNALs
209 -- SIGNALs
209 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
210 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
211 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
211 -- CLK & RST --
212 -- CLK & RST --
212 SIGNAL clk2x : STD_ULOGIC;
213 SIGNAL clk2x : STD_ULOGIC;
213 SIGNAL clkmn : STD_ULOGIC;
214 SIGNAL clkmn : STD_ULOGIC;
214 SIGNAL clkm : STD_ULOGIC;
215 SIGNAL clkm : STD_ULOGIC;
215 SIGNAL rstn : STD_ULOGIC;
216 SIGNAL rstn : STD_ULOGIC;
216 SIGNAL rstraw : STD_ULOGIC;
217 SIGNAL rstraw : STD_ULOGIC;
217 SIGNAL pciclk : STD_ULOGIC;
218 SIGNAL pciclk : STD_ULOGIC;
218 SIGNAL sdclkl : STD_ULOGIC;
219 SIGNAL sdclkl : STD_ULOGIC;
219 SIGNAL cgi : clkgen_in_type;
220 SIGNAL cgi : clkgen_in_type;
220 SIGNAL cgo : clkgen_out_type;
221 SIGNAL cgo : clkgen_out_type;
221 --- AHB / APB
222 --- AHB / APB
222 SIGNAL apbi : apb_slv_in_type;
223 SIGNAL apbi : apb_slv_in_type;
223 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
224 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
224 SIGNAL ahbsi : ahb_slv_in_type;
225 SIGNAL ahbsi : ahb_slv_in_type;
225 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
226 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
226 SIGNAL ahbmi : ahb_mst_in_type;
227 SIGNAL ahbmi : ahb_mst_in_type;
227 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
228 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
228 --UART
229 --UART
229 SIGNAL ahbuarti : uart_in_type;
230 SIGNAL ahbuarti : uart_in_type;
230 SIGNAL ahbuarto : uart_out_type;
231 SIGNAL ahbuarto : uart_out_type;
231 SIGNAL apbuarti : uart_in_type;
232 SIGNAL apbuarti : uart_in_type;
232 SIGNAL apbuarto : uart_out_type;
233 SIGNAL apbuarto : uart_out_type;
233 --MEM CTRLR
234 --MEM CTRLR
234 SIGNAL memi : memory_in_type;
235 SIGNAL memi : memory_in_type;
235 SIGNAL memo : memory_out_type;
236 SIGNAL memo : memory_out_type;
236 SIGNAL wpo : wprot_out_type;
237 SIGNAL wpo : wprot_out_type;
237 SIGNAL sdo : sdram_out_type;
238 SIGNAL sdo : sdram_out_type;
238 SIGNAL mbe : STD_LOGIC; -- enable memory programming
239 SIGNAL mbe : STD_LOGIC; -- enable memory programming
239 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
240 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
240 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
241 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
241 SIGNAL nSRAM_OE_s : STD_LOGIC;
242 SIGNAL nSRAM_OE_s : STD_LOGIC;
242 --IRQ
243 --IRQ
243 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
244 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
244 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
245 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
245 --Timer
246 --Timer
246 SIGNAL gpti : gptimer_in_type;
247 SIGNAL gpti : gptimer_in_type;
247 SIGNAL gpto : gptimer_out_type;
248 SIGNAL gpto : gptimer_out_type;
248 --DSU
249 --DSU
249 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
250 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
250 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
251 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
251 SIGNAL dsui : dsu_in_type;
252 SIGNAL dsui : dsu_in_type;
252 SIGNAL dsuo : dsu_out_type;
253 SIGNAL dsuo : dsu_out_type;
253 -----------------------------------------------------------------------------
254 -----------------------------------------------------------------------------
254 SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
256
257
257 BEGIN
258 BEGIN
258
259
259
260
260 ----------------------------------------------------------------------
261 ----------------------------------------------------------------------
261 --- Reset and Clock generation -------------------------------------
262 --- Reset and Clock generation -------------------------------------
262 ----------------------------------------------------------------------
263 ----------------------------------------------------------------------
263
264
264 cgi.pllctrl <= "00";
265 cgi.pllctrl <= "00";
265 cgi.pllrst <= rstraw;
266 cgi.pllrst <= rstraw;
266
267
267 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
268 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
268
269
269 clkgen0 : clkgen -- clock generator
270 clkgen0 : clkgen -- clock generator
270 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
271 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
271 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
272 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
272 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
273 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
273
274
274 ----------------------------------------------------------------------
275 ----------------------------------------------------------------------
275 --- LEON3 processor / DSU / IRQ ------------------------------------
276 --- LEON3 processor / DSU / IRQ ------------------------------------
276 ----------------------------------------------------------------------
277 ----------------------------------------------------------------------
277
278
278 l3 : IF CFG_LEON3 = 1 GENERATE
279 l3 : IF CFG_LEON3 = 1 GENERATE
279 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
280 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
280 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
281 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
281 u0 : leon3s -- LEON3 processor
282 u0 : leon3s -- LEON3 processor
282 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
283 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
283 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
284 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
284 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
285 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
285 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
286 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
286 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
287 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
287 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
288 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
288 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
289 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
289 irqi(i), irqo(i), dbgi(i), dbgo(i));
290 irqi(i), irqo(i), dbgi(i), dbgo(i));
290 END GENERATE leon3_non_radhard;
291 END GENERATE leon3_non_radhard;
291
292
292 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
293 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
293 cpu : leon3ft
294 cpu : leon3ft
294 GENERIC MAP (
295 GENERIC MAP (
295 HINDEX => i, --: integer; --CPU_HINDEX,
296 HINDEX => i, --: integer; --CPU_HINDEX,
296 FABTECH => fabtech, --CFG_TECH,
297 FABTECH => fabtech, --CFG_TECH,
297 MEMTECH => memtech, --CFG_TECH,
298 MEMTECH => memtech, --CFG_TECH,
298 NWINDOWS => CFG_NWIN, --CFG_NWIN,
299 NWINDOWS => CFG_NWIN, --CFG_NWIN,
299 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
300 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
300 FPU => CFG_FPU, --CFG_FPU,
301 FPU => CFG_FPU, --CFG_FPU,
301 V8 => CFG_V8, --CFG_V8,
302 V8 => CFG_V8, --CFG_V8,
302 CP => 0, --CFG_CP,
303 CP => 0, --CFG_CP,
303 MAC => CFG_MAC, --CFG_MAC,
304 MAC => CFG_MAC, --CFG_MAC,
304 PCLOW => pclow, --CFG_PCLOW,
305 PCLOW => pclow, --CFG_PCLOW,
305 NOTAG => 0, --CFG_NOTAG,
306 NOTAG => 0, --CFG_NOTAG,
306 NWP => CFG_NWP, --CFG_NWP,
307 NWP => CFG_NWP, --CFG_NWP,
307 ICEN => CFG_ICEN, --CFG_ICEN,
308 ICEN => CFG_ICEN, --CFG_ICEN,
308 IREPL => CFG_IREPL, --CFG_IREPL,
309 IREPL => CFG_IREPL, --CFG_IREPL,
309 ISETS => CFG_ISETS, --CFG_ISETS,
310 ISETS => CFG_ISETS, --CFG_ISETS,
310 ILINESIZE => CFG_ILINE, --CFG_ILINE,
311 ILINESIZE => CFG_ILINE, --CFG_ILINE,
311 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
312 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
312 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
313 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
313 DCEN => CFG_DCEN, --CFG_DCEN,
314 DCEN => CFG_DCEN, --CFG_DCEN,
314 DREPL => CFG_DREPL, --CFG_DREPL,
315 DREPL => CFG_DREPL, --CFG_DREPL,
315 DSETS => CFG_DSETS, --CFG_DSETS,
316 DSETS => CFG_DSETS, --CFG_DSETS,
316 DLINESIZE => CFG_DLINE, --CFG_DLINE,
317 DLINESIZE => CFG_DLINE, --CFG_DLINE,
317 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
318 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
318 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
319 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
319 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
320 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
320 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
321 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
321 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
322 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
322 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
323 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
323 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
324 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
324 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
325 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
325 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
326 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
326 MMUEN => CFG_MMUEN, --CFG_MMUEN,
327 MMUEN => CFG_MMUEN, --CFG_MMUEN,
327 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
328 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
328 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
329 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
329 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
330 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
330 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
331 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
331 LDDEL => CFG_LDDEL, --CFG_LDDEL,
332 LDDEL => CFG_LDDEL, --CFG_LDDEL,
332 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
333 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
333 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
334 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
334 PWD => CFG_PWD, --CFG_PWD,
335 PWD => CFG_PWD, --CFG_PWD,
335 SVT => CFG_SVT, --CFG_SVT,
336 SVT => CFG_SVT, --CFG_SVT,
336 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
337 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
337 SMP => CFG_NCPU-1, --CFG_NCPU-1,
338 SMP => CFG_NCPU-1, --CFG_NCPU-1,
338 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
339 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
339 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
340 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
340 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
341 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
341 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
342 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
342 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
343 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
343 CACHED => 0, --: integer; --CFG_DFIXED,
344 CACHED => 0, --: integer; --CFG_DFIXED,
344 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
345 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
345 SCANTEST => 0, --: integer; --CFG_SCANTEST,
346 SCANTEST => 0, --: integer; --CFG_SCANTEST,
346 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
347 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
347 BP => 1) --CFG_BP
348 BP => 1) --CFG_BP
348 PORT MAP ( --
349 PORT MAP ( --
349 rstn => rstn, --rst_n,
350 rstn => rstn, --rst_n,
350 clk => clkm, --clk,
351 clk => clkm, --clk,
351 ahbi => ahbmi, --ahbmi,
352 ahbi => ahbmi, --ahbmi,
352 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
353 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
353 ahbsi => ahbsi, --ahbsi,
354 ahbsi => ahbsi, --ahbsi,
354 ahbso => ahbso, --ahbso,
355 ahbso => ahbso, --ahbso,
355 irqi => irqi(i), --irqi(CPU_HINDEX),
356 irqi => irqi(i), --irqi(CPU_HINDEX),
356 irqo => irqo(i), --irqo(CPU_HINDEX),
357 irqo => irqo(i), --irqo(CPU_HINDEX),
357 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
358 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
358 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
359 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
359 gclk => clkm --clk
360 gclk => clkm --clk
360 );
361 );
361 END GENERATE leon3_radhard_i;
362 END GENERATE leon3_radhard_i;
362
363
363 END GENERATE;
364 END GENERATE;
364 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
365 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
365
366
366 dsugen : IF CFG_DSU = 1 GENERATE
367 dsugen : IF CFG_DSU = 1 GENERATE
367 dsu0 : dsu3 -- LEON3 Debug Support Unit
368 dsu0 : dsu3 -- LEON3 Debug Support Unit
368 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
369 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
369 haddr => 16#900#, hmask => 16#F00#,
370 haddr => 16#900#, hmask => 16#F00#,
370 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
371 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
371 irq => 0, kbytes => CFG_ATBSZ)
372 irq => 0, kbytes => CFG_ATBSZ)
372 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
373 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
373 dbgo, dbgi, dsui, dsuo);
374 dbgo, dbgi, dsui, dsuo);
374 dsui.enable <= '1';
375 dsui.enable <= '1';
375 dsui.break <= '0';
376 dsui.break <= '0';
376 END GENERATE;
377 END GENERATE;
377 END GENERATE;
378 END GENERATE;
378
379
379 nodsu : IF CFG_DSU = 0 GENERATE
380 nodsu : IF CFG_DSU = 0 GENERATE
380 ahbso(0) <= ahbs_none;
381 ahbso(0) <= ahbs_none;
381 dsuo.tstop <= '0';
382 dsuo.tstop <= '0';
382 dsuo.active <= '0';
383 dsuo.active <= '0';
383 END GENERATE;
384 END GENERATE;
384
385
385 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
386 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
386 irqctrl0 : irqmp -- interrupt controller
387 irqctrl0 : irqmp -- interrupt controller
387 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
388 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
388 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
389 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
389 END GENERATE;
390 END GENERATE;
390 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
391 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
391 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
392 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
392 irqi(i).irl <= "0000";
393 irqi(i).irl <= "0000";
393 END GENERATE;
394 END GENERATE;
394 apbo(2) <= apb_none;
395 apbo(2) <= apb_none;
395 END GENERATE;
396 END GENERATE;
396
397
397 ----------------------------------------------------------------------
398 ----------------------------------------------------------------------
398 --- Memory controllers ---------------------------------------------
399 --- Memory controllers ---------------------------------------------
399 ----------------------------------------------------------------------
400 ----------------------------------------------------------------------
400 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
401 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
401 memctrlr : mctrl GENERIC MAP (
402 memctrlr : mctrl GENERIC MAP (
402 hindex => 2,
403 hindex => 2,
403 pindex => 0,
404 pindex => 0,
404 paddr => 0,
405 paddr => 0,
405 srbanks => 1
406 srbanks => 1
406 )
407 )
407 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
408 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
408 memi.bexcn <= '1';
409 memi.bexcn <= '1';
409 memi.brdyn <= '1';
410 memi.brdyn <= '1';
410
411
411 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
412 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
412 nSRAM_OE_s <= memo.ramoen(0);
413 nSRAM_OE_s <= memo.ramoen(0);
413 END GENERATE;
414 END GENERATE;
414
415
415 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
416 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
416 memctrlr : srctrle_0ws
417 memctrlr : srctrle_0ws
417 GENERIC MAP(
418 GENERIC MAP(
418 hindex => 2, -- TODO : hindex => 0
419 hindex => 2, -- TODO : hindex => 0
419 pindex => 0,
420 pindex => 0,
420 paddr => 0,
421 paddr => 0,
421 srbanks => 2,
422 srbanks => 2,
422 banksz => SRBANKSZ, --512k * 32
423 banksz => SRBANKSZ, --512k * 32
423 rmw => 1,
424 rmw => 1,
424 --Aeroflex memory generics:
425 --Aeroflex memory generics:
425 mbpedac => BYPASS_EDAC_MEMCTRLR,
426 mbpedac => BYPASS_EDAC_MEMCTRLR,
426 mprog => 1, -- program memory by default values after reset
427 mprog => 1, -- program memory by default values after reset
427 mpsrate => 15, -- default scrub rate period
428 mpsrate => 15, -- default scrub rate period
428 mpb2s => 14, -- default busy to scrub delay
429 mpb2s => 14, -- default busy to scrub delay
429 mpapb => 1, -- instantiate apb register
430 mpapb => 1, -- instantiate apb register
430 mchipcnt => 2,
431 mchipcnt => 2,
431 mpenall => 1 -- when 0 program only E1 chip, else program all dies
432 mpenall => 1 -- when 0 program only E1 chip, else program all dies
432 )
433 )
433 PORT MAP (
434 PORT MAP (
434 rst => rstn,
435 rst => rstn,
435 clk => clkm,
436 clk => clkm,
436 ahbsi => ahbsi,
437 ahbsi => ahbsi,
437 ahbso => ahbso(2), -- TODO :ahbso(0),
438 ahbso => ahbso(2), -- TODO :ahbso(0),
438 apbi => apbi,
439 apbi => apbi,
439 apbo => apbo(0),
440 apbo => apbo(0),
440 sri => memi,
441 sri => memi,
441 sro => memo,
442 sro => memo,
442 --Aeroflex memory signals:
443 --Aeroflex memory signals:
443 ucerr => OPEN, -- uncorrectable error signal
444 ucerr => OPEN, -- uncorrectable error signal
444 mbe => mbe, -- enable memory programming
445 mbe => mbe, -- enable memory programming
445 mbe_drive => mbe_drive -- drive the MBE memory signal
446 mbe_drive => mbe_drive -- drive the MBE memory signal
446 );
447 );
447
448
448 memi.brdyn <= nSRAM_READY;
449 memi.brdyn <= nSRAM_READY;
450
451 drv_mbe: IF USES_MBE_PIN = 1 GENERATE
452 mbe_pad : iopad
453 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
454 PORT MAP(pad => SRAM_MBE,
455 i => mbe,
456 en => mbe_drive,
457 o => memi.bexcn);
449
458
450 mbe_pad : iopad
459 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
451 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
460 nSRAM_OE_s <= memo.oen;
452 PORT MAP(pad => SRAM_MBE,
461 END GENERATE;
453 i => mbe,
462
454 en => mbe_drive,
463 no_drv_mbe: IF USES_MBE_PIN /= 1 GENERATE
455 o => memi.bexcn);
464 memi.bexcn <= '1';
456
465 END GENERATE;
457 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
466
458 nSRAM_OE_s <= memo.oen;
459
467
460 END GENERATE;
468 END GENERATE;
461
469
462
470
463 memi.writen <= '1';
471 memi.writen <= '1';
464 memi.wrn <= "1111";
472 memi.wrn <= "1111";
465 memi.bwidth <= "10";
473 memi.bwidth <= "10";
466
474
467 -----------------------------------------------------------------------------
475 -----------------------------------------------------------------------------
468 -- SLOW TIMING EMULATION
476 -- SLOW TIMING EMULATION
469 -----------------------------------------------------------------------------
477 -----------------------------------------------------------------------------
470 SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE
478 SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE
471 PROCESS (clkm, rstn)
479 PROCESS (clkm, rstn)
472 BEGIN -- PROCESS
480 BEGIN -- PROCESS
473 IF rstn = '0' THEN -- asynchronous reset (active low)
481 IF rstn = '0' THEN -- asynchronous reset (active low)
474 memi.data <= (OTHERS => '0');
482 memi.data <= (OTHERS => '0');
475 memo_data <= (OTHERS => '0');
483 memo_data <= (OTHERS => '0');
476 ELSIF clkm'event AND clkm = '1' THEN -- rising clock edge
484 ELSIF clkm'event AND clkm = '1' THEN -- rising clock edge
477 memi.data <= memi_data;
485 memi.data <= memi_data;
478 memo_data <= memo.data;
486 memo_data <= memo.data;
479 END IF;
487 END IF;
480 END PROCESS;
488 END PROCESS;
481 END GENERATE SLOW_TIMING_EMULATION_ON;
489 END GENERATE SLOW_TIMING_EMULATION_ON;
482 SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE
490 SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE
483 memi.data <= memi_data;
491 memi.data <= memi_data;
484 memo_data <= memo.data;
492 memo_data <= memo.data;
485 END GENERATE SLOW_TIMING_EMULATION_OFF;
493 END GENERATE SLOW_TIMING_EMULATION_OFF;
486
494
487 bdr : FOR i IN 0 TO 3 GENERATE
495 bdr : FOR i IN 0 TO 3 GENERATE
488 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
496 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
489 PORT MAP (
497 PORT MAP (
490 data(31-i*8 DOWNTO 24-i*8),
498 data(31-i*8 DOWNTO 24-i*8),
491 memo_data(31-i*8 DOWNTO 24-i*8),
499 memo_data(31-i*8 DOWNTO 24-i*8),
492 memo.bdrive(i),
500 memo.bdrive(i),
493 memi_data(31-i*8 DOWNTO 24-i*8));
501 memi_data(31-i*8 DOWNTO 24-i*8));
494 END GENERATE;
502 END GENERATE;
495 -----------------------------------------------------------------------------
503 -----------------------------------------------------------------------------
496
504
497 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
505 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
498 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
506 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
499 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
507 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
500 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
508 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
501 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
509 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
502 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
510 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
503 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
511 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
504 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
512 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
505 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
513 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
506
514
507 ----------------------------------------------------------------------
515 ----------------------------------------------------------------------
508 --- AHB CONTROLLER -------------------------------------------------
516 --- AHB CONTROLLER -------------------------------------------------
509 ----------------------------------------------------------------------
517 ----------------------------------------------------------------------
510 ahb0 : ahbctrl -- AHB arbiter/multiplexer
518 ahb0 : ahbctrl -- AHB arbiter/multiplexer
511 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
519 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
512 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
520 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
513 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
521 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
514 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
522 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
515
523
516 ----------------------------------------------------------------------
524 ----------------------------------------------------------------------
517 --- AHB UART -------------------------------------------------------
525 --- AHB UART -------------------------------------------------------
518 ----------------------------------------------------------------------
526 ----------------------------------------------------------------------
519 dcomgen : IF CFG_AHB_UART = 1 GENERATE
527 dcomgen : IF CFG_AHB_UART = 1 GENERATE
520 dcom0 : ahbuart
528 dcom0 : ahbuart
521 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
529 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
522 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
530 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
523 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
531 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
524 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
532 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
525 END GENERATE;
533 END GENERATE;
526 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
534 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
527
535
528 ----------------------------------------------------------------------
536 ----------------------------------------------------------------------
529 --- APB Bridge -----------------------------------------------------
537 --- APB Bridge -----------------------------------------------------
530 ----------------------------------------------------------------------
538 ----------------------------------------------------------------------
531 apb0 : apbctrl -- AHB/APB bridge
539 apb0 : apbctrl -- AHB/APB bridge
532 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
540 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
533 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
541 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
534
542
535 ----------------------------------------------------------------------
543 ----------------------------------------------------------------------
536 --- GPT Timer ------------------------------------------------------
544 --- GPT Timer ------------------------------------------------------
537 ----------------------------------------------------------------------
545 ----------------------------------------------------------------------
538 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
546 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
539 timer0 : gptimer -- timer unit
547 timer0 : gptimer -- timer unit
540 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
548 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
541 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
549 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
542 nbits => CFG_GPT_TW)
550 nbits => CFG_GPT_TW)
543 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
551 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
544 gpti.dhalt <= dsuo.tstop;
552 gpti.dhalt <= dsuo.tstop;
545 gpti.extclk <= '0';
553 gpti.extclk <= '0';
546 END GENERATE;
554 END GENERATE;
547 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
555 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
548
556
549
557
550 ----------------------------------------------------------------------
558 ----------------------------------------------------------------------
551 --- APB UART -------------------------------------------------------
559 --- APB UART -------------------------------------------------------
552 ----------------------------------------------------------------------
560 ----------------------------------------------------------------------
553 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
561 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
554 uart1 : apbuart -- UART 1
562 uart1 : apbuart -- UART 1
555 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
563 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
556 fifosize => CFG_UART1_FIFO)
564 fifosize => CFG_UART1_FIFO)
557 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
565 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
558 apbuarti.rxd <= urxd1;
566 apbuarti.rxd <= urxd1;
559 apbuarti.extclk <= '0';
567 apbuarti.extclk <= '0';
560 utxd1 <= apbuarto.txd;
568 utxd1 <= apbuarto.txd;
561 apbuarti.ctsn <= '0';
569 apbuarti.ctsn <= '0';
562 END GENERATE;
570 END GENERATE;
563 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
571 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
564
572
565 -------------------------------------------------------------------------------
573 -------------------------------------------------------------------------------
566 -- AMBA BUS -------------------------------------------------------------------
574 -- AMBA BUS -------------------------------------------------------------------
567 -------------------------------------------------------------------------------
575 -------------------------------------------------------------------------------
568
576
569 -- APB --------------------------------------------------------------------
577 -- APB --------------------------------------------------------------------
570 apbi_ext <= apbi;
578 apbi_ext <= apbi;
571 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
579 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
572 max_16_apb : IF I + 5 < 16 GENERATE
580 max_16_apb : IF I + 5 < 16 GENERATE
573 apbo(I+5) <= apbo_ext(I+5);
581 apbo(I+5) <= apbo_ext(I+5);
574 END GENERATE max_16_apb;
582 END GENERATE max_16_apb;
575 END GENERATE all_apb;
583 END GENERATE all_apb;
576 -- AHB_Slave --------------------------------------------------------------
584 -- AHB_Slave --------------------------------------------------------------
577 ahbi_s_ext <= ahbsi;
585 ahbi_s_ext <= ahbsi;
578 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
586 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
579 max_16_ahbs : IF I + 3 < 16 GENERATE
587 max_16_ahbs : IF I + 3 < 16 GENERATE
580 ahbso(I+3) <= ahbo_s_ext(I+3);
588 ahbso(I+3) <= ahbo_s_ext(I+3);
581 END GENERATE max_16_ahbs;
589 END GENERATE max_16_ahbs;
582 END GENERATE all_ahbs;
590 END GENERATE all_ahbs;
583 -- AHB_Master -------------------------------------------------------------
591 -- AHB_Master -------------------------------------------------------------
584 ahbi_m_ext <= ahbmi;
592 ahbi_m_ext <= ahbmi;
585 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
593 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
586 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
594 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
587 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
595 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
588 END GENERATE max_16_ahbm;
596 END GENERATE max_16_ahbm;
589 END GENERATE all_ahbm;
597 END GENERATE all_ahbm;
590
598
591
599
592
600
593 END Behavioral;
601 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,146 +1,147
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27
28 PACKAGE lpp_leon3_soc_pkg IS
28 PACKAGE lpp_leon3_soc_pkg IS
29
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
33
34 COMPONENT leon3_soc
34 COMPONENT leon3_soc
35 GENERIC (
35 GENERIC (
36 fabtech : INTEGER;
36 fabtech : INTEGER;
37 memtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
43 clk_freq : INTEGER;
44 IS_RADHARD : INTEGER;
44 IS_RADHARD : INTEGER;
45 NB_CPU : INTEGER;
45 NB_CPU : INTEGER;
46 ENABLE_FPU : INTEGER;
46 ENABLE_FPU : INTEGER;
47 FPU_NETLIST : INTEGER;
47 FPU_NETLIST : INTEGER;
48 ENABLE_DSU : INTEGER;
48 ENABLE_DSU : INTEGER;
49 ENABLE_AHB_UART : INTEGER;
49 ENABLE_AHB_UART : INTEGER;
50 ENABLE_APB_UART : INTEGER;
50 ENABLE_APB_UART : INTEGER;
51 ENABLE_IRQMP : INTEGER;
51 ENABLE_IRQMP : INTEGER;
52 ENABLE_GPT : INTEGER;
52 ENABLE_GPT : INTEGER;
53 NB_AHB_MASTER : INTEGER;
53 NB_AHB_MASTER : INTEGER;
54 NB_AHB_SLAVE : INTEGER;
54 NB_AHB_SLAVE : INTEGER;
55 NB_APB_SLAVE : INTEGER;
55 NB_APB_SLAVE : INTEGER;
56 ADDRESS_SIZE : INTEGER;
56 ADDRESS_SIZE : INTEGER;
57 USES_IAP_MEMCTRLR : INTEGER;
57 USES_IAP_MEMCTRLR : INTEGER;
58 USES_MBE_PIN : INTEGER:=1;
58 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 SRBANKSZ : INTEGER := 8;
60 SRBANKSZ : INTEGER := 8;
60 SLOW_TIMING_EMULATION : integer := 0
61 SLOW_TIMING_EMULATION : integer := 0
61 );
62 );
62 PORT (
63 PORT (
63 clk : IN STD_ULOGIC;
64 clk : IN STD_ULOGIC;
64 reset : IN STD_ULOGIC;
65 reset : IN STD_ULOGIC;
65
66
66 errorn : OUT STD_ULOGIC;
67 errorn : OUT STD_ULOGIC;
67
68
68 -- UART AHB ---------------------------------------------------------------
69 -- UART AHB ---------------------------------------------------------------
69 ahbrxd : IN STD_ULOGIC; -- DSU rx data
70 ahbrxd : IN STD_ULOGIC; -- DSU rx data
70 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
71 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
71
72
72 -- UART APB ---------------------------------------------------------------
73 -- UART APB ---------------------------------------------------------------
73 urxd1 : IN STD_ULOGIC; -- UART1 rx data
74 urxd1 : IN STD_ULOGIC; -- UART1 rx data
74 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
75 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
75
76
76 -- RAM --------------------------------------------------------------------
77 -- RAM --------------------------------------------------------------------
77 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
78 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
78 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 nSRAM_BE0 : OUT STD_LOGIC;
80 nSRAM_BE0 : OUT STD_LOGIC;
80 nSRAM_BE1 : OUT STD_LOGIC;
81 nSRAM_BE1 : OUT STD_LOGIC;
81 nSRAM_BE2 : OUT STD_LOGIC;
82 nSRAM_BE2 : OUT STD_LOGIC;
82 nSRAM_BE3 : OUT STD_LOGIC;
83 nSRAM_BE3 : OUT STD_LOGIC;
83 nSRAM_WE : OUT STD_LOGIC;
84 nSRAM_WE : OUT STD_LOGIC;
84 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
85 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
85 nSRAM_OE : OUT STD_LOGIC;
86 nSRAM_OE : OUT STD_LOGIC;
86 nSRAM_READY : IN STD_LOGIC;
87 nSRAM_READY : IN STD_LOGIC;
87 SRAM_MBE : INOUT STD_LOGIC;
88 SRAM_MBE : INOUT STD_LOGIC;
88 -- APB --------------------------------------------------------------------
89 -- APB --------------------------------------------------------------------
89 apbi_ext : OUT apb_slv_in_type;
90 apbi_ext : OUT apb_slv_in_type;
90 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
91 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
91 -- AHB_Slave --------------------------------------------------------------
92 -- AHB_Slave --------------------------------------------------------------
92 ahbi_s_ext : OUT ahb_slv_in_type;
93 ahbi_s_ext : OUT ahb_slv_in_type;
93 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
94 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
94 -- AHB_Master -------------------------------------------------------------
95 -- AHB_Master -------------------------------------------------------------
95 ahbi_m_ext : OUT AHB_Mst_In_Type;
96 ahbi_m_ext : OUT AHB_Mst_In_Type;
96 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
97 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
97 END COMPONENT;
98 END COMPONENT;
98
99
99
100
100 --COMPONENT leon3ft_soc
101 --COMPONENT leon3ft_soc
101 -- GENERIC (
102 -- GENERIC (
102 -- fabtech : INTEGER;
103 -- fabtech : INTEGER;
103 -- memtech : INTEGER;
104 -- memtech : INTEGER;
104 -- padtech : INTEGER;
105 -- padtech : INTEGER;
105 -- clktech : INTEGER;
106 -- clktech : INTEGER;
106 -- disas : INTEGER;
107 -- disas : INTEGER;
107 -- dbguart : INTEGER;
108 -- dbguart : INTEGER;
108 -- pclow : INTEGER;
109 -- pclow : INTEGER;
109 -- clk_freq : INTEGER;
110 -- clk_freq : INTEGER;
110 -- NB_CPU : INTEGER;
111 -- NB_CPU : INTEGER;
111 -- ENABLE_FPU : INTEGER;
112 -- ENABLE_FPU : INTEGER;
112 -- FPU_NETLIST : INTEGER;
113 -- FPU_NETLIST : INTEGER;
113 -- ENABLE_DSU : INTEGER;
114 -- ENABLE_DSU : INTEGER;
114 -- ENABLE_AHB_UART : INTEGER;
115 -- ENABLE_AHB_UART : INTEGER;
115 -- ENABLE_APB_UART : INTEGER;
116 -- ENABLE_APB_UART : INTEGER;
116 -- ENABLE_IRQMP : INTEGER;
117 -- ENABLE_IRQMP : INTEGER;
117 -- ENABLE_GPT : INTEGER;
118 -- ENABLE_GPT : INTEGER;
118 -- NB_AHB_MASTER : INTEGER;
119 -- NB_AHB_MASTER : INTEGER;
119 -- NB_AHB_SLAVE : INTEGER;
120 -- NB_AHB_SLAVE : INTEGER;
120 -- NB_APB_SLAVE : INTEGER);
121 -- NB_APB_SLAVE : INTEGER);
121 -- PORT (
122 -- PORT (
122 -- clk : IN STD_ULOGIC;
123 -- clk : IN STD_ULOGIC;
123 -- reset : IN STD_ULOGIC;
124 -- reset : IN STD_ULOGIC;
124 -- errorn : OUT STD_ULOGIC;
125 -- errorn : OUT STD_ULOGIC;
125 -- ahbrxd : IN STD_ULOGIC;
126 -- ahbrxd : IN STD_ULOGIC;
126 -- ahbtxd : OUT STD_ULOGIC;
127 -- ahbtxd : OUT STD_ULOGIC;
127 -- urxd1 : IN STD_ULOGIC;
128 -- urxd1 : IN STD_ULOGIC;
128 -- utxd1 : OUT STD_ULOGIC;
129 -- utxd1 : OUT STD_ULOGIC;
129 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
130 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
130 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -- nSRAM_BE0 : OUT STD_LOGIC;
132 -- nSRAM_BE0 : OUT STD_LOGIC;
132 -- nSRAM_BE1 : OUT STD_LOGIC;
133 -- nSRAM_BE1 : OUT STD_LOGIC;
133 -- nSRAM_BE2 : OUT STD_LOGIC;
134 -- nSRAM_BE2 : OUT STD_LOGIC;
134 -- nSRAM_BE3 : OUT STD_LOGIC;
135 -- nSRAM_BE3 : OUT STD_LOGIC;
135 -- nSRAM_WE : OUT STD_LOGIC;
136 -- nSRAM_WE : OUT STD_LOGIC;
136 -- nSRAM_CE : OUT STD_LOGIC;
137 -- nSRAM_CE : OUT STD_LOGIC;
137 -- nSRAM_OE : OUT STD_LOGIC;
138 -- nSRAM_OE : OUT STD_LOGIC;
138 -- apbi_ext : OUT apb_slv_in_type;
139 -- apbi_ext : OUT apb_slv_in_type;
139 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
140 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
140 -- ahbi_s_ext : OUT ahb_slv_in_type;
141 -- ahbi_s_ext : OUT ahb_slv_in_type;
141 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
142 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
142 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
143 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
143 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
144 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
144 --END COMPONENT;
145 --END COMPONENT;
145
146
146 END;
147 END;
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