HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r651:bc7dd8a54a19

Updated LFR EM design....

Alexis Jeandet -

r651:bc7dd8a54a19 default

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r651:bc7dd8a54a19

designs/Makefile created 644 +10 0

@@ -0,0 +1,10
	1	SUBDIRS := $(shell find ./ -maxdepth 1 -mindepth 1 -type d)
	2
	3	all :
	4
	5	.PHONY: force
	6
	7
	8	%:
	9	-for d in $(SUBDIRS); do (cd $$d; $(MAKE) $@ ); done
	10

Makefile +1 0

             distclean:
             	$(MAKE) -C tests distclean
+            	$(MAKE) -C designs distclean

boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK-DAC.pdc +1 -1

             set_io	{led[1]}	-pinname	L18	-fixed	yes	-DIRECTION	Inout
             set_io	{led[2]}	-pinname	M17	-fixed	yes	-DIRECTION	Inout
-            set_io	TAG1    -pinname	J12	-fixed	yes	-DIRECTION	Inout
+            #set_io	TAG1    -pinname	J12	-fixed	yes	-DIRECTION	Inout
             set_io	TAG2	-pinname	K13	-fixed	yes	-DIRECTION	Inout
             set_io	TAG3	-pinname	L16	-fixed	yes	-DIRECTION	Inout
             set_io	TAG4	-pinname	L15	-fixed	yes	-DIRECTION	Inout

designs/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd +1 0

                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 19,
                   USES_IAP_MEMCTRLR => 1,
+                  USES_MBE_PIN      => 1,
                   BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 8)
                 PORT MAP (

designs/LFR-RTAX_keypoint/LFR-EQM.vhd +2 -1

                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 19,
                   USES_IAP_MEMCTRLR => 1,
+                  USES_MBE_PIN      => 1,
                   BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 8)
                 PORT MAP (
                 --TAG(8) <= nSRAM_BUSY;
               END GENERATE USE_DEBUG_VECTOR_IF2;
-            END beh;
  No newline at end of file
+            END beh;

designs/LFR-em-WFP_MS/LFR-em.vhd +3 -1

               ----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL nSRAM_READY : STD_LOGIC;
+              SIGNAL SRAM_MBE : STD_LOGIC;
             BEGIN  -- beh
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
+                  USES_MBE_PIN      => 0,
                   BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 9)
                 PORT MAP (
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => nSRAM_READY,
-                  SRAM_MBE    => '0',
+                  SRAM_MBE    => SRAM_MBE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,

designs/LFR-em-WFP_MS/Makefile +2 -7

-            #GRLIB=../..
             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             EFFORT=high
             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
-            #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-            #VHDLSYNFILES=config.vhd leon3mp.vhd
             VHDLSYNFILES=LFR-em.vhd
             VHDLSIMFILES=testbench.vhd
-            #SIMTOP=testbench
-            #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
-            #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
             SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
             TECHLIBS = proasic3e
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
-            	tmtc openchip hynix ihp gleichmann micron usbhc
+            	tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth
             DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
             	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +17 -9

                 --
                 ADDRESS_SIZE      : INTEGER := 19;
                 USES_IAP_MEMCTRLR : INTEGER := 1;
+                USES_MBE_PIN      : INTEGER := 1;
                 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
                 SRBANKSZ          : INTEGER := 8;
                 SLOW_TIMING_EMULATION : integer := 0
                     );
                 memi.brdyn <= nSRAM_READY;
+            drv_mbe: IF USES_MBE_PIN = 1 GENERATE
+                    mbe_pad : iopad
+                      GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
+                      PORT MAP(pad => SRAM_MBE,
+                               i   => mbe,
+                               en  => mbe_drive,
+                               o   => memi.bexcn);
-                mbe_pad : iopad
+                    nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
-                  GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
+                    nSRAM_OE_s <= memo.oen;
-                  PORT MAP(pad => SRAM_MBE,
+                END GENERATE;
-                           i   => mbe,
-                           en  => mbe_drive,
+            no_drv_mbe: IF USES_MBE_PIN /= 1 GENERATE
-                           o   => memi.bexcn);
+                    memi.bexcn <= '1';
+                END GENERATE;
-                nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
-                nSRAM_OE_s <= memo.oen;
               END GENERATE;

lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +1 0

                   NB_APB_SLAVE    : INTEGER;
                   ADDRESS_SIZE    : INTEGER;
                   USES_IAP_MEMCTRLR : INTEGER;
+                  USES_MBE_PIN      : INTEGER:=1;
                   BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
                   SRBANKSZ        : INTEGER := 8;
                   SLOW_TIMING_EMULATION : integer := 0

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