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- Update files to simulate with questasim...
pellion -
r499:ac8423f90316 JC
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@@ -38,7 +38,7 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
@@ -48,43 +48,47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
85 ---------------------------------------------------------------------------
89 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
90 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
92 );
89
93
90 END LFR_em;
94 END LFR_em;
@@ -97,7 +101,7 ARCHITECTURE beh OF LFR_em IS
97 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
104
101 -- CONSTANTS
105 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
@@ -126,23 +130,23 ARCHITECTURE beh OF LFR_em IS
126 SIGNAL gpioo : gpio_out_type;
130 SIGNAL gpioo : gpio_out_type;
127
131
128 -- AD Converter ADS7886
132 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
135 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
137
136 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
140
139 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
142 SIGNAL rstn : STD_LOGIC;
141
143
142 SIGNAL LFR_soft_rstn : STD_LOGIC;
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
143 SIGNAL LFR_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
144
146
145 SIGNAL ADC_smpclk_s : STD_LOGIC;
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 -----------------------------------------------------------------------------
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
146
150
147 BEGIN -- beh
151 BEGIN -- beh
148
152
@@ -176,7 +180,7 BEGIN -- beh
176
180
177 PROCESS (clk_25, rstn)
181 PROCESS (clk_25, rstn)
178 BEGIN -- PROCESS
182 BEGIN -- PROCESS
179 IF rstn = '0' THEN -- asynchronous reset (active low)
183 IF rstn = '0' THEN -- asynchronous reset (active low)
180 led(0) <= '0';
184 led(0) <= '0';
181 led(1) <= '0';
185 led(1) <= '0';
182 led(2) <= '0';
186 led(2) <= '0';
@@ -208,17 +212,19 BEGIN -- beh
208 ENABLE_GPT => 1,
212 ENABLE_GPT => 1,
209 NB_AHB_MASTER => NB_AHB_MASTER,
213 NB_AHB_MASTER => NB_AHB_MASTER,
210 NB_AHB_SLAVE => NB_AHB_SLAVE,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
211 NB_APB_SLAVE => NB_APB_SLAVE)
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 20,
217 USES_IAP_MEMCTRLR => 0)
212 PORT MAP (
218 PORT MAP (
213 clk => clk_25,
219 clk => clk_25,
214 reset => rstn,
220 reset => rstn,
215 errorn => OPEN,
221 errorn => OPEN,
216
222
217 ahbrxd => TAG1,
223 ahbrxd => TAG1,
218 ahbtxd => TAG3,
224 ahbtxd => TAG3,
219 urxd1 => TAG2,
225 urxd1 => TAG2,
220 utxd1 => TAG4,
226 utxd1 => TAG4,
221
227
222 address => address,
228 address => address,
223 data => data,
229 data => data,
224 nSRAM_BE0 => nSRAM_BE0,
230 nSRAM_BE0 => nSRAM_BE0,
@@ -226,8 +232,10 BEGIN -- beh
226 nSRAM_BE2 => nSRAM_BE2,
232 nSRAM_BE2 => nSRAM_BE2,
227 nSRAM_BE3 => nSRAM_BE3,
233 nSRAM_BE3 => nSRAM_BE3,
228 nSRAM_WE => nSRAM_WE,
234 nSRAM_WE => nSRAM_WE,
229 nSRAM_CE => nSRAM_CE,
235 nSRAM_CE => nSRAM_CE_s,
230 nSRAM_OE => nSRAM_OE,
236 nSRAM_OE => nSRAM_OE,
237 nSRAM_READY => '0',
238 SRAM_MBE => OPEN,
231
239
232 apbi_ext => apbi_ext,
240 apbi_ext => apbi_ext,
233 apbo_ext => apbo_ext,
241 apbo_ext => apbo_ext,
@@ -237,25 +245,27 BEGIN -- beh
237 ahbo_m_ext => ahbo_m_ext);
245 ahbo_m_ext => ahbo_m_ext);
238
246
239
247
248 nSRAM_CE <= nSRAM_CE_s(0);
249
240 -------------------------------------------------------------------------------
250 -------------------------------------------------------------------------------
241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
242 -------------------------------------------------------------------------------
252 -------------------------------------------------------------------------------
243 apb_lfr_time_management_1 : apb_lfr_time_management
253 apb_lfr_time_management_1 : apb_lfr_time_management
244 GENERIC MAP (
254 GENERIC MAP (
245 pindex => 6,
255 pindex => 6,
246 paddr => 6,
256 paddr => 6,
247 pmask => 16#fff#,
257 pmask => 16#fff#,
248 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
249 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
250 PORT MAP (
260 PORT MAP (
251 clk25MHz => clk_25,
261 clk25MHz => clk_25,
252 clk24_576MHz => clk_24, -- 49.152MHz/2
262 clk24_576MHz => clk_24, -- 49.152MHz/2
253 resetn => rstn,
263 resetn => rstn,
254 grspw_tick => swno.tickout,
264 grspw_tick => swno.tickout,
255 apbi => apbi_ext,
265 apbi => apbi_ext,
256 apbo => apbo_ext(6),
266 apbo => apbo_ext(6),
257 coarse_time => coarse_time,
267 coarse_time => coarse_time,
258 fine_time => fine_time,
268 fine_time => fine_time,
259 LFR_soft_rstn => LFR_soft_rstn
269 LFR_soft_rstn => LFR_soft_rstn
260 );
270 );
261
271
@@ -349,7 +359,7 BEGIN -- beh
349 -- LFR ------------------------------------------------------------------------
359 -- LFR ------------------------------------------------------------------------
350 -------------------------------------------------------------------------------
360 -------------------------------------------------------------------------------
351 LFR_rstn <= LFR_soft_rstn AND rstn;
361 LFR_rstn <= LFR_soft_rstn AND rstn;
352
362
353 lpp_lfr_1 : lpp_lfr
363 lpp_lfr_1 : lpp_lfr
354 GENERIC MAP (
364 GENERIC MAP (
355 Mem_use => use_RAM,
365 Mem_use => use_RAM,
@@ -357,14 +367,14 BEGIN -- beh
357 --nb_word_by_buffer_size => 30,
367 --nb_word_by_buffer_size => 30,
358 nb_snapshot_param_size => 32,
368 nb_snapshot_param_size => 32,
359 delta_vector_size => 32,
369 delta_vector_size => 32,
360 delta_vector_size_f0_2 => 7, -- log2(96)
370 delta_vector_size_f0_2 => 7, -- log2(96)
361 pindex => 15,
371 pindex => 15,
362 paddr => 15,
372 paddr => 15,
363 pmask => 16#fff#,
373 pmask => 16#fff#,
364 pirq_ms => 6,
374 pirq_ms => 6,
365 pirq_wfp => 14,
375 pirq_wfp => 14,
366 hindex => 2,
376 hindex => 2,
367 top_lfr_version => X"010123") -- aa.bb.cc version
377 top_lfr_version => X"01012D") -- aa.bb.cc version
368 -- AA : BOARD NUMBER
378 -- AA : BOARD NUMBER
369 -- 0 => MINI_LFR
379 -- 0 => MINI_LFR
370 -- 1 => EM
380 -- 1 => EM
@@ -380,56 +390,65 BEGIN -- beh
380 ahbo => ahbo_m_ext(2),
390 ahbo => ahbo_m_ext(2),
381 coarse_time => coarse_time,
391 coarse_time => coarse_time,
382 fine_time => fine_time,
392 fine_time => fine_time,
383 data_shaping_BW => bias_fail_sw);--,
393 data_shaping_BW => bias_fail_sw,
394 debug_vector => OPEN,
395 debug_vector_ms => OPEN); --,
384 --observation_vector_0 => OPEN,
396 --observation_vector_0 => OPEN,
385 --observation_vector_1 => OPEN,
397 --observation_vector_1 => OPEN,
386 --observation_reg => observation_reg);
398 --observation_reg => observation_reg);
387
399
388
400
389 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
401 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
390 sample_s(I) <= sample(I) & '0' & '0';
402 sample_s(I) <= sample(I) & '0' & '0';
391 END GENERATE all_sample;
403 END GENERATE all_sample;
392
404 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
405
393 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
394 --
407 --
395 -----------------------------------------------------------------------------
408 -----------------------------------------------------------------------------
396 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
409 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
397 GENERIC MAP (
410 GENERIC MAP (
398 ChanelCount => 8,
411 ChanelCount => 9,
399 ncycle_cnv_high => 13,
412 ncycle_cnv_high => 13,
400 ncycle_cnv => 25)
413 ncycle_cnv => 25,
414 FILTER_ENABLED => 16#FF#)
401 PORT MAP (
415 PORT MAP (
402 cnv_clk => clk_24,
416 cnv_clk => clk_24,
403 cnv_rstn => rstn,
417 cnv_rstn => rstn,
404 cnv => ADC_smpclk_s,
418 cnv => ADC_smpclk_s,
405 clk => clk_25,
419 clk => clk_25,
406 rstn => rstn,
420 rstn => rstn,
407 ADC_data => ADC_data,
421 ADC_data => ADC_data,
408 ADC_nOE => ADC_OEB_bar_CH,
422 ADC_nOE => ADC_OEB_bar_CH_s,
409 sample => sample,
423 sample => sample,
410 sample_val => sample_val);
424 sample_val => sample_val);
411
425
412
426 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
413
414
415 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
416 -- GENERIC MAP (
417 -- ChanelCount => 8,
418 -- ncycle_cnv_high => 40, -- TODO : 79
419 -- ncycle_cnv => 250) -- TODO : 500
420 -- PORT MAP (
421 -- cnv_clk => clk_24, -- TODO : 49.152
422 -- cnv_rstn => rstn, -- ok
423 -- cnv => ADC_smpclk_s, -- ok
424 -- clk => clk_25, -- ok
425 -- rstn => rstn, -- ok
426 -- ADC_data => ADC_data, -- ok
427 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
428 -- sample => sample, -- ok
429 -- sample_val => sample_val); -- ok
430
427
431 ADC_smpclk <= ADC_smpclk_s;
428 ADC_smpclk <= ADC_smpclk_s;
432
429 HK_smpclk <= ADC_smpclk_s;
430
433 TAG8 <= ADC_smpclk_s;
431 TAG8 <= ADC_smpclk_s;
434
432
433 -----------------------------------------------------------------------------
434 -- HK
435 -----------------------------------------------------------------------------
436 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
437
438 lpp_lfr_hk_1: lpp_lfr_hk
439 GENERIC MAP (
440 pindex => 7,
441 paddr => 7,
442 pmask => 16#fff#)
443 PORT MAP (
444 clk => clk_25,
445 rstn => rstn,
446
447 apbi => apbi_ext,
448 apbo => apbo_ext(7),
449
450 sample_val => sample_val,
451 sample => sample_s(8),
452 HK_SEL => HK_SEL);
453
435 END beh;
454 END beh;
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@@ -14,11 +14,11 SYNPOPT="set_option -pipe 0; set_option
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc
22
22
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
@@ -42,12 +42,15 DIRSKIP = b1553 pcif leon2 leon2ft crypt
42 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft_rtax \
43 ./lpp_uart \
43 ./lpp_uart \
44 ./lpp_usb \
44 ./lpp_usb \
45 ./lpp_sim/CY7C1061DV33 \
45
46
46 FILESKIP = i2cmst.vhd \
47 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
50 Top_MatrixSpec.vhd \
50 APB_FFT.vhd
51 APB_FFT.vhd\
52 CoreFFT_simu.vhd \
53 lpp_lfr_apbreg_simu.vhd
51
54
52 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
56 include $(GRLIB)/software/leon3/Makefile
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@@ -511,7 +511,7 BEGIN -- beh
511 pirq_ms => 6,
511 pirq_ms => 6,
512 pirq_wfp => 14,
512 pirq_wfp => 14,
513 hindex => 2,
513 hindex => 2,
514 top_lfr_version => X"00012A") -- aa.bb.cc version
514 top_lfr_version => X"00012C") -- aa.bb.cc version
515 PORT MAP (
515 PORT MAP (
516 clk => clk_25,
516 clk => clk_25,
517 rstn => LFR_rstn,
517 rstn => LFR_rstn,
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@@ -375,12 +375,10 BEGIN
375
375
376 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
376 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
377 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
377 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
378 data_out_256(I,J) <= sample_out_reg256_s(I,J);
378 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-1);
379
379 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -1);
380 END GENERATE all_bits;
380 END GENERATE all_bits;
381 END GENERATE all_channel_out_v;
381 END GENERATE all_channel_out_v;
382
383 -- data_out_16 <= sample_out_reg16;
384
382
385 END beh;
383 END beh;
386
384
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@@ -348,7 +348,8 COMPONENT top_ad_conv_RHF1401_withFilter
348 GENERIC (
348 GENERIC (
349 ChanelCount : INTEGER;
349 ChanelCount : INTEGER;
350 ncycle_cnv_high : INTEGER;
350 ncycle_cnv_high : INTEGER;
351 ncycle_cnv : INTEGER);
351 ncycle_cnv : INTEGER;
352 FILTER_ENABLED : INTEGER := 16#FF#);
352 PORT (
353 PORT (
353 cnv_clk : IN STD_LOGIC;
354 cnv_clk : IN STD_LOGIC;
354 cnv_rstn : IN STD_LOGIC;
355 cnv_rstn : IN STD_LOGIC;
@@ -361,6 +362,21 COMPONENT top_ad_conv_RHF1401_withFilter
361 sample_val : OUT STD_LOGIC);
362 sample_val : OUT STD_LOGIC);
362 END COMPONENT;
363 END COMPONENT;
363
364
365 COMPONENT lpp_lfr_hk
366 GENERIC (
367 pindex : INTEGER;
368 paddr : INTEGER;
369 pmask : INTEGER);
370 PORT (
371 clk : IN STD_LOGIC;
372 rstn : IN STD_LOGIC;
373 apbi : IN apb_slv_in_type;
374 apbo : OUT apb_slv_out_type;
375 sample_val : IN STD_LOGIC;
376 sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
377 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
378 END COMPONENT;
379
364
380
365 END lpp_ad_conv;
381 END lpp_ad_conv;
366
382
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@@ -10,7 +10,9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25);
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
14 PORT (
16 PORT (
15 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
16 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
@@ -46,6 +48,9 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
46 SIGNAL ADC_data_result : Samples15;
48 SIGNAL ADC_data_result : Samples15;
47
49
48 SIGNAL sample_counter : INTEGER;
50 SIGNAL sample_counter : INTEGER;
51 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52
53 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
49
54
50 BEGIN
55 BEGIN
51
56
@@ -124,15 +129,11 BEGIN
124 BEGIN -- PROCESS
129 BEGIN -- PROCESS
125 IF rstn = '0' THEN -- asynchronous reset (active low)
130 IF rstn = '0' THEN -- asynchronous reset (active low)
126 channel_counter <= MAX_COUNTER;
131 channel_counter <= MAX_COUNTER;
127 sample_reg(0) <= (OTHERS => '0');
128 sample_reg(1) <= (OTHERS => '0');
129 sample_reg(2) <= (OTHERS => '0');
130 sample_reg(3) <= (OTHERS => '0');
131 sample_reg(4) <= (OTHERS => '0');
132 sample_reg(5) <= (OTHERS => '0');
133 sample_reg(6) <= (OTHERS => '0');
134 sample_reg(7) <= (OTHERS => '0');
135
132
133 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
134 sample_reg(I) <= (OTHERS => '0');
135 END LOOP all_sample_reg_init;
136
136 sample_val <= '0';
137 sample_val <= '0';
137 sample_counter <= 0;
138 sample_counter <= 0;
138 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
139 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
@@ -145,28 +146,40 BEGIN
145 END IF;
146 END IF;
146 sample_val <= '0';
147 sample_val <= '0';
147
148
148 CASE channel_counter IS
149 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1);
150 IF channel_counter = I*2 THEN
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1);
151 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1);
152 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1);
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1);
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1);
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1);
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1);
157 IF sample_counter = 9 THEN
158 sample_counter <= 0 ;
159 sample_val <= '1';
160 ELSE
153 ELSE
161 sample_counter <= sample_counter +1;
154 sample_reg(I) <= ADC_data;
162 END IF;
155 END IF;
163
156 END IF;
164 WHEN OTHERS => NULL;
157 END LOOP all_sample_reg;
165 END CASE;
166
158
159 IF channel_counter = (ChanelCount-1)*2 THEN
160
161 IF sample_counter = MAX_SAMPLE_COUNTER THEN
162 sample_counter <= 0 ;
163 sample_val <= '1';
164 ELSE
165 sample_counter <= sample_counter +1;
166 END IF;
167
168 END IF;
167 END IF;
169 END IF;
168 END PROCESS;
170 END PROCESS;
169
171
172 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
173 -- BEGIN -- PROCESS mux_adc
174 -- CASE channel_counter IS
175 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
176 -- END CASE;
177 -- END PROCESS mux_adc;
178
179
180 -----------------------------------------------------------------------------
181 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
182 -----------------------------------------------------------------------------
170
183
171 WITH channel_counter SELECT
184 WITH channel_counter SELECT
172 ADC_data_selected <= sample_reg(0) WHEN 0*2,
185 ADC_data_selected <= sample_reg(0) WHEN 0*2,
@@ -176,31 +189,16 BEGIN
176 sample_reg(4) WHEN 4*2,
189 sample_reg(4) WHEN 4*2,
177 sample_reg(5) WHEN 5*2,
190 sample_reg(5) WHEN 5*2,
178 sample_reg(6) WHEN 6*2,
191 sample_reg(6) WHEN 6*2,
179 sample_reg(7) WHEN OTHERS ;
192 sample_reg(7) WHEN 7*2,
193 sample_reg(8) WHEN OTHERS ;
180
194
195 -----------------------------------------------------------------------------
196 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
197 -----------------------------------------------------------------------------
181
198
182 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
199 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
183
200
184 sample <= sample_reg;
201 sample <= sample_reg;
185
186
187
188
189 --RHF1401_drvr_1: RHF1401_drvr
190 -- GENERIC MAP (
191 -- ChanelCount => ChanelCount)
192 -- PORT MAP (
193 -- cnv_clk => cnv_sync,
194 -- clk => clk,
195 -- rstn => rstn,
196 -- ADC_data => ADC_data,
197 -- --ADC_smpclk => OPEN,
198 -- ADC_nOE => ADC_nOE,
199 -- sample => sample,
200 -- sample_val => sample_val);
201
202
203
204
202
205 END ar_top_ad_conv_RHF1401;
203 END ar_top_ad_conv_RHF1401;
206
204
@@ -218,4 +216,3 END ar_top_ad_conv_RHF1401;
218
216
219
217
220
218
221
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@@ -5,3 +5,4 top_ad_conv_RHF1401_withFilter.vhd
5 TestModule_RHF1401.vhd
5 TestModule_RHF1401.vhd
6 top_ad_conv_ADS7886_v2.vhd
6 top_ad_conv_ADS7886_v2.vhd
7 ADS7886_drvr_v2.vhd
7 ADS7886_drvr_v2.vhd
8 lpp_lfr_hk.vhd
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@@ -38,6 +38,7 PACKAGE apb_devices_list IS
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
41
42
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
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@@ -66,9 +66,9 ENTITY leon3_soc IS
66 ENABLE_IRQMP : INTEGER := 1;
66 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_GPT : INTEGER := 1;
67 ENABLE_GPT : INTEGER := 1;
68 --
68 --
69 NB_AHB_MASTER : INTEGER := 0;
69 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_SLAVE : INTEGER := 0;
70 NB_AHB_SLAVE : INTEGER := 1;
71 NB_APB_SLAVE : INTEGER := 0;
71 NB_APB_SLAVE : INTEGER := 1;
72 --
72 --
73 ADDRESS_SIZE : INTEGER := 20;
73 ADDRESS_SIZE : INTEGER := 20;
74 USES_IAP_MEMCTRLR : INTEGER := 0
74 USES_IAP_MEMCTRLR : INTEGER := 0
@@ -488,4 +488,4 END GENERATE;
488
488
489
489
490
490
491 END Behavioral;
491 END Behavioral; No newline at end of file
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@@ -31,7 +31,7 USE lpp.FILTERcfg.ALL;
31 USE lpp.lpp_memory.ALL;
31 USE lpp.lpp_memory.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
34 USE data_type_pkg.ALL;
34 USE lpp.data_type_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
@@ -383,11 +383,11 BEGIN
383
383
384 -----------------------------------------------------------------------------
384 -----------------------------------------------------------------------------
385
385
386 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
386 all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE
387 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
387 all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE
388 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
388 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
389 END GENERATE all_channel_sample_f3;
389 END GENERATE all_channel_sample_f3_cic;
390 END GENERATE all_bit_sample_f3;
390 END GENERATE all_bit_sample_f3_cic;
391
391
392 Downsampling_f3 : Downsampling
392 Downsampling_f3 : Downsampling
393 GENERIC MAP (
393 GENERIC MAP (
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