# HG changeset patch # User pellion # Date 2015-01-19 15:27:19 # Node ID ac8423f903164a24f68376f549cee83a03a87fbd # Parent 3368687275e92d8b6dbef42d0451bd98da346cf5 - Update files to simulate with questasim - CIC_LFR : output data - AD_CONV : add one channel into RHF1401_ith_filter for HK and add HK for LFR. MINI-LFR_WFP_MS 0.1.44 LFR-em-WFP_MS 1.1.45 diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -38,7 +38,7 @@ USE esa.memoryctrl.ALL; LIBRARY lpp; USE lpp.lpp_memory.ALL; USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; @@ -48,43 +48,47 @@ USE lpp.lpp_leon3_soc_pkg.ALL; ENTITY LFR_em IS PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; reset : IN STD_ULOGIC; - + -- TAG -------------------------------------------------------------------- - TAG1 : IN STD_ULOGIC; -- DSU rx data - TAG3 : OUT STD_ULOGIC; -- DSU tx data + TAG1 : IN STD_ULOGIC; -- DSU rx data + TAG3 : OUT STD_ULOGIC; -- DSU tx data -- UART APB --------------------------------------------------------------- - TAG2 : IN STD_ULOGIC; -- UART1 rx data - TAG4 : OUT STD_ULOGIC; -- UART1 tx data + TAG2 : IN STD_ULOGIC; -- UART1 rx data + TAG4 : OUT STD_ULOGIC; -- UART1 tx data -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; + spw1_din : IN STD_LOGIC; + spw1_sin : IN STD_LOGIC; + spw1_dout : OUT STD_LOGIC; + spw1_sout : OUT STD_LOGIC; + spw2_din : IN STD_LOGIC; + spw2_sin : IN STD_LOGIC; + spw2_dout : OUT STD_LOGIC; + spw2_sout : OUT STD_LOGIC; -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + -- HK --------------------------------------------------------------------- + HK_smpclk : OUT STD_LOGIC; + ADC_OEB_bar_HK : OUT STD_LOGIC; + HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); --------------------------------------------------------------------------- - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + TAG8 : OUT STD_LOGIC; + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END LFR_em; @@ -97,7 +101,7 @@ ARCHITECTURE beh OF LFR_em IS ----------------------------------------------------------------------------- SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - + -- CONSTANTS CONSTANT CFG_PADTECH : INTEGER := inferred; CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f @@ -126,23 +130,23 @@ ARCHITECTURE beh OF LFR_em IS SIGNAL gpioo : gpio_out_type; -- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample : Samples14v(8 DOWNTO 0); + SIGNAL sample_s : Samples(8 DOWNTO 0); SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL rstn : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; + SIGNAL ADC_smpclk_s : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- beh @@ -176,7 +180,7 @@ BEGIN -- beh PROCESS (clk_25, rstn) BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) + IF rstn = '0' THEN -- asynchronous reset (active low) led(0) <= '0'; led(1) <= '0'; led(2) <= '0'; @@ -208,17 +212,19 @@ BEGIN -- beh ENABLE_GPT => 1, NB_AHB_MASTER => NB_AHB_MASTER, NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 20, + USES_IAP_MEMCTRLR => 0) PORT MAP ( - clk => clk_25, - reset => rstn, - errorn => OPEN, + clk => clk_25, + reset => rstn, + errorn => OPEN, - ahbrxd => TAG1, - ahbtxd => TAG3, - urxd1 => TAG2, - utxd1 => TAG4, - + ahbrxd => TAG1, + ahbtxd => TAG3, + urxd1 => TAG2, + utxd1 => TAG4, + address => address, data => data, nSRAM_BE0 => nSRAM_BE0, @@ -226,8 +232,10 @@ BEGIN -- beh nSRAM_BE2 => nSRAM_BE2, nSRAM_BE3 => nSRAM_BE3, nSRAM_WE => nSRAM_WE, - nSRAM_CE => nSRAM_CE, + nSRAM_CE => nSRAM_CE_s, nSRAM_OE => nSRAM_OE, + nSRAM_READY => '0', + SRAM_MBE => OPEN, apbi_ext => apbi_ext, apbo_ext => apbo_ext, @@ -237,25 +245,27 @@ BEGIN -- beh ahbo_m_ext => ahbo_m_ext); + nSRAM_CE <= nSRAM_CE_s(0); + ------------------------------------------------------------------------------- -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- ------------------------------------------------------------------------------- apb_lfr_time_management_1 : apb_lfr_time_management GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + pindex => 6, + paddr => 6, + pmask => 16#fff#, + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( - clk25MHz => clk_25, - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => rstn, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time, + clk25MHz => clk_25, + clk24_576MHz => clk_24, -- 49.152MHz/2 + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + coarse_time => coarse_time, + fine_time => fine_time, LFR_soft_rstn => LFR_soft_rstn ); @@ -349,7 +359,7 @@ BEGIN -- beh -- LFR ------------------------------------------------------------------------ ------------------------------------------------------------------------------- LFR_rstn <= LFR_soft_rstn AND rstn; - + lpp_lfr_1 : lpp_lfr GENERIC MAP ( Mem_use => use_RAM, @@ -357,14 +367,14 @@ BEGIN -- beh --nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) + delta_vector_size_f0_2 => 7, -- log2(96) pindex => 15, paddr => 15, pmask => 16#fff#, pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"010123") -- aa.bb.cc version + top_lfr_version => X"01012D") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM @@ -380,56 +390,65 @@ BEGIN -- beh ahbo => ahbo_m_ext(2), coarse_time => coarse_time, fine_time => fine_time, - data_shaping_BW => bias_fail_sw);--, + data_shaping_BW => bias_fail_sw, + debug_vector => OPEN, + debug_vector_ms => OPEN); --, --observation_vector_0 => OPEN, --observation_vector_1 => OPEN, --observation_reg => observation_reg); - all_sample: FOR I IN 7 DOWNTO 0 GENERATE + all_sample : FOR I IN 7 DOWNTO 0 GENERATE sample_s(I) <= sample(I) & '0' & '0'; END GENERATE all_sample; - + sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); + ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- - top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter GENERIC MAP ( - ChanelCount => 8, + ChanelCount => 9, ncycle_cnv_high => 13, - ncycle_cnv => 25) + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH, - sample => sample, + cnv_clk => clk_24, + cnv_rstn => rstn, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH_s, + sample => sample, sample_val => sample_val); - - - - --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 - -- GENERIC MAP ( - -- ChanelCount => 8, - -- ncycle_cnv_high => 40, -- TODO : 79 - -- ncycle_cnv => 250) -- TODO : 500 - -- PORT MAP ( - -- cnv_clk => clk_24, -- TODO : 49.152 - -- cnv_rstn => rstn, -- ok - -- cnv => ADC_smpclk_s, -- ok - -- clk => clk_25, -- ok - -- rstn => rstn, -- ok - -- ADC_data => ADC_data, -- ok - -- ADC_nOE => ADC_OEB_bar_CH, -- ok - -- sample => sample, -- ok - -- sample_val => sample_val); -- ok + ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); ADC_smpclk <= ADC_smpclk_s; - + HK_smpclk <= ADC_smpclk_s; + TAG8 <= ADC_smpclk_s; + ----------------------------------------------------------------------------- + -- HK + ----------------------------------------------------------------------------- + ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); + + lpp_lfr_hk_1: lpp_lfr_hk + GENERIC MAP ( + pindex => 7, + paddr => 7, + pmask => 16#fff#) + PORT MAP ( + clk => clk_25, + rstn => rstn, + + apbi => apbi_ext, + apbo => apbo_ext(7), + + sample_val => sample_val, + sample => sample_s(8), + HK_SEL => HK_SEL); + END beh; diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/LFR-em-WFP_MS/Makefile --- a/designs/LFR-em-WFP_MS/Makefile +++ b/designs/LFR-em-WFP_MS/Makefile @@ -14,11 +14,11 @@ SYNPOPT="set_option -pipe 0; set_option #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd #VHDLSYNFILES=config.vhd leon3mp.vhd VHDLSYNFILES=LFR-em.vhd -#VHDLSIMFILES=testbench.vhd +VHDLSIMFILES=testbench.vhd #SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc @@ -42,12 +42,15 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./dsp/lpp_fft_rtax \ ./lpp_uart \ ./lpp_usb \ + ./lpp_sim/CY7C1061DV33 \ FILESKIP = i2cmst.vhd \ APB_MULTI_DIODE.vhd \ APB_MULTI_DIODE.vhd \ Top_MatrixSpec.vhd \ - APB_FFT.vhd + APB_FFT.vhd\ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -511,7 +511,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00012A") -- aa.bb.cc version + top_lfr_version => X"00012C") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/lib/lpp/dsp/cic/cic_lfr.vhd b/lib/lpp/dsp/cic/cic_lfr.vhd --- a/lib/lpp/dsp/cic/cic_lfr.vhd +++ b/lib/lpp/dsp/cic/cic_lfr.vhd @@ -375,12 +375,10 @@ BEGIN all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE all_bits: FOR J IN 15 DOWNTO 0 GENERATE - data_out_256(I,J) <= sample_out_reg256_s(I,J); - + data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-1); + data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -1); END GENERATE all_bits; END GENERATE all_channel_out_v; - --- data_out_16 <= sample_out_reg16; END beh; diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -348,7 +348,8 @@ COMPONENT top_ad_conv_RHF1401_withFilter GENERIC ( ChanelCount : INTEGER; ncycle_cnv_high : INTEGER; - ncycle_cnv : INTEGER); + ncycle_cnv : INTEGER; + FILTER_ENABLED : INTEGER := 16#FF#); PORT ( cnv_clk : IN STD_LOGIC; cnv_rstn : IN STD_LOGIC; @@ -361,6 +362,21 @@ COMPONENT top_ad_conv_RHF1401_withFilter sample_val : OUT STD_LOGIC); END COMPONENT; +COMPONENT lpp_lfr_hk + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + sample_val : IN STD_LOGIC; + sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); +END COMPONENT; + END lpp_ad_conv; diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd --- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd @@ -10,7 +10,9 @@ ENTITY top_ad_conv_RHF1401_withFilter IS GENERIC( ChanelCount : INTEGER := 8; ncycle_cnv_high : INTEGER := 13; - ncycle_cnv : INTEGER := 25); + ncycle_cnv : INTEGER := 25; + FILTER_ENABLED : INTEGER := 16#FF# + ); PORT ( cnv_clk : IN STD_LOGIC; -- 24Mhz cnv_rstn : IN STD_LOGIC; @@ -46,6 +48,9 @@ ARCHITECTURE ar_top_ad_conv_RHF1401 OF t SIGNAL ADC_data_result : Samples15; SIGNAL sample_counter : INTEGER; + CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; + + CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount)); BEGIN @@ -124,15 +129,11 @@ BEGIN BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) channel_counter <= MAX_COUNTER; - sample_reg(0) <= (OTHERS => '0'); - sample_reg(1) <= (OTHERS => '0'); - sample_reg(2) <= (OTHERS => '0'); - sample_reg(3) <= (OTHERS => '0'); - sample_reg(4) <= (OTHERS => '0'); - sample_reg(5) <= (OTHERS => '0'); - sample_reg(6) <= (OTHERS => '0'); - sample_reg(7) <= (OTHERS => '0'); + all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP + sample_reg(I) <= (OTHERS => '0'); + END LOOP all_sample_reg_init; + sample_val <= '0'; sample_counter <= 0; ELSIF clk'event AND clk = '1' THEN -- rising clock edge @@ -145,28 +146,40 @@ BEGIN END IF; sample_val <= '0'; - CASE channel_counter IS - WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1); - WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1); - WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1); - WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1); - WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1); - WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1); - WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1); - WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1); - IF sample_counter = 9 THEN - sample_counter <= 0 ; - sample_val <= '1'; + all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP + IF channel_counter = I*2 THEN + IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN + sample_reg(I) <= ADC_data_result(14 DOWNTO 1); ELSE - sample_counter <= sample_counter +1; + sample_reg(I) <= ADC_data; END IF; - - WHEN OTHERS => NULL; - END CASE; + END IF; + END LOOP all_sample_reg; + IF channel_counter = (ChanelCount-1)*2 THEN + + IF sample_counter = MAX_SAMPLE_COUNTER THEN + sample_counter <= 0 ; + sample_val <= '1'; + ELSE + sample_counter <= sample_counter +1; + END IF; + + END IF; END IF; END PROCESS; +-- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg) +-- BEGIN -- PROCESS mux_adc +-- CASE channel_counter IS +-- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2); +-- END CASE; +-- END PROCESS mux_adc; + + + ----------------------------------------------------------------------------- + -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/ + ----------------------------------------------------------------------------- WITH channel_counter SELECT ADC_data_selected <= sample_reg(0) WHEN 0*2, @@ -176,31 +189,16 @@ BEGIN sample_reg(4) WHEN 4*2, sample_reg(5) WHEN 5*2, sample_reg(6) WHEN 6*2, - sample_reg(7) WHEN OTHERS ; + sample_reg(7) WHEN 7*2, + sample_reg(8) WHEN OTHERS ; + ----------------------------------------------------------------------------- + -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\ + ----------------------------------------------------------------------------- ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) ); sample <= sample_reg; - - - - - --RHF1401_drvr_1: RHF1401_drvr - -- GENERIC MAP ( - -- ChanelCount => ChanelCount) - -- PORT MAP ( - -- cnv_clk => cnv_sync, - -- clk => clk, - -- rstn => rstn, - -- ADC_data => ADC_data, - -- --ADC_smpclk => OPEN, - -- ADC_nOE => ADC_nOE, - -- sample => sample, - -- sample_val => sample_val); - - - END ar_top_ad_conv_RHF1401; @@ -218,4 +216,3 @@ END ar_top_ad_conv_RHF1401; - diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt --- a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt +++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt @@ -5,3 +5,4 @@ top_ad_conv_RHF1401_withFilter.vhd TestModule_RHF1401.vhd top_ad_conv_ADS7886_v2.vhd ADS7886_drvr_v2.vhd +lpp_lfr_hk.vhd diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd --- a/lib/lpp/lpp_amba/apb_devices_list.vhd +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -38,6 +38,7 @@ PACKAGE apb_devices_list IS CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; CONSTANT LPP_LFR : amba_device_type := 16#19#; CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; + CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#; CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -66,9 +66,9 @@ ENTITY leon3_soc IS ENABLE_IRQMP : INTEGER := 1; ENABLE_GPT : INTEGER := 1; -- - NB_AHB_MASTER : INTEGER := 0; - NB_AHB_SLAVE : INTEGER := 0; - NB_APB_SLAVE : INTEGER := 0; + NB_AHB_MASTER : INTEGER := 1; + NB_AHB_SLAVE : INTEGER := 1; + NB_APB_SLAVE : INTEGER := 1; -- ADDRESS_SIZE : INTEGER := 20; USES_IAP_MEMCTRLR : INTEGER := 0 @@ -488,4 +488,4 @@ END GENERATE; -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -31,7 +31,7 @@ USE lpp.FILTERcfg.ALL; USE lpp.lpp_memory.ALL; USE lpp.lpp_waveform_pkg.ALL; USE lpp.cic_pkg.ALL; -USE data_type_pkg.ALL; +USE lpp.data_type_pkg.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; @@ -383,11 +383,11 @@ BEGIN ----------------------------------------------------------------------------- - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE + all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE + all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE sample_f3_cic_s(J,I) <= sample_f3_cic(J,I); - END GENERATE all_channel_sample_f3; - END GENERATE all_bit_sample_f3; + END GENERATE all_channel_sample_f3_cic; + END GENERATE all_bit_sample_f3_cic; Downsampling_f3 : Downsampling GENERIC MAP (