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Modif ALU...
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_fft.all;
27 use work.fft_components.all;
28
29 entity FFT is
30 generic(
31 Data_sz : integer := 16;
32 NbData : integer := 256);
33 port(
34 clkm : in std_logic;
35 rstn : in std_logic;
36 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 FifoIN_Data : in std_logic_vector(79 downto 0);
38 FifoOUT_Full : in std_logic_vector(4 downto 0);
39 Read : out std_logic_vector(4 downto 0);
40 Write : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
42 Data : out std_logic_vector(79 downto 0)
43 );
44 end entity;
45
46
47 architecture ar_FFT of FFT is
48
49 signal Drive_Write : std_logic;
50 signal Drive_DataRE : std_logic_vector(15 downto 0);
51 signal Drive_DataIM : std_logic_vector(15 downto 0);
52
53 signal Start : std_logic;
54 signal FFT_Load : std_logic;
55 signal FFT_Ready : std_logic;
56 signal FFT_Valid : std_logic;
57 signal FFT_DataRE : std_logic_vector(15 downto 0);
58 signal FFT_DataIM : std_logic_vector(15 downto 0);
59
60 signal Link_Read : std_logic;
61
62 begin
63
64 Start <= '0';
65
66 DRIVE : Driver_FFT
67 generic map(Data_sz,NbData)
68 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
69
70 FFT0 : CoreFFT
71 generic map(
72 LOGPTS => gLOGPTS,
73 LOGLOGPTS => gLOGLOGPTS,
74 WSIZE => gWSIZE,
75 TWIDTH => gTWIDTH,
76 DWIDTH => gDWIDTH,
77 TDWIDTH => gTDWIDTH,
78 RND_MODE => gRND_MODE,
79 SCALE_MODE => gSCALE_MODE,
80 PTS => gPTS,
81 HALFPTS => gHALFPTS,
82 inBuf_RWDLY => gInBuf_RWDLY)
83 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
84
85
86 LINK : Linker_FFT
87 generic map(Data_sz,NbData)
88 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
89
90
91 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs
27
28 entity TwoComplementer is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 reset : in std_logic; --! Reset general du composant
34 clr : in std_logic; --! Un reset sp�cifique au programme
35 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
36 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
37 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
38 );
39 end TwoComplementer;
40
41
42 architecture ar_TwoComplementer of TwoComplementer is
43
44 signal REG : std_logic_vector(Input_SZ-1 downto 0);
45 signal OPinteger : integer;
46 signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0);
47
48 begin
49
50 RES <= REG;
51 OPinteger <= to_integer(signed(OP));
52 RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ));
53
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 REG <= (others => '0');
59 elsif(clk'event and clk='1')then
60
61 if(clr='1')then
62 REG <= (others => '0');
63 elsif(TwoComp='1')then
64 REG <= RESCOMP;
65 else
66 REG <= OP;
67 end if;
68
69 end if;
70
71 end process;
72 end ar_TwoComplementer; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_demux.all;
27
28 entity Demultiplex is
29 generic(
30 Data_sz : integer range 1 to 32 := 16);
31 port(
32 clk : in std_logic;
33 rstn : in std_logic;
34
35 Read : in std_logic_vector(4 downto 0);
36
37 EmptyF0a : in std_logic_vector(4 downto 0);
38 EmptyF0b : in std_logic_vector(4 downto 0);
39 EmptyF1 : in std_logic_vector(4 downto 0);
40 EmptyF2 : in std_logic_vector(4 downto 0);
41
42 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
45 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
46
47 Read_DEMUX : out std_logic_vector(19 downto 0);
48 Empty : out std_logic_vector(4 downto 0);
49 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
50 );
51 end entity;
52
53
54 architecture ar_Demultiplex of Demultiplex is
55
56 signal DataCpt : std_logic_vector(3 downto 0);
57
58 begin
59
60 FLG0 : WatchFlag
61 port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt);
62
63 DEM : DEMUX
64 generic map(Data_sz)
65 port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data);
66
67 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_matrix.all;
27
28 entity MatriceSpectrale is
29 generic(
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
32 port(
33 clkm : in std_logic;
34 rstn : in std_logic;
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 Data_IN : in std_logic_vector(79 downto 0);
39 ACQ : in std_logic;
40 FlagError : out std_logic;
41 Pong : out std_logic;
42 Write : out std_logic_vector(1 downto 0);
43 Read : out std_logic_vector(4 downto 0);
44 Data_OUT : out std_logic_vector(63 downto 0)
45 );
46 end entity;
47
48
49 architecture ar_MatriceSpectrale of MatriceSpectrale is
50
51 signal Matrix_Write : std_logic;
52 signal Matrix_Read : std_logic_vector(1 downto 0);
53 signal Matrix_Result : std_logic_vector(31 downto 0);
54
55 signal TopSM_Start : std_logic;
56 signal TopSM_Statu : std_logic_vector(3 downto 0);
57 signal TopSM_Data1 : std_logic_vector(15 downto 0);
58 signal TopSM_Data2 : std_logic_vector(15 downto 0);
59
60 begin
61
62 TopSM : TopSpecMatrix
63 generic map (Input_SZ)
64 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
65
66 SM : SpectralMatrix
67 generic map (Input_SZ,Result_SZ)
68 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
69
70 DISP : Dispatch
71 generic map(Result_SZ)
72 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
73
74
75 end architecture;
76
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@@ -79,7 +79,8 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
79 79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 80 alu_sel_input : IN STD_LOGIC;
81 81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
83 84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
84 85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
85 86 END COMPONENT;
@@ -105,7 +106,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
105 106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 107 alu_sel_input : OUT STD_LOGIC;
107 108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
108 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
109 110 END COMPONENT;
110 111
111 112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -117,7 +118,7 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_
117 118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 119 SIGNAL alu_sel_input : STD_LOGIC;
119 120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
120 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
121 122
122 123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
123 124 SIGNAL sample_in_rotate : STD_LOGIC;
@@ -155,6 +156,7 BEGIN
155 156 alu_sel_input => alu_sel_input,
156 157 alu_sel_coeff => alu_sel_coeff,
157 158 alu_ctrl => alu_ctrl,
159 alu_comp => "00",
158 160 --DATA
159 161 sample_in => sample_in_s,
160 162 sample_out => sample_out_s);
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@@ -50,7 +50,7 ENTITY IIR_CEL_CTRLR_v2_CONTROL IS
50 50 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 51 alu_sel_input : OUT STD_LOGIC;
52 52 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
53 alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
53 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
54 54 );
55 55 END IIR_CEL_CTRLR_v2_CONTROL;
56 56
@@ -92,7 +92,7 BEGIN
92 92 --ALU -------------------------------------------------------------------
93 93 alu_selected_coeff <= 0; --
94 94 alu_sel_input <= '0'; --
95 alu_ctrl <= (OTHERS => '0'); --
95 alu_ctrl <= ctrl_IDLE; --
96 96 --OUT
97 97 sample_out_val <= '0'; --
98 98 sample_out_rot <= '0'; --
@@ -108,7 +108,7 BEGIN
108 108 sample_out_rot <= '0';
109 109 sample_in_rot <= '0';
110 110 sample_out_val <= '0';
111 alu_ctrl <= "0100";
111 alu_ctrl <= ctrl_CLRMAC;
112 112 alu_selected_coeff <= 0;
113 113 in_sel_src <= "01";
114 114 ram_read <= '0';
@@ -134,7 +134,7 BEGIN
134 134 IIR_CEL_STATE <= compute_b2;
135 135 ram_read <= '1';
136 136 raddr_add1 <= '1';
137 alu_ctrl <= "0010";
137 alu_ctrl <= ctrl_MULT;
138 138 alu_sel_input <= '1';
139 139 in_sel_src <= "01";
140 140
@@ -160,7 +160,7 BEGIN
160 160 in_sel_src <= "11";
161 161 END IF;
162 162 alu_selected_coeff <= alu_selected_coeff+1;
163 alu_ctrl <= "0001";
163 alu_ctrl <= ctrl_MAC;
164 164 IIR_CEL_STATE <= compute_b1;
165 165
166 166 WHEN compute_b1 =>
@@ -183,7 +183,7 BEGIN
183 183 in_sel_src <= "00";
184 184 END IF;
185 185 alu_selected_coeff <= alu_selected_coeff+1;
186 alu_ctrl <= "0001";
186 alu_ctrl <= ctrl_MAC;
187 187 IIR_CEL_STATE <= compute_b0;
188 188
189 189 WHEN compute_b0 =>
@@ -199,7 +199,7 BEGIN
199 199 raddr_add1 <= '0';
200 200 in_sel_src <= "10";
201 201 alu_selected_coeff <= alu_selected_coeff+1;
202 alu_ctrl <= "0001";
202 alu_ctrl <= ctrl_MAC;
203 203 IIR_CEL_STATE <= compute_a2;
204 204 IF Cel_ongoing = Cels_count THEN
205 205 sample_in_rot <= '1';
@@ -223,7 +223,7 BEGIN
223 223 END IF;
224 224 in_sel_src <= "00";
225 225 alu_selected_coeff <= alu_selected_coeff+1;
226 alu_ctrl <= "0001";
226 alu_ctrl <= ctrl_MAC;
227 227 IIR_CEL_STATE <= compute_a1;
228 228 sample_in_rot <= '0';
229 229
@@ -236,7 +236,7 BEGIN
236 236 waddr_previous <= "01";
237 237 ram_read <= '1';
238 238 raddr_rst <= '0';
239 alu_ctrl <= "0010";
239 alu_ctrl <= ctrl_MULT;
240 240 sample_in_rot <= '0';
241 241 IF Cel_ongoing = Cels_count THEN
242 242 alu_selected_coeff <= 0;
@@ -274,7 +274,7 BEGIN
274 274 WHEN wait_valid_last_output =>
275 275 IIR_CEL_STATE <= wait_valid_last_output_2;
276 276 sample_in_rot <= '0';
277 alu_ctrl <= "0000";
277 alu_ctrl <= ctrl_IDLE;
278 278 alu_selected_coeff <= 0;
279 279 in_sel_src <= "01";
280 280 ram_read <= '0';
@@ -291,7 +291,7 BEGIN
291 291 WHEN wait_valid_last_output_2 =>
292 292 IIR_CEL_STATE <= waiting;
293 293 sample_in_rot <= '0';
294 alu_ctrl <= "0000";
294 alu_ctrl <= ctrl_IDLE;
295 295 alu_selected_coeff <= 0;
296 296 in_sel_src <= "01";
297 297 ram_read <= '0';
@@ -310,4 +310,4 BEGIN
310 310 END IF;
311 311 END PROCESS;
312 312
313 END ar_IIR_CEL_CTRLR_v2_CONTROL;
313 END ar_IIR_CEL_CTRLR_v2_CONTROL; No newline at end of file
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@@ -55,7 +55,8 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
55 55 --
56 56 alu_sel_input : IN STD_LOGIC;
57 57 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
58 alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
58 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
59 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 60 -- DATA
60 61 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
61 62 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
@@ -200,6 +201,7 BEGIN
200 201 clk => clk,
201 202 reset => rstn,
202 203 ctrl => alu_ctrl,
204 comp => alu_comp,
203 205 OP1 => alu_sample,
204 206 OP2 => alu_coef,
205 207 RES => alu_output_s);
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@@ -26,7 +26,6 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
30 29 use work.fft_components.all;
31 30
32 31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
@@ -75,6 +74,22 component APB_FFT_half is
75 74 );
76 75 end component;
77 76
77 component FFT is
78 generic(
79 Data_sz : integer := 16;
80 NbData : integer := 256);
81 port(
82 clkm : in std_logic;
83 rstn : in std_logic;
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Read : out std_logic_vector(4 downto 0);
88 Write : out std_logic_vector(4 downto 0);
89 ReUse : out std_logic_vector(4 downto 0);
90 Data : out std_logic_vector(79 downto 0)
91 );
92 end component;
78 93
79 94 component Flag_Extremum is
80 95 port(
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@@ -1,77 +1,63
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 --IDLE = 0000
28 --MAC = 0001
29 --MULT = 0010 and set MULT in ADD reg
30 --ADD = 0011
31 --CLRMAC = 0100
32
33
34 ENTITY ALU IS
35 GENERIC(
36 Arith_en : INTEGER := 1;
37 Logic_en : INTEGER := 1;
38 Input_SZ_1 : INTEGER := 16;
39 Input_SZ_2 : INTEGER := 9
40
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 reset : IN STD_LOGIC;
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
49 );
50 END ENTITY;
51
52 ARCHITECTURE ar_ALU OF ALU IS
53
54 SIGNAL clr_MAC : STD_LOGIC := '1';
55
56 BEGIN
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
58
59 arith : IF Arith_en = 1 GENERATE
60 MACinst : MAC
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
63 END GENERATE;
64
65 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
29
30 entity ALU is
31 generic(
32 Arith_en : integer := 1;
33 Logic_en : integer := 1;
34 Input_SZ_1 : integer := 16;
35 Input_SZ_2 : integer := 16);
36 port(
37 clk : in std_logic; --! Horloge du composant
38 reset : in std_logic; --! Reset general du composant
39 ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
40 comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
41 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
42 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
43 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
44 );
45 end ALU;
46
47 --! @details S�lection grace a l'entr�e "ctrl" :
48 --! Pause : IDLE = 000
49 --! Multiplieur/Accumulateur : MAC = 001
50 --! Multiplication : MULT = 010
51 --! Addition : ADD = 011
52 --! Reset du MAC : CLRMAC = 100
53 architecture ar_ALU of ALU is
54
55 begin
56
57 arith : if Arith_en = 1 generate
58 MACinst : MAC
59 generic map(Input_SZ_1,Input_SZ_2)
60 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
61 end generate;
62
63 end architecture; No newline at end of file
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@@ -40,6 +40,7 ENTITY MAC IS
40 40 reset : IN STD_LOGIC;
41 41 clr_MAC : IN STD_LOGIC;
42 42 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 44 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
44 45 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
45 46 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
@@ -51,34 +52,35 END MAC;
51 52
52 53 ARCHITECTURE ar_MAC OF MAC IS
53 54
54 SIGNAL add, mult : STD_LOGIC;
55 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
55 signal add,mult : std_logic;
56 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 57
57 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
59 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60 61
62 signal MACMUXsel : std_logic;
63 signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
61 65
62 SIGNAL MACMUXsel : STD_LOGIC;
63 SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
64 SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65
66
66 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
67 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
67 68
68 SIGNAL MACMUX2sel : STD_LOGIC;
69 signal MACMUX2sel : std_logic;
69 70
70 SIGNAL add_D : STD_LOGIC;
71 SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
72 SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
73 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
74 SIGNAL MACMUXsel_D : STD_LOGIC;
75 SIGNAL MACMUX2sel_D : STD_LOGIC;
76 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
77 SIGNAL clr_MAC_D : STD_LOGIC;
78 SIGNAL clr_MAC_D_D : STD_LOGIC;
71 signal add_D : std_logic;
72 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
73 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
74 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
75 signal MACMUXsel_D : std_logic;
76 signal MACMUX2sel_D : std_logic;
77 signal MACMUX2sel_D_D : std_logic;
78 signal clr_MAC_D : std_logic;
79 signal clr_MAC_D_D : std_logic;
80 signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0);
79 81
80 SIGNAL load_mult_result : STD_LOGIC;
81 SIGNAL load_mult_result_D : STD_LOGIC;
82 SIGNAL load_mult_result : STD_LOGIC;
83 SIGNAL load_mult_result_D : STD_LOGIC;
82 84
83 85 BEGIN
84 86
@@ -111,14 +113,14 BEGIN
111 113 Input_SZ_A => Input_SZ_A,
112 114 Input_SZ_B => Input_SZ_B
113 115 )
114 PORT MAP(
115 clk => clk,
116 reset => reset,
117 mult => mult,
118 OP1 => OP1,
119 OP2 => OP2,
120 RES => MULTout
121 );
116 port map(
117 clk => clk,
118 reset => reset,
119 mult => mult,
120 OP1 => OP1_2C,
121 OP2 => OP2_2C,
122 RES => MULTout
123 );
122 124 --==============================================================
123 125
124 126 PROCESS (clk, reset)
@@ -148,9 +150,38 BEGIN
148 150 OP2 => ADDERinB,
149 151 RES => ADDERout
150 152 );
153
151 154 --==============================================================
155 --===================TWO COMPLEMENTERS==========================
156 --==============================================================
157 TWO_COMPLEMENTER1 : TwoComplementer
158 generic map(
159 Input_SZ => Input_SZ_A
160 )
161 port map(
162 clk => clk,
163 reset => reset,
164 clr => clr_MAC,
165 TwoComp => Comp_2C(0),
166 OP => OP1,
167 RES => OP1_2C
168 );
152 169
153 170
171 TWO_COMPLEMENTER2 : TwoComplementer
172 generic map(
173 Input_SZ => Input_SZ_B
174 )
175 port map(
176 clk => clk,
177 reset => reset,
178 clr => clr_MAC,
179 TwoComp => Comp_2C(1),
180 OP => OP2,
181 RES => OP2_2C
182 );
183 --==============================================================
184
154 185 clr_MACREG1 : MAC_REG
155 186 GENERIC MAP(size => 1)
156 187 PORT MAP(
@@ -169,23 +200,24 BEGIN
169 200 Q(0) => add_D
170 201 );
171 202
172 OP1REG : MAC_REG
173 GENERIC MAP(size => Input_SZ_A)
174 PORT MAP(
175 reset => reset,
176 clk => clk,
177 D => OP1,
178 Q => OP1_D
179 );
203 OP1REG : MAC_REG
204 generic map(size => Input_SZ_A)
205 port map(
206 reset => reset,
207 clk => clk,
208 D => OP1_2C,
209 Q => OP1_2C_D
210 );
180 211
181 OP2REG : MAC_REG
182 GENERIC MAP(size => Input_SZ_B)
183 PORT MAP(
184 reset => reset,
185 clk => clk,
186 D => OP2,
187 Q => OP2_D
188 );
212
213 OP2REG : MAC_REG
214 generic map(size => Input_SZ_B)
215 port map(
216 reset => reset,
217 clk => clk,
218 D => OP2_2C,
219 Q => OP2_2C_D
220 );
189 221
190 222 MULToutREG : MAC_REG
191 223 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
@@ -235,14 +267,14 BEGIN
235 267 PORT MAP(
236 268 sel => MACMUXsel_D,
237 269 INA1 => ADDERout,
238 INA2 => OP2_D_Resz,
270 INA2 => OP2_2C_D_Resz,
239 271 INB1 => MULTout,
240 INB2 => OP1_D_Resz,
272 INB2 => OP1_2C_D_Resz,
241 273 OUTA => ADDERinA,
242 274 OUTB => ADDERinB
243 275 );
244 OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B));
245 OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B));
276 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
277 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
246 278 --==============================================================
247 279
248 280
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@@ -89,13 +89,23 PACKAGE general_purpose IS
89 89 PORT(
90 90 clk : IN STD_LOGIC;
91 91 reset : IN STD_LOGIC;
92 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 comp : IN STD_LOGIC_VECTOR(1 downto 0);
93 94 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
94 95 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
95 96 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
96 97 );
97 98 END COMPONENT;
98 99
100 ---------------------------------------------------------
101 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
102 ---------------------------------------------------------
103 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 ---------------------------------------------------------
99 109
100 110 COMPONENT MAC IS
101 111 GENERIC(
@@ -108,12 +118,25 PACKAGE general_purpose IS
108 118 reset : IN STD_LOGIC;
109 119 clr_MAC : IN STD_LOGIC;
110 120 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
111 122 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
112 123 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
113 124 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
114 125 );
115 126 END COMPONENT;
116 127
128 COMPONENT TwoComplementer is
129 generic(
130 Input_SZ : integer := 16);
131 port(
132 clk : in std_logic; --! Horloge du composant
133 reset : in std_logic; --! Reset general du composant
134 clr : in std_logic; --! Un reset sp�cifique au programme
135 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
136 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
137 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
138 );
139 end COMPONENT;
117 140
118 141 COMPONENT MAC_CONTROLER IS
119 142 PORT(
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@@ -45,6 +45,8 use lpp.lpp_ad_conv.all;
45 45 use lpp.iir_filter.all;
46 46 use lpp.general_purpose.all;
47 47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
49 use lpp.lpp_top_lfr_pkg.all;
48 50
49 51 entity leon3mp is
50 52 generic (
@@ -95,6 +97,11 entity leon3mp is
95 97 -- UART
96 98 UART_RXD : in std_logic;
97 99 UART_TXD : out std_logic;
100 -- ACQ
101 Clk_49Mhz : IN STD_LOGIC;
102 CNV_CH1 : OUT STD_LOGIC;
103 SCK_CH1 : OUT STD_LOGIC;
104 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
98 105 -- ADC
99 106 -- ADC_in : in AD7688_in(4 downto 0);
100 107 -- ADC_out : out AD7688_out;
@@ -170,82 +177,84 signal dsuo : dsu_out_type;
170 177 --- AJOUT TEST ------------------------Signaux----------------------
171 178 ---------------------------------------------------------------------
172 179 -- FIFOs
173 signal FifoIN_Full : std_logic_vector(4 downto 0);
174 signal FifoIN_Empty : std_logic_vector(4 downto 0);
175 signal FifoIN_Data : std_logic_vector(79 downto 0);
180 signal FifoF0a_Full : std_logic_vector(4 downto 0);
181 signal FifoF0a_Empty : std_logic_vector(4 downto 0);
182 signal FifoF0a_Data : std_logic_vector(79 downto 0);
183 signal FifoF0b_Full : std_logic_vector(4 downto 0);
184 signal FifoF0b_Empty : std_logic_vector(4 downto 0);
185 signal FifoF0b_Data : std_logic_vector(79 downto 0);
186 signal FifoF1_Full : std_logic_vector(4 downto 0);
187 signal FifoF1_Empty : std_logic_vector(4 downto 0);
188 signal FifoF1_Data : std_logic_vector(79 downto 0);
189 signal FifoF3_Full : std_logic_vector(4 downto 0);
190 signal FifoF3_Empty : std_logic_vector(4 downto 0);
191 signal FifoF3_Data : std_logic_vector(79 downto 0);
176 192
177 193 signal FifoINT_Full : std_logic_vector(4 downto 0);
178 194 signal FifoINT_Data : std_logic_vector(79 downto 0);
179 195
180 signal FifoOUT_FullV : std_logic;
196 --signal FifoOUT_FullV : std_logic;
181 197 signal FifoOUT_Full : std_logic_vector(1 downto 0);
182 signal Matrix_WriteV : std_logic_vector(0 downto 0);
198 --signal Matrix_WriteV : std_logic_vector(0 downto 0);
183 199
184 200 -- MATRICE SPECTRALE
185 signal Matrix_Write : std_logic;
186 signal Matrix_Read : std_logic_vector(1 downto 0);
187 signal Matrix_Result : std_logic_vector(31 downto 0);
201 signal SM_FlagError : std_logic;
202 signal SM_Pong : std_logic;
203 signal SM_Read : std_logic_vector(4 downto 0);
204 signal SM_Write : std_logic_vector(1 downto 0);
205 signal SM_Data : std_logic_vector(63 downto 0);
188 206
189 signal TopSM_Start : std_logic;
190 signal TopSM_Statu : std_logic_vector(3 downto 0);
191 signal TopSM_Read : std_logic_vector(4 downto 0);
192 signal TopSM_Data1 : std_logic_vector(15 downto 0);
193 signal TopSM_Data2 : std_logic_vector(15 downto 0);
194
195 signal Disp_FlagError : std_logic;
196 signal Disp_Pong : std_logic;
197 signal Disp_Write : std_logic_vector(1 downto 0);--
198 signal Disp_Data : std_logic_vector(63 downto 0);--
199 signal Dma_acq : std_logic;
207 signal Dma_acq : std_logic;
200 208
201 209 -- FFT
202 signal Drive_Write : std_logic;
203 signal Drive_Read : std_logic_vector(4 downto 0);
204 signal Drive_DataRE : std_logic_vector(15 downto 0);
205 signal Drive_DataIM : std_logic_vector(15 downto 0);
210 signal FFT_Read : std_logic_vector(4 downto 0);
211 signal FFT_Write : std_logic_vector(4 downto 0);
212 signal FFT_ReUse : std_logic_vector(4 downto 0);
213 signal FFT_Data : std_logic_vector(79 downto 0);
206 214
207 signal Start : std_logic;
208 signal RstnFFT : std_logic;
209 signal FFT_Load : std_logic;
210 signal FFT_Ready : std_logic;
211 signal FFT_Valid : std_logic;
212 signal FFT_DataRE : std_logic_vector(15 downto 0);
213 signal FFT_DataIM : std_logic_vector(15 downto 0);
215 -- DEMUX
216 signal DEMU_Read : std_logic_vector(19 downto 0);
217 signal DEMU_Empty : std_logic_vector(4 downto 0);
218 signal DEMU_Data : std_logic_vector(79 downto 0);
214 219
215 signal Link_Read : std_logic;
216 signal Link_Write : std_logic_vector(4 downto 0);
217 signal Link_ReUse : std_logic_vector(4 downto 0);
218 signal Link_Data : std_logic_vector(79 downto 0);
220 -- ACQ
221 signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
219 228
220 229 -- ADC
221 signal SmplClk : std_logic;
222 signal ADC_DataReady : std_logic;
223 signal ADC_SmplOut : Samples_out(4 downto 0);
224 signal enableADC : std_logic;
225
226 signal WG_Write : std_logic_vector(4 downto 0);
227 signal WG_ReUse : std_logic_vector(4 downto 0);
228 signal WG_DATA : std_logic_vector(79 downto 0);
229 signal s_out : std_logic_vector(79 downto 0);
230
231 signal fuller : std_logic_vector(4 downto 0);
232 signal reader : std_logic_vector(4 downto 0);
233 signal try : std_logic_vector(1 downto 0);
234 signal TXDint : std_logic;
235
236 -- IIR Filter
237 signal sample_clk_out : std_logic;
238
239 signal Rd : std_logic_vector(0 downto 0);
240 signal Ept : std_logic_vector(4 downto 0);
241
242 signal Bwr : std_logic_vector(0 downto 0);
243 signal Bre : std_logic_vector(0 downto 0);
244 signal DataTMP : std_logic_vector(15 downto 0);
245 signal FullUp : std_logic_vector(0 downto 0);
246 signal EmptyUp : std_logic_vector(0 downto 0);
247 signal FullDown : std_logic_vector(0 downto 0);
248 signal EmptyDown : std_logic_vector(0 downto 0);
230 --signal SmplClk : std_logic;
231 --signal ADC_DataReady : std_logic;
232 --signal ADC_SmplOut : Samples_out(4 downto 0);
233 --signal enableADC : std_logic;
234 --
235 --signal WG_Write : std_logic_vector(4 downto 0);
236 --signal WG_ReUse : std_logic_vector(4 downto 0);
237 --signal WG_DATA : std_logic_vector(79 downto 0);
238 --signal s_out : std_logic_vector(79 downto 0);
239 --
240 --signal fuller : std_logic_vector(4 downto 0);
241 --signal reader : std_logic_vector(4 downto 0);
242 --signal try : std_logic_vector(1 downto 0);
243 --signal TXDint : std_logic;
244 --
245 ---- IIR Filter
246 --signal sample_clk_out : std_logic;
247 --
248 --signal Rd : std_logic_vector(0 downto 0);
249 --signal Ept : std_logic_vector(4 downto 0);
250 --
251 --signal Bwr : std_logic_vector(0 downto 0);
252 --signal Bre : std_logic_vector(0 downto 0);
253 --signal DataTMP : std_logic_vector(15 downto 0);
254 --signal FullUp : std_logic_vector(0 downto 0);
255 --signal EmptyUp : std_logic_vector(0 downto 0);
256 --signal FullDown : std_logic_vector(0 downto 0);
257 --signal EmptyDown : std_logic_vector(0 downto 0);
249 258 ---------------------------------------------------------------------
250 259 constant IOAEN : integer := CFG_CAN;
251 260 constant boardfreq : integer := 50000;
@@ -309,37 +318,43 led(1 downto 0) <= gpio(1 downto 0);
309 318 -- MemIn1 : APB_FIFO
310 319 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
311 320 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
321
322 TopACQ : lpp_top_acq
323 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
324
325 --- FIFO IN -------------------------------------------------------------
326
327 Memf0a : lppFIFOxN
328 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
329 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
330
331 Memf0b : lppFIFOxN
332 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
333 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
334
335 Memf1 : lppFIFOxN
336 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
337 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
338
339 Memf3 : lppFIFOxN
340 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
341 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
342
343 --- DEMUX -------------------------------------------------------------
344
345 DEMUX0 : Demultiplex
346 generic map(Data_sz => 16)
347 port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
312 348
313 349 --- FFT -------------------------------------------------------------
314 350
315 MemIn : APB_FIFO
316 generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
317 port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
318
319 DRIVE : Driver_FFT
320 generic map(Data_sz => 16)
321 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
351 -- MemIn : APB_FIFO
352 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
353 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
322 354
323 Start <= '0';
324
325 FFT : CoreFFT
326 generic map(
327 LOGPTS => gLOGPTS,
328 LOGLOGPTS => gLOGLOGPTS,
329 WSIZE => gWSIZE,
330 TWIDTH => gTWIDTH,
331 DWIDTH => gDWIDTH,
332 TDWIDTH => gTDWIDTH,
333 RND_MODE => gRND_MODE,
334 SCALE_MODE => gSCALE_MODE,
335 PTS => gPTS,
336 HALFPTS => gHALFPTS,
337 inBuf_RWDLY => gInBuf_RWDLY)
338 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
339
340 LINK : Linker_FFT
341 generic map(Data_sz => 16)
342 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);
355 FFT0 : FFT
356 generic map(Data_sz => 16,NbData => 256)
357 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
343 358
344 359 ----- LINK MEMORY -------------------------------------------------------
345 360
@@ -349,7 +364,7 Start <= '0';
349 364
350 365 MemInt : lppFIFOxN
351 366 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
352 port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
367 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
353 368
354 369 -- MemIn : APB_FIFO
355 370 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
@@ -357,23 +372,15 Start <= '0';
357 372
358 373 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
359 374
360 TopSM : TopSpecMatrix
361 generic map (Input_SZ => 16)
362 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
363
364 SM : SpectralMatrix
365 generic map (Input_SZ => 16, Result_SZ => 32)
366 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
375 SM0 : MatriceSpectrale
376 generic map(Input_SZ => 16,Result_SZ => 32)
377 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
367 378
368 379 Dma_acq <= '1';
369
370 DISP : Dispatch
371 generic map(Data_SZ => 32)
372 port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
373 380
374 381 MemOut : APB_FIFO
375 382 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
376 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9));
383 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
377 384
378 385 ----- FIFO -------------------------------------------------------------
379 386
Show file before | Show file after | Hide comments
@@ -1,4 +1,24
1 -- WatchFlag.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
2 22 library IEEE;
3 23 use IEEE.std_logic_1164.all;
4 24 use IEEE.numeric_std.all;
@@ -8,11 +28,6 port(
8 28 clk : in std_logic;
9 29 rstn : in std_logic;
10 30
11 FullF0a : in std_logic_vector(4 downto 0);
12 FullF0b : in std_logic_vector(4 downto 0);
13 FullF1 : in std_logic_vector(4 downto 0);
14 FullF2 : in std_logic_vector(4 downto 0);
15
16 31 EmptyF0a : in std_logic_vector(4 downto 0);
17 32 EmptyF0b : in std_logic_vector(4 downto 0);
18 33 EmptyF1 : in std_logic_vector(4 downto 0);
@@ -26,6 +41,7 end entity;
26 41 architecture ar_WatchFlag of WatchFlag is
27 42
28 43 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
44 constant OneToSet : std_logic_vector(4 downto 0) := "01111";
29 45
30 46 begin
31 47 process(clk,rstn)
@@ -35,25 +51,25 begin
35 51
36 52 elsif(clk'event and clk='1')then
37 53
38 if(FullF0a = FlagSet)then
54 if(EmptyF0a = OneToSet)then
39 55 DataCpt(0) <= '1';
40 56 elsif(EmptyF0a = FlagSet)then
41 57 DataCpt(0) <= '0';
42 58 end if;
43 59
44 if(FullF0b = FlagSet)then
60 if(EmptyF0b = OneToSet)then
45 61 DataCpt(1) <= '1';
46 62 elsif(EmptyF0b = FlagSet)then
47 63 DataCpt(1) <= '0';
48 64 end if;
49 65
50 if(FullF1 = FlagSet)then
66 if(EmptyF1 = OneToSet)then
51 67 DataCpt(2) <= '1';
52 68 elsif(EmptyF1 = FlagSet)then
53 69 DataCpt(2) <= '0';
54 70 end if;
55 71
56 if(FullF2 = FlagSet)then
72 if(EmptyF2 = OneToSet)then
57 73 DataCpt(3) <= '1';
58 74 elsif(EmptyF2 = FlagSet)then
59 75 DataCpt(3) <= '0';
Show file before | Show file after | Hide comments
@@ -31,6 +31,33 use lpp.lpp_amba.all;
31 31
32 32 package lpp_demux is
33 33
34
35 component Demultiplex is
36 generic(
37 Data_sz : integer range 1 to 32 := 16);
38 port(
39 clk : in std_logic;
40 rstn : in std_logic;
41
42 Read : in std_logic_vector(4 downto 0);
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
34 61 component DEMUX is
35 62 generic(
36 63 Data_sz : integer range 1 to 32 := 16);
@@ -63,11 +90,6 port(
63 90 clk : in std_logic;
64 91 rstn : in std_logic;
65 92
66 FullF0a : in std_logic_vector(4 downto 0);
67 FullF0b : in std_logic_vector(4 downto 0);
68 FullF1 : in std_logic_vector(4 downto 0);
69 FullF2 : in std_logic_vector(4 downto 0);
70
71 93 EmptyF0a : in std_logic_vector(4 downto 0);
72 94 EmptyF0b : in std_logic_vector(4 downto 0);
73 95 EmptyF1 : in std_logic_vector(4 downto 0);
Show file before | Show file after | Hide comments
@@ -22,6 +22,8
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
25 27
26 28 --! Driver de l'ALU
27 29
@@ -39,7 +41,8 entity ALU_Driver is
39 41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 42 Valid : out std_logic; --! Flag, R�sultat disponible
41 43 Read : out std_logic; --! Flag, op�rande disponible
42 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
43 46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
44 47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
45 48 );
@@ -58,7 +61,7 signal go_st : std_logic;
58 61 signal Take_reg : std_logic;
59 62 signal Received_reg : std_logic;
60 63
61 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
62 65 signal ect : etat;
63 66 signal st : etat;
64 67
@@ -70,7 +73,8 begin
70 73 ect <= eX;
71 74 st <= e0;
72 75 go_st <= '0';
73 CTRL <= "10000";
76 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
74 78 Read <= '0';
75 79 Valid <= '0';
76 80 Take_reg <= '0';
@@ -84,7 +88,7 begin
84 88 when eX =>
85 89 go_st <= '0';
86 90 Read <= '1';
87 CTRL <= "10000";
91 CTRL <= ctrl_CLRMAC;
88 92 ect <= e0;
89 93
90 94 when e0 =>
@@ -102,18 +106,18 begin
102 106 when e1 =>
103 107 OP1 <= OP1re;
104 108 OP2 <= OP2re;
105 CTRL <= "00001";
109 CTRL <= ctrl_MAC;
106 110 Read <= '1';
107 ect <= idle;
111 ect <= eY;
108 112
109 when idle =>
113 when eY =>
110 114 OP1im <= IN1;
111 115 if(Conjugate='1')then --
112 116 OP2im <= IN1; --
113 117 else --
114 118 OP2im <= IN2; -- modif 23/06/11
115 119 end if; --
116 CTRL <= "00000";
120 CTRL <= ctrl_IDLE;
117 121 if(Take_reg='1' and Take='0')then
118 122 Read <= '0';
119 123 ect <= e2;
@@ -122,11 +126,11 begin
122 126 when e2 =>
123 127 OP1 <= OP1im;
124 128 OP2 <= OP2im;
125 CTRL <= "00001";
126 ect <= idle2;
129 CTRL <= ctrl_MAC;
130 ect <= eZ;
127 131
128 when idle2 =>
129 CTRL <= "00000";
132 when eZ =>
133 CTRL <= ctrl_IDLE;
130 134 go_st <= '1';
131 135 if(Received_reg='0' and Received='1')then
132 136 if(Conjugate='1')then
@@ -137,24 +141,25 begin
137 141 end if;
138 142
139 143 when e3 =>
140 CTRL <= "10000";
144 CTRL <= ctrl_CLRMAC;
141 145 go_st <= '0';
142 146 ect <= e4;
143 147
144 148 when e4 =>
145 149 OP1 <= OP1im;
146 150 OP2 <= OP2re;
147 CTRL <= "00001";
151 CTRL <= ctrl_MAC;
148 152 ect <= e5;
149 153
150 154 when e5 =>
151 155 OP1 <= OP1re;
152 156 OP2 <= OP2im;
153 CTRL <= "01001";
154 ect <= idle3;
155
156 when idle3 =>
157 CTRL <= "00000";
157 COMP <= "10";
158 ect <= eW;
159
160 when eW =>
161 CTRL <= ctrl_IDLE;
162 COMP <= "00";
158 163 go_st <= '1';
159 164 if(Received_reg='1' and Received='0')then
160 165 ect <= eX;
@@ -175,13 +180,13 begin
175 180 if(Received_reg='0' and Received='1')then
176 181 Valid <= '0';
177 182 if(Conjugate='1')then
178 st <= idle2;
183 st <= eY;
179 184 else
180 st <= idle;
185 st <= eX;
181 186 end if;
182 187 end if;
183 188
184 when idle =>
189 when eX =>
185 190 st <= e3;
186 191
187 192 when e3 =>
@@ -196,10 +201,10 begin
196 201 when e5 =>
197 202 if(Received_reg='1' and Received='0')then
198 203 Valid <= '0';
199 st <= idle2;
204 st <= eY;
200 205 end if;
201 206
202 when idle2 =>
207 when eY =>
203 208 st <= e0;
204 209
205 210 when others =>
Show file before | Show file after | Hide comments
@@ -22,7 +22,9
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 library lpp;
25 26 use lpp.lpp_matrix.all;
27 use lpp.general_purpose.all;
26 28
27 29 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
28 30
@@ -46,7 +48,8 end Matrix;
46 48
47 49 architecture ar_Matrix of Matrix is
48 50
49 signal CTRL : std_logic_vector(4 downto 0);
51 signal CTRL : std_logic_vector(2 downto 0);
52 signal COMP : std_logic_vector(1 downto 0);
50 53 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
51 54 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
52 55
@@ -54,13 +57,12 begin
54 57
55 58 DRIVE : ALU_Driver
56 59 generic map(Input_SZ,Input_SZ)
57 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
60 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,COMP,OP1,OP2);
58 61
59 62
60 ALU : ALU_v2
63 ALU0 : ALU
61 64 generic map(1,0,Input_SZ,Input_SZ)
62 port map(clk,raz,CTRL,OP1,OP2,Result);
65 port map(clk,raz,CTRL,COMP,OP1,OP2,Result);
63 66
64 67
65 68 end ar_Matrix;
66
Show file before | Show file after | Hide comments
@@ -56,6 +56,27 component APB_Matrix is
56 56 );
57 57 end component;
58 58
59 component MatriceSpectrale is
60 generic(
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 port(
64 clkm : in std_logic;
65 rstn : in std_logic;
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 Data_IN : in std_logic_vector(79 downto 0);
70 ACQ : in std_logic;
71 FlagError : out std_logic;
72 Pong : out std_logic;
73 Write : out std_logic_vector(1 downto 0);
74 Read : out std_logic_vector(4 downto 0);
75 Data_OUT : out std_logic_vector(63 downto 0)
76 );
77 end component;
78
79
59 80 component TopSpecMatrix is
60 81 generic(
61 82 Input_SZ : integer := 16);
@@ -222,57 +243,11 component ALU_Driver is
222 243 Conjugate : in std_logic;
223 244 Valid : out std_logic;
224 245 Read : out std_logic;
225 CTRL : out std_logic_vector(4 downto 0);
246 CTRL : out std_logic_vector(2 downto 0);
247 COMP : out std_logic_vector(1 downto 0);
226 248 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
227 249 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
228 250 );
229 251 end component;
230 252
231
232 component ALU_v2 is
233 generic(
234 Arith_en : integer := 1;
235 Logic_en : integer := 1;
236 Input_SZ_1 : integer := 16;
237 Input_SZ_2 : integer := 9);
238 port(
239 clk : in std_logic;
240 reset : in std_logic;
241 ctrl : in std_logic_vector(4 downto 0);
242 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
243 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
244 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
245 );
246 end component;
247
248
249 component MAC_v2 is
250 generic(
251 Input_SZ_A : integer := 8;
252 Input_SZ_B : integer := 8);
253 port(
254 clk : in std_logic;
255 reset : in std_logic;
256 clr_MAC : in std_logic;
257 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
258 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
259 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
260 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
261 );
262 end component;
263
264
265 component TwoComplementer is
266 generic(
267 Input_SZ : integer := 16);
268 port(
269 clk : in std_logic;
270 reset : in std_logic;
271 clr : in std_logic;
272 TwoComp : in std_logic;
273 OP : in std_logic_vector(Input_SZ-1 downto 0);
274 RES : out std_logic_vector(Input_SZ-1 downto 0)
275 );
276 end component;
277
278 253 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -28,16 +28,16 ENTITY lpp_top_acq IS
28 28 --
29 29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38 --
39 39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
41 41 );
42 42 END lpp_top_acq;
43 43
@@ -170,7 +170,7 BEGIN
170 170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 171 GENERIC MAP (
172 172 tech => 0,
173 Mem_use => use_CEL,
173 Mem_use => use_RAM,
174 174 Sample_SZ => 18,
175 175 Coef_SZ => Coef_SZ,
176 176 Coef_Nb => 25, -- TODO
@@ -221,12 +221,12 BEGIN
221 221 sample_out_val => sample_f0_val,
222 222 sample_out => sample_f0);
223 223
224 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
224 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
225 225 sample_f0_wdata(I) <= sample_f0(0, I);
226 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
226 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
230 230 END GENERATE all_bit_sample_f0;
231 231
232 232 PROCESS (clk, rstn)
@@ -281,12 +281,12 BEGIN
281 281 NOT(sample_f1_val) &
282 282 NOT(sample_f1_val);
283 283
284 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
284 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
285 285 sample_f1_wdata(I) <= sample_f1(0, I);
286 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
286 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
290 290 END GENERATE all_bit_sample_f1;
291 291
292 292 -----------------------------------------------------------------------------
@@ -311,12 +311,12 BEGIN
311 311 NOT(sample_f2_val) &
312 312 NOT(sample_f2_val);
313 313
314 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
314 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
315 315 sample_f2_wdata(I) <= sample_f2(0, I);
316 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
316 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
320 320 END GENERATE all_bit_sample_f2;
321 321
322 322 -----------------------------------------------------------------------------
@@ -341,12 +341,12 BEGIN
341 341 (NOT sample_f3_val) &
342 342 (NOT sample_f3_val);
343 343
344 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
344 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
345 345 sample_f3_wdata(I) <= sample_f3(0, I);
346 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
346 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
350 350 END GENERATE all_bit_sample_f3;
351 351
352 352
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@@ -22,15 +22,15 PACKAGE lpp_top_lfr_pkg IS
22 22 cnv_rstn : IN STD_LOGIC;
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
25 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
34 34 END COMPONENT;
35 35
36 END lpp_top_lfr_pkg;
36 END lpp_top_lfr_pkg; No newline at end of file
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