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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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use lpp.lpp_matrix.all;
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--! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
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entity Matrix is
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generic(
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Input_SZ : integer := 16);
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port(
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clk : in std_logic; --! Horloge du composant
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raz : in std_logic; --! Reset general du composant
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IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
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IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
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Take : in std_logic; --! Flag, op�rande r�cup�r�
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Received : in std_logic; --! Flag, R�sultat bien ressu
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Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
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Valid : out std_logic; --! Flag, R�sultat disponible
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Read : out std_logic; --! Flag, op�rande disponible
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Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
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);
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end Matrix;
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architecture ar_Matrix of Matrix is
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signal CTRL : std_logic_vector(4 downto 0);
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signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
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signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
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begin
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DRIVE : ALU_Driver
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generic map(Input_SZ,Input_SZ)
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port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
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ALU : ALU_v2
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generic map(1,0,Input_SZ,Input_SZ)
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port map(clk,raz,CTRL,OP1,OP2,Result);
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end ar_Matrix;
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