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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

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martin -
r146:e09c526b7abe martin
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1 NO CONTENT: modified file, binary diff hidden
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@@ -1,18 +1,19
1 ./lpp_ad_Conv
1 ./amba_lcd_16x2_ctrlr
2 ./lpp_usb
2 ./dsp/iir_filter
3 ./lpp_amba
3 ./dsp/lpp_downsampling
4 ./lpp_memory
4 ./dsp/lpp_fft
5 ./general_purpose
5 ./general_purpose
6 ./general_purpose/lpp_AMR
6 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
7 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
8 ./general_purpose/lpp_delay
9 ./lpp_cna
9 ./lpp_ad_Conv
10 ./lpp_amba
10 ./lpp_bootloader
11 ./lpp_bootloader
11 ./lpp_matrix
12 ./lpp_cna
12 ./amba_lcd_16x2_ctrlr
13 ./lpp_demux
13 ./lpp_dma
14 ./lpp_dma
14 ./dsp/iir_filter
15 ./lpp_matrix
15 ./dsp/lpp_fft
16 ./lpp_memory
16 ./dsp/lpp_downsampling
17 ./lpp_top_lfr
17 ./lpp_uart
18 ./lpp_uart
18 ./lpp_top_lfr
19 ./lpp_usb
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@@ -1,19 +1,17
1 Adder.vhd
2 ADDRcntr.vhd
1 ADDRcntr.vhd
3 ALU.vhd
2 ALU.vhd
3 Adder.vhd
4 Clk_Divider2.vhd
4 Clk_Divider2.vhd
5 Clk_Divider2.vhd~
6 Clk_divider.vhd
5 Clk_divider.vhd
7 general_purpose.vhd
6 MAC.vhd
8 general_purpose.vhd~
9 MAC_CONTROLER.vhd
7 MAC_CONTROLER.vhd
8 MAC_MUX.vhd
10 MAC_MUX2.vhd
9 MAC_MUX2.vhd
11 MAC_MUX.vhd
12 MAC_REG.vhd
10 MAC_REG.vhd
13 MAC.vhd
14 Multiplier.vhd
15 MUX2.vhd
11 MUX2.vhd
16 MUXN.vhd
12 MUXN.vhd
13 Multiplier.vhd
17 REG.vhd
14 REG.vhd
15 SYNC_FF.vhd
18 Shifter.vhd
16 Shifter.vhd
19 SYNC_FF.vhd
17 general_purpose.vhd
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@@ -1,8 +1,8
1 fifo_latency_correction.vhd
1 fifo_latency_correction.vhd
2 lpp_dma.vhd
2 lpp_dma_apbreg.vhd
3 lpp_dma_apbreg.vhd
3 lpp_dma_fsm.vhd
4 lpp_dma_fsm.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_ip.vhd
5 lpp_dma_pkg.vhd
6 lpp_dma_pkg.vhd
6 lpp_dma_send_16word.vhd
7 lpp_dma_send_16word.vhd
7 lpp_dma_send_1word.vhd
8 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
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@@ -20,7 +20,7 ENTITY lpp_top_acq IS
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC;
23 cnv_clk : IN STD_LOGIC; -- clk 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
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@@ -1,2 +1,2
1 lpp_top_acq.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_top_lfr_pkg.vhd
2 lpp_top_acq.vhd
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