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ADD LPP_CNA (and CAL to LFR-em)
pellion -
r531:1e4a9714222a JC
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@@ -0,0 +1,7
1 lpp_cna.vhd
2 APB_LFR_CAL.vhd
3 RAM_READER.vhd
4 RAM_WRITER.vhd
5 SPI_DAC_DRIVER.vhd
6 dynamic_freq_div.vhd
7 lfr_cal_driver.vhd
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@@ -16,3 +16,12 device LPP_MATRIX 13
16 16 device LPP_DELAY 14
17 17 device LPP_USB 15
18 18 device LPP_BALISE 16
19 device LPP_DMA_TYPE 17
20 device LPP_BOOTLOADER_TYPE 18
21 device LPP_LFR 19
22 device LPP_CLKSETTING 20
23 device LPP_LFR_HK_DEVICE 21
24 device LPP_LFR_MANAGEMENT 22
25 device LPP_DEBUG_DMA A0
26 device LPP_DEBUG_LFR A1
27 device LPP_DEBUG_LFR_ID A2
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@@ -84,7 +84,7 set_io TAG3 -pinname L16 -fixed yes -DIR
84 84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90 90
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@@ -82,6 +82,11 ENTITY LFR_em IS
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
85 90 -- HK ---------------------------------------------------------------------
86 91 HK_smpclk : OUT STD_LOGIC;
87 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
@@ -253,6 +258,7 BEGIN -- beh
253 258 -------------------------------------------------------------------------------
254 259 apb_lfr_management_1 : apb_lfr_management
255 260 GENERIC MAP (
261 tech => apa3e,
256 262 pindex => 6,
257 263 paddr => 6,
258 264 pmask => 16#fff#,
@@ -270,6 +276,11 BEGIN -- beh
270 276 HK_val => sample_val,
271 277 HK_sel => HK_SEL,
272 278
279 DAC_SDO => DAC_SDO,
280 DAC_SCK => DAC_SCK,
281 DAC_SYNC => DAC_SYNC,
282 DAC_CAL_EN => DAC_CAL_EN,
283
273 284 coarse_time => coarse_time,
274 285 fine_time => fine_time,
275 286 LFR_soft_rstn => LFR_soft_rstn
@@ -380,7 +391,7 BEGIN -- beh
380 391 pirq_ms => 6,
381 392 pirq_wfp => 14,
382 393 hindex => 2,
383 top_lfr_version => X"01013A") -- aa.bb.cc version
394 top_lfr_version => X"01013B") -- aa.bb.cc version
384 395 -- AA : BOARD NUMBER
385 396 -- 0 => MINI_LFR
386 397 -- 1 => EM
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@@ -18,7 +18,7 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
22 22
23 23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
@@ -38,7 +38,6 DIRSKIP = b1553 pcif leon2 leon2ft crypt
38 38 ./general_purpose/lpp_balise \
39 39 ./general_purpose/lpp_delay \
40 40 ./lpp_bootloader \
41 ./lpp_cna \
42 41 ./dsp/lpp_fft_rtax \
43 42 ./lpp_uart \
44 43 ./lpp_usb \
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@@ -11,10 +11,10
11 11 ./dsp/lpp_fft_rtax
12 12 ./lpp_memory
13 13 ./dsp/lpp_fft
14 ./lpp_cna
14 15 ./lfr_management
15 16 ./lpp_ad_Conv
16 17 ./lpp_bootloader
17 ./lpp_cna
18 18 ./lpp_spectral_matrix
19 19 ./lpp_demux
20 20 ./lpp_Header
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@@ -29,11 +29,15 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 USE lpp.lpp_cna.ALL;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
32 35
33 36
34 37 ENTITY apb_lfr_management IS
35 38
36 39 GENERIC(
40 tech : INTEGER := 0;
37 41 pindex : INTEGER := 0; --! APB slave index
38 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
@@ -55,6 +59,11 ENTITY apb_lfr_management IS
55 59 HK_val : IN STD_LOGIC;
56 60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 61 ---------------------------------------------------------------------------
62 DAC_SDO : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
66 ---------------------------------------------------------------------------
58 67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
60 69 ---------------------------------------------------------------------------
@@ -67,7 +76,7 ARCHITECTURE Behavioral OF apb_lfr_manag
67 76
68 77 CONSTANT REVISION : INTEGER := 1;
69 78 CONSTANT pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
79 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
71 80 1 => apb_iobar(paddr, pmask)
72 81 );
73 82
@@ -120,6 +129,27 ARCHITECTURE Behavioral OF apb_lfr_manag
120 129 SIGNAL previous_fine_time_bit : STD_LOGIC;
121 130
122 131 SIGNAL rstn_LFR_TM : STD_LOGIC;
132
133 -----------------------------------------------------------------------------
134 -- DAC
135 -----------------------------------------------------------------------------
136 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT abits : INTEGER := 8;
141
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL Reload : STD_LOGIC;
145 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 SIGNAL WEN : STD_LOGIC;
147 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
123 153
124 154 BEGIN
125 155
@@ -141,7 +171,18 BEGIN
141 171 soft_tick <= '0';
142 172
143 173 coarsetime_reg_updated <= '0';
144
174 --DAC
175 pre <= (OTHERS => '1');
176 N <= (OTHERS => '1');
177 Reload <= '1';
178 DATA_IN <= (OTHERS => '0');
179 WEN <= '1';
180 LOAD_ADDRESSN <= '1';
181 ADDRESS_IN <= (OTHERS => '1');
182 INTERLEAVED <= '0';
183 DAC_CFG <= (OTHERS => '0');
184 --
185 DAC_CAL_EN_s <= '0';
145 186 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
146 187 coarsetime_reg_updated <= '0';
147 188
@@ -190,6 +231,24 BEGIN
190 231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
191 232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
192 233 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
234 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
235 Rdata(3 DOWNTO 0) <= DAC_CFG;
236 Rdata(4) <= Reload;
237 Rdata(5) <= INTERLEAVED;
238 Rdata(6) <= DAC_CAL_EN_s;
239 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
240 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
241 Rdata(PRESZ-1 DOWNTO 0) <= pre;
242 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
243 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
244 Rdata(CPTSZ-1 DOWNTO 0) <= N;
245 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
246 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
247 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
248 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
249 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
250 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
251 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
193 252 WHEN OTHERS =>
194 253 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
195 254 END CASE;
@@ -204,10 +263,28 BEGIN
204 263 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
205 264 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
206 265 coarsetime_reg_updated <= '1';
266 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
267 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
268 Reload <= apbi.pwdata(4);
269 INTERLEAVED <= apbi.pwdata(5);
270 DAC_CAL_EN_s <= apbi.pwdata(6);
271 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
272 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
273 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
274 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
275 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
276 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
277 LOAD_ADDRESSN <= '0';
278 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
279 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
280 WEN <= '0';
281
207 282 WHEN OTHERS =>
208 283 NULL;
209 284 END CASE;
210 285 ELSE
286 LOAD_ADDRESSN <= '1';
287 WEN <= '1';
211 288 IF r.ctrl = '1' THEN
212 289 r.ctrl <= '0';
213 290 END IF;
@@ -393,5 +470,38 BEGIN
393 470 END PROCESS;
394 471
395 472 HK_sel <= HK_sel_s;
396
473
474 -----------------------------------------------------------------------------
475 -- DAC
476 -----------------------------------------------------------------------------
477 cal : lfr_cal_driver
478 GENERIC MAP(
479 tech => tech,
480 PRESZ => PRESZ,
481 CPTSZ => CPTSZ,
482 datawidth => datawidth,
483 abits => abits
484 )
485 PORT MAP(
486 clk => clk25MHz,
487 rstn => resetn,
488
489 pre => pre,
490 N => N,
491 Reload => Reload,
492 DATA_IN => DATA_IN,
493 WEN => WEN,
494 LOAD_ADDRESSN => LOAD_ADDRESSN,
495 ADDRESS_IN => ADDRESS_IN,
496 ADDRESS_OUT => ADDRESS_OUT,
497 INTERLEAVED => INTERLEAVED,
498 DAC_CFG => DAC_CFG,
499
500 SYNC => DAC_SYNC,
501 DOUT => DAC_SDO,
502 SCLK => DAC_SCK,
503 SMPCLK => OPEN --DAC_SMPCLK
504 );
505
506 DAC_CAL_EN <= DAC_CAL_EN_s;
397 507 END Behavioral; No newline at end of file
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@@ -31,6 +31,7 PACKAGE lpp_lfr_management IS
31 31
32 32 COMPONENT apb_lfr_management
33 33 GENERIC (
34 tech : INTEGER;
34 35 pindex : INTEGER;
35 36 paddr : INTEGER;
36 37 pmask : INTEGER;
@@ -46,6 +47,10 PACKAGE lpp_lfr_management IS
46 47 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
47 48 HK_val : IN STD_LOGIC;
48 49 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 DAC_SDO : OUT STD_LOGIC;
51 DAC_SCK : OUT STD_LOGIC;
52 DAC_SYNC : OUT STD_LOGIC;
53 DAC_CAL_EN : OUT STD_LOGIC;
49 54 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
50 55 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
51 56 LFR_soft_rstn : OUT STD_LOGIC);
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@@ -11,5 +11,10 PACKAGE lpp_lfr_management_apbreg_pkg IS
11 11 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
12 12 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
13 13 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
14 CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
15 CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
16 CONSTANT ADDR_LFR_MANAGMENT_DAC_N : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
17 CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
18 CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
14 19
15 20 END lpp_lfr_management_apbreg_pkg;
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@@ -39,7 +39,7 PACKAGE apb_devices_list IS
39 39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41 41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
42
42 CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#;
43 43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
44 44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
45 45
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@@ -19,163 +19,165
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.lpp_amba.all;
31 use lpp.lpp_cna.all;
32 use lpp.apb_devices_list.all;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
29 LIBRARY lpp;
30 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_cna.ALL;
32 USE lpp.apb_devices_list.ALL;
33 33
34 entity apb_lfr_cal is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 tech : integer := 0;
40 PRESZ : integer := 8;
41 CPTSZ : integer := 16;
42 datawidth : integer := 18;
43 dacresolution : integer := 12;
44 abits : integer := 8
34 ENTITY apb_lfr_cal IS
35 GENERIC (
36 pindex : INTEGER := 0;
37 paddr : INTEGER := 0;
38 pmask : INTEGER := 16#fff#;
39 tech : INTEGER := 0;
40 PRESZ : INTEGER := 8;
41 CPTSZ : INTEGER := 16;
42 datawidth : INTEGER := 18;
43 dacresolution : INTEGER := 12;
44 abits : INTEGER := 8
45 45 );
46 port (
47 rstn : in std_logic;
48 clk : in std_logic;
49 apbi : in apb_slv_in_type;
50 apbo : out apb_slv_out_type;
51 SDO : out std_logic;
52 SCK : out std_logic;
53 SYNC : out std_logic;
54 SMPCLK : out std_logic
46 PORT (
47 rstn : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51 SDO : OUT STD_LOGIC;
52 SCK : OUT STD_LOGIC;
53 SYNC : OUT STD_LOGIC;
54 SMPCLK : OUT STD_LOGIC
55 55 );
56 end entity;
56 END ENTITY;
57 57
58 58 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
59 59 --! et les sorties seront cabl�es vers le convertisseur.
60 60
61 architecture ar_apb_lfr_cal of apb_lfr_cal is
61 ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
62 62
63 constant REVISION : integer := 1;
63 CONSTANT REVISION : INTEGER := 1;
64 64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
65 CONSTANT pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68 68
69 signal pre : STD_LOGIC_VECTOR(PRESZ-1 downto 0);
70 signal N : STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
71 signal Reload : std_logic;
72 signal DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
73 signal WEN : STD_LOGIC;
74 signal LOAD_ADDRESSN : STD_LOGIC;
75 signal ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 downto 0);
76 signal ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 downto 0);
77 signal INTERLEAVED : STD_LOGIC;
78 signal DAC_CFG : STD_LOGIC_VECTOR(3 downto 0);
79 signal Rdata : std_logic_vector(31 downto 0);
69 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
70 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
71 SIGNAL Reload : STD_LOGIC;
72 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
73 SIGNAL WEN : STD_LOGIC;
74 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
75 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
76 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
77 SIGNAL INTERLEAVED : STD_LOGIC;
78 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 begin
81 BEGIN
82 82
83 cal: lfr_cal_driver
84 generic map(
85 tech => tech,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
89 abits => abits
90 )
91 Port map(
92 clk => clk,
93 rstn => rstn,
94 pre => pre,
95 N => N,
96 Reload => Reload,
97 DATA_IN => DATA_IN,
98 WEN => WEN,
99 LOAD_ADDRESSN => LOAD_ADDRESSN,
100 ADDRESS_IN => ADDRESS_IN,
101 ADDRESS_OUT => ADDRESS_OUT,
102 INTERLEAVED => INTERLEAVED,
103 DAC_CFG => DAC_CFG,
104 SYNC => SYNC,
105 DOUT => SDO,
106 SCLK => SCK,
107 SMPCLK => SMPCLK
108 );
83 cal : lfr_cal_driver
84 GENERIC MAP(
85 tech => tech,
86 PRESZ => PRESZ,
87 CPTSZ => CPTSZ,
88 datawidth => datawidth,
89 abits => abits
90 )
91 PORT MAP(
92 clk => clk,
93 rstn => rstn,
94
95 pre => pre,
96 N => N,
97 Reload => Reload,
98 DATA_IN => DATA_IN,
99 WEN => WEN,
100 LOAD_ADDRESSN => LOAD_ADDRESSN,
101 ADDRESS_IN => ADDRESS_IN,
102 ADDRESS_OUT => ADDRESS_OUT,
103 INTERLEAVED => INTERLEAVED,
104 DAC_CFG => DAC_CFG,
105
106 SYNC => SYNC,
107 DOUT => SDO,
108 SCLK => SCK,
109 SMPCLK => SMPCLK -- OPEN
110 );
109 111
110 process(rstn,clk)
111 begin
112 if(rstn='0')then
113 pre <= (others=>'1');
114 N <= (others=>'1');
115 Reload <= '1';
116 DATA_IN <= (others=>'0');
117 WEN <= '1';
118 LOAD_ADDRESSN <= '1';
119 ADDRESS_IN <= (others=>'1');
120 INTERLEAVED <= '0';
121 DAC_CFG <= (others=>'0');
122 Rdata <= (others=>'0');
123 elsif(clk'event and clk='1')then
124
112 PROCESS(rstn, clk)
113 BEGIN
114 IF(rstn = '0')then
115 pre <= (OTHERS => '1');
116 N <= (OTHERS => '1');
117 Reload <= '1';
118 DATA_IN <= (OTHERS => '0');
119 WEN <= '1';
120 LOAD_ADDRESSN <= '1';
121 ADDRESS_IN <= (OTHERS => '1');
122 INTERLEAVED <= '0';
123 DAC_CFG <= (OTHERS => '0');
124 Rdata <= (OTHERS => '0');
125 ELSIF(clk'EVENT AND clk = '1')then
126
125 127
126 --APB Write OP
127 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
128 case apbi.paddr(abits-1 downto 2) is
129 when "000000" =>
130 DAC_CFG <= apbi.pwdata(3 downto 0);
131 Reload <= apbi.pwdata(4);
132 INTERLEAVED <= apbi.pwdata(5);
133 when "000001" =>
134 pre <= apbi.pwdata(PRESZ-1 downto 0);
135 when "000010" =>
136 N <= apbi.pwdata(CPTSZ-1 downto 0);
137 when "000011" =>
138 ADDRESS_IN <= apbi.pwdata(abits-1 downto 0);
139 LOAD_ADDRESSN <= '0';
140 when "000100" =>
141 DATA_IN <= apbi.pwdata(datawidth-1 downto 0);
142 WEN <= '0';
143 when others =>
144 null;
145 end case;
146 else
147 LOAD_ADDRESSN <= '1';
148 WEN <= '1';
149 end if;
128 --APB Write OP
129 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
130 CASE apbi.paddr(abits-1 DOWNTO 2) IS
131 WHEN "000000" =>
132 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
133 Reload <= apbi.pwdata(4);
134 INTERLEAVED <= apbi.pwdata(5);
135 WHEN "000001" =>
136 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
137 WHEN "000010" =>
138 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
139 WHEN "000011" =>
140 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
141 LOAD_ADDRESSN <= '0';
142 WHEN "000100" =>
143 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
144 WEN <= '0';
145 WHEN OTHERS =>
146 NULL;
147 END CASE;
148 ELSE
149 LOAD_ADDRESSN <= '1';
150 WEN <= '1';
151 END IF;
150 152
151 --APB Read OP
152 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
153 case apbi.paddr(abits-1 downto 2) is
154 when "000000" =>
155 Rdata(3 downto 0) <= DAC_CFG;
156 Rdata(4) <= Reload;
157 Rdata(5) <= INTERLEAVED;
158 Rdata(31 downto 6) <= (others => '0');
159 when "000001" =>
160 Rdata(PRESZ-1 downto 0) <= pre;
161 Rdata(31 downto PRESZ) <= (others => '0');
162 when "000010" =>
163 Rdata(CPTSZ-1 downto 0) <= N;
164 Rdata(31 downto CPTSZ) <= (others => '0');
165 when "000011" =>
166 Rdata(abits-1 downto 0) <= ADDRESS_OUT;
167 Rdata(31 downto abits) <= (others => '0');
168 when "000100" =>
169 Rdata(datawidth-1 downto 0) <= DATA_IN;
170 Rdata(31 downto datawidth) <= (others => '0');
171 when others =>
172 Rdata <= (others => '0');
173 end case;
174 end if;
153 --APB Read OP
154 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
155 CASE apbi.paddr(abits-1 DOWNTO 2) IS
156 WHEN "000000" =>
157 Rdata(3 DOWNTO 0) <= DAC_CFG;
158 Rdata(4) <= Reload;
159 Rdata(5) <= INTERLEAVED;
160 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
161 WHEN "000001" =>
162 Rdata(PRESZ-1 DOWNTO 0) <= pre;
163 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
164 WHEN "000010" =>
165 Rdata(CPTSZ-1 DOWNTO 0) <= N;
166 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
167 WHEN "000011" =>
168 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
169 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
170 WHEN "000100" =>
171 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
172 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
173 WHEN OTHERS =>
174 Rdata <= (OTHERS => '0');
175 END CASE;
176 END IF;
175 177
176 end if;
177 apbo.pconfig <= pconfig;
178 end process;
178 END IF;
179 apbo.pconfig <= pconfig;
180 END PROCESS;
179 181
180 apbo.prdata <= Rdata when apbi.penable = '1';
181 end architecture ar_apb_lfr_cal; No newline at end of file
182 apbo.prdata <= Rdata WHEN apbi.penable = '1';
183 END ARCHITECTURE ar_apb_lfr_cal;
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@@ -19,128 +19,128
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 24 LIBRARY techmap;
25 25 USE techmap.gencomp.ALL;
26 26
27 library lpp;
28 use lpp.lpp_cna.all;
27 LIBRARY lpp;
28 USE lpp.lpp_cna.ALL;
29 29
30 30
31 entity lfr_cal_driver is
32 generic(
33 tech : integer := 0;
34 PRESZ : integer range 1 to 32:=4;
35 PREMAX : integer := 16#FFFFFF#;
36 CPTSZ : integer range 1 to 32:=16;
37 datawidth : integer := 18;
38 abits : integer := 8
39 );
40 Port (
41 clk : in STD_LOGIC;
42 rstn : in STD_LOGIC;
43 pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
44 N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
45 Reload : in std_logic;
46 DATA_IN : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
47 WEN : in STD_LOGIC;
48 LOAD_ADDRESSN : IN STD_LOGIC;
49 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 downto 0);
50 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
51 INTERLEAVED : IN STD_LOGIC;
52 DAC_CFG : IN STD_LOGIC_VECTOR(3 downto 0);
53 SYNC : out STD_LOGIC;
54 DOUT : out STD_LOGIC;
55 SCLK : out STD_LOGIC;
56 SMPCLK : out STD_lOGIC
57 );
58 end lfr_cal_driver;
59
60 architecture Behavioral of lfr_cal_driver is
61 constant dacresolution : integer := 12;
62 signal RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 downto 0);
63 signal RAM_WEN : STD_LOGIC;
64 signal RAM_WADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
65 signal RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 downto 0);
66 signal RAM_RADDR : STD_LOGIC_VECTOR(abits-1 downto 0);
67 signal RAM_REN : STD_LOGIC;
68 signal DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 downto 0);
69 signal SMP_CLK : STD_LOGIC;
70 signal DAC_INPUT : STD_LOGIC_VECTOR(15 downto 0);
71
72 begin
73
74 ADDRESS_OUT <= RAM_WADDR;
75 DAC_INPUT <= DAC_CFG & DAC_DATA;
76 SMPCLK <= SMP_CLK;
31 ENTITY lfr_cal_driver IS
32 GENERIC(
33 tech : INTEGER := 0;
34 PRESZ : INTEGER RANGE 1 TO 32 := 4;
35 PREMAX : INTEGER := 16#FFFFFF#;
36 CPTSZ : INTEGER RANGE 1 TO 32 := 16;
37 datawidth : INTEGER := 18;
38 abits : INTEGER := 8
39 );
40 PORT (
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 pre : IN STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
44 N : IN STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
45 Reload : IN STD_LOGIC;
46 DATA_IN : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
47 WEN : IN STD_LOGIC;
48 LOAD_ADDRESSN : IN STD_LOGIC;
49 ADDRESS_IN : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
50 ADDRESS_OUT : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
51 INTERLEAVED : IN STD_LOGIC;
52 DAC_CFG : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 SYNC : OUT STD_LOGIC;
54 DOUT : OUT STD_LOGIC;
55 SCLK : OUT STD_LOGIC;
56 SMPCLK : OUT STD_LOGIC
57 );
58 END lfr_cal_driver;
77 59
78 dac_drv: SPI_DAC_DRIVER
79 Generic map(
80 datawidth => 16,
81 MSBFIRST => 1
82 )
83 Port map(
84 clk => clk,
85 rstn => rstn,
86 DATA => DAC_INPUT,
87 SMP_CLK => SMP_CLK,
88 SYNC => SYNC,
89 DOUT => DOUT,
90 SCLK => SCLK
91 );
60 ARCHITECTURE Behavioral OF lfr_cal_driver IS
61 CONSTANT dacresolution : INTEGER := 12;
62 SIGNAL RAM_DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
63 SIGNAL RAM_WEN : STD_LOGIC;
64 SIGNAL RAM_WADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
65 SIGNAL RAM_DATA_OUT : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
66 SIGNAL RAM_RADDR : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
67 SIGNAL RAM_REN : STD_LOGIC;
68 SIGNAL DAC_DATA : STD_LOGIC_VECTOR(dacresolution-1 DOWNTO 0);
69 SIGNAL SMP_CLK : STD_LOGIC;
70 SIGNAL DAC_INPUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
71
72 BEGIN
73
74 ADDRESS_OUT <= RAM_WADDR;
75 DAC_INPUT <= DAC_CFG & DAC_DATA;
76 SMPCLK <= SMP_CLK;
92 77
93 freqGen: dynamic_freq_div
94 generic map(
95 PRESZ => PRESZ,
96 PREMAX => PREMAX,
97 CPTSZ => CPTSZ
98 )
99 Port map( clk => clk,
100 rstn => rstn,
101 pre => pre,
102 N => N,
103 Reload => Reload,
104 clk_out => SMP_CLK
105 );
106
107
108 ramWr: RAM_WRITER
109 Generic map(
110 datawidth => datawidth,
111 abits => abits
112 )
113 Port map(
114 clk => clk,
115 rstn => rstn,
116 DATA_IN => DATA_IN,
117 DATA_OUT => RAM_DATA_IN,
118 WEN_IN => WEN,
119 WEN_OUT => RAM_WEN,
120 LOAD_ADDRESSN => LOAD_ADDRESSN,
121 ADDRESS_IN => ADDRESS_IN,
122 ADDRESS_OUT => RAM_WADDR
123 );
124
125 ramRd: RAM_READER
126 Generic map(
127 datawidth => datawidth,
128 dacresolution => dacresolution,
129 abits => abits
130 )
131 Port map(
132 clk => clk,
133 rstn => rstn,
134 DATA_IN => RAM_DATA_OUT,
135 ADDRESS => RAM_RADDR,
136 REN => RAM_REN,
137 DATA_OUT => DAC_DATA,
138 SMP_CLK => SMP_CLK,
139 INTERLEAVED => INTERLEAVED
78 dac_drv : SPI_DAC_DRIVER
79 GENERIC MAP(
80 datawidth => 16,
81 MSBFIRST => 1
82 )
83 PORT MAP(
84 clk => clk,
85 rstn => rstn,
86 DATA => DAC_INPUT,
87 SMP_CLK => SMP_CLK,
88 SYNC => SYNC,
89 DOUT => DOUT,
90 SCLK => SCLK
91 );
92
93 freqGen : dynamic_freq_div
94 GENERIC MAP(
95 PRESZ => PRESZ,
96 PREMAX => PREMAX,
97 CPTSZ => CPTSZ
98 )
99 PORT MAP(clk => clk,
100 rstn => rstn,
101 pre => pre,
102 N => N,
103 Reload => Reload,
104 clk_out => SMP_CLK
140 105 );
141 106
142 SRAM : syncram_2p
143 GENERIC MAP(tech, abits, datawidth)
144 PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
107
108 ramWr : RAM_WRITER
109 GENERIC MAP(
110 datawidth => datawidth,
111 abits => abits
112 )
113 PORT MAP(
114 clk => clk,
115 rstn => rstn,
116 DATA_IN => DATA_IN,
117 DATA_OUT => RAM_DATA_IN,
118 WEN_IN => WEN,
119 WEN_OUT => RAM_WEN,
120 LOAD_ADDRESSN => LOAD_ADDRESSN,
121 ADDRESS_IN => ADDRESS_IN,
122 ADDRESS_OUT => RAM_WADDR
123 );
145 124
146 end Behavioral;
125 ramRd : RAM_READER
126 GENERIC MAP(
127 datawidth => datawidth,
128 dacresolution => dacresolution,
129 abits => abits
130 )
131 PORT MAP(
132 clk => clk,
133 rstn => rstn,
134 DATA_IN => RAM_DATA_OUT,
135 ADDRESS => RAM_RADDR,
136 REN => RAM_REN,
137 DATA_OUT => DAC_DATA,
138 SMP_CLK => SMP_CLK,
139 INTERLEAVED => INTERLEAVED
140 );
141
142 SRAM : syncram_2p
143 GENERIC MAP(tech, abits, datawidth)
144 PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
145
146 END Behavioral; No newline at end of file
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