# HG changeset patch
# User pellion
# Date 2015-02-06 11:52:46
# Node ID 1e4a9714222ade6d03611444824ec356fd4a6378
# Parent  5eb17174cdba3829f81508f11febc9e271dd08b3

ADD LPP_CNA (and CAL to LFR-em)

diff --git a/APB_DEVICES/apb_devices_list.txt b/APB_DEVICES/apb_devices_list.txt
--- a/APB_DEVICES/apb_devices_list.txt
+++ b/APB_DEVICES/apb_devices_list.txt
@@ -16,3 +16,12 @@ device LPP_MATRIX 13
 device LPP_DELAY 14
 device LPP_USB 15
 device LPP_BALISE 16
+device LPP_DMA_TYPE 17
+device LPP_BOOTLOADER_TYPE 18
+device LPP_LFR 19
+device LPP_CLKSETTING 20
+device LPP_LFR_HK_DEVICE 21  
+device LPP_LFR_MANAGEMENT 22 
+device LPP_DEBUG_DMA A0
+device LPP_DEBUG_LFR A1   
+device LPP_DEBUG_LFR_ID A2
diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc
--- a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc
+++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc
@@ -84,7 +84,7 @@ set_io	TAG3	-pinname	L16	-fixed	yes	-DIR
 set_io	TAG4	-pinname	L15	-fixed	yes	-DIRECTION	Inout
 #set_io	TAG5	-pinname	M16	-fixed	yes	-DIRECTION	Inout
 #set_io	TAG6	-pinname	L13	-fixed	yes	-DIRECTION	Inout
-#set_io  TAG7	-pinname	P6	-fixed	yes	-DIRECTION	Inout
+#set_io TAG7	-pinname	P6	-fixed	yes	-DIRECTION	Inout
 set_io	TAG8	-pinname	R6	-fixed	yes	-DIRECTION	Inout
 #set_io	TAG9	-pinname	T4	-fixed	yes	-DIRECTION	Inout
 
diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd
--- a/designs/LFR-em-WFP_MS/LFR-em.vhd
+++ b/designs/LFR-em-WFP_MS/LFR-em.vhd
@@ -82,6 +82,11 @@ ENTITY LFR_em IS
     ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
     ADC_smpclk     : OUT   STD_LOGIC;
     ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
+    -- DAC --------------------------------------------------------------------
+    DAC_SDO    : OUT STD_LOGIC;
+    DAC_SCK    : OUT STD_LOGIC;
+    DAC_SYNC   : OUT STD_LOGIC;
+    DAC_CAL_EN : OUT STD_LOGIC;
     -- HK ---------------------------------------------------------------------
     HK_smpclk      : OUT   STD_LOGIC;
     ADC_OEB_bar_HK : OUT   STD_LOGIC;
@@ -253,6 +258,7 @@ BEGIN  -- beh
 -------------------------------------------------------------------------------
   apb_lfr_management_1 : apb_lfr_management
     GENERIC MAP (
+      tech             => apa3e,
       pindex           => 6,
       paddr            => 6,
       pmask            => 16#fff#,
@@ -270,6 +276,11 @@ BEGIN  -- beh
       HK_val        => sample_val,
       HK_sel        => HK_SEL, 
       
+      DAC_SDO           => DAC_SDO,
+      DAC_SCK            => DAC_SCK,
+      DAC_SYNC          => DAC_SYNC,
+      DAC_CAL_EN        => DAC_CAL_EN,     
+
       coarse_time   => coarse_time,
       fine_time     => fine_time,
       LFR_soft_rstn => LFR_soft_rstn
@@ -380,7 +391,7 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"01013A")  -- aa.bb.cc version
+      top_lfr_version        => X"01013B")  -- aa.bb.cc version
                                             -- AA : BOARD NUMBER
                                             --      0 => MINI_LFR
                                             --      1 => EM
diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/LFR-em-WFP_MS/Makefile
--- a/designs/LFR-em-WFP_MS/Makefile
+++ b/designs/LFR-em-WFP_MS/Makefile
@@ -18,7 +18,7 @@ VHDLSIMFILES=testbench.vhd
 #SIMTOP=testbench
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
-PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc
+PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
 
 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
@@ -38,7 +38,6 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt
 	./general_purpose/lpp_balise \
 	./general_purpose/lpp_delay \
 	./lpp_bootloader \
-	./lpp_cna \
 	./dsp/lpp_fft_rtax \
 	./lpp_uart \
 	./lpp_usb \
diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt
--- a/lib/lpp/dirs.txt
+++ b/lib/lpp/dirs.txt
@@ -11,10 +11,10 @@
 ./dsp/lpp_fft_rtax
 ./lpp_memory
 ./dsp/lpp_fft
+./lpp_cna
 ./lfr_management
 ./lpp_ad_Conv
 ./lpp_bootloader
-./lpp_cna
 ./lpp_spectral_matrix
 ./lpp_demux
 ./lpp_Header
diff --git a/lib/lpp/lfr_management/apb_lfr_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd
--- a/lib/lpp/lfr_management/apb_lfr_management.vhd
+++ b/lib/lpp/lfr_management/apb_lfr_management.vhd
@@ -29,11 +29,15 @@ USE lpp.apb_devices_list.ALL;
 USE lpp.general_purpose.ALL;
 USE lpp.lpp_lfr_management.ALL;
 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
+USE lpp.lpp_cna.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
 
 
 ENTITY apb_lfr_management IS
 
   GENERIC(
+    tech             : INTEGER := 0;
     pindex           : INTEGER := 0;        --! APB slave index
     paddr            : INTEGER := 0;        --! ADDR field of the APB BAR
     pmask            : INTEGER := 16#fff#;  --! MASK field of the APB BAR
@@ -55,6 +59,11 @@ ENTITY apb_lfr_management IS
     HK_val        : IN  STD_LOGIC;
     HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
     ---------------------------------------------------------------------------
+    DAC_SDO    : OUT STD_LOGIC;
+    DAC_SCK    : OUT STD_LOGIC;
+    DAC_SYNC   : OUT STD_LOGIC;
+    DAC_CAL_EN : OUT STD_LOGIC;
+    ---------------------------------------------------------------------------
     coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
     fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);  --! fine TIME
     ---------------------------------------------------------------------------
@@ -67,7 +76,7 @@ ARCHITECTURE Behavioral OF apb_lfr_manag
 
   CONSTANT REVISION : INTEGER := 1;
   CONSTANT pconfig : apb_config_type := (
-    0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
+    0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
     1 => apb_iobar(paddr, pmask)
     );
 
@@ -120,6 +129,27 @@ ARCHITECTURE Behavioral OF apb_lfr_manag
   SIGNAL previous_fine_time_bit : STD_LOGIC;
   
   SIGNAL rstn_LFR_TM : STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  -- DAC
+  -----------------------------------------------------------------------------
+  CONSTANT  PRESZ         : INTEGER := 8;
+  CONSTANT  CPTSZ         : INTEGER := 16;
+  CONSTANT  datawidth     : INTEGER := 18;
+  CONSTANT  dacresolution : INTEGER := 12;
+  CONSTANT  abits         : INTEGER := 8;
+  
+  SIGNAL pre           : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
+  SIGNAL N             : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
+  SIGNAL Reload        : STD_LOGIC;
+  SIGNAL DATA_IN       : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
+  SIGNAL WEN           : STD_LOGIC;
+  SIGNAL LOAD_ADDRESSN : STD_LOGIC;
+  SIGNAL ADDRESS_IN    : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL ADDRESS_OUT   : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL INTERLEAVED   : STD_LOGIC;
+  SIGNAL DAC_CFG       : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL DAC_CAL_EN_s  : STD_LOGIC;
   
 BEGIN
 
@@ -141,7 +171,18 @@ BEGIN
       soft_tick           <= '0';
 
       coarsetime_reg_updated <= '0';
-
+      --DAC
+      pre           <= (OTHERS => '1');
+      N             <= (OTHERS => '1');
+      Reload        <= '1';
+      DATA_IN       <= (OTHERS => '0');
+      WEN           <= '1';
+      LOAD_ADDRESSN <= '1';
+      ADDRESS_IN    <= (OTHERS => '1');
+      INTERLEAVED   <= '0';
+      DAC_CFG       <= (OTHERS => '0');
+      --
+      DAC_CAL_EN_s <= '0';
     ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
       coarsetime_reg_updated <= '0';
 
@@ -190,6 +231,24 @@ BEGIN
           WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
             Rdata(31 DOWNTO 16) <= (OTHERS => '0');
             Rdata(15 DOWNTO 0)  <= r.HK_temp_2;
+          WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
+            Rdata(3 DOWNTO 0)  <= DAC_CFG;
+            Rdata(4)           <= Reload;
+            Rdata(5)           <= INTERLEAVED;
+            Rdata(6)           <= DAC_CAL_EN_s;
+            Rdata(31 DOWNTO 7) <= (OTHERS => '0');
+          WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
+            Rdata(PRESZ-1 DOWNTO 0) <= pre;
+            Rdata(31 DOWNTO PRESZ)  <= (OTHERS => '0');
+          WHEN ADDR_LFR_MANAGMENT_DAC_N =>
+            Rdata(CPTSZ-1 DOWNTO 0) <= N;
+            Rdata(31 DOWNTO CPTSZ)  <= (OTHERS => '0');
+          WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
+            Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
+            Rdata(31 DOWNTO abits)  <= (OTHERS => '0');
+          WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
+            Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
+            Rdata(31 DOWNTO datawidth)  <= (OTHERS => '0');
           WHEN OTHERS =>
             Rdata(31 DOWNTO 0) <= (OTHERS => '0');
         END CASE;
@@ -204,10 +263,28 @@ BEGIN
             WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
               r.coarse_time_load     <= apbi.pwdata(30 DOWNTO 0);
               coarsetime_reg_updated <= '1';
+          WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
+            DAC_CFG      <= apbi.pwdata(3 DOWNTO 0);
+            Reload       <= apbi.pwdata(4);
+            INTERLEAVED  <= apbi.pwdata(5);
+            DAC_CAL_EN_s <= apbi.pwdata(6);
+          WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
+            pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
+          WHEN ADDR_LFR_MANAGMENT_DAC_N =>
+            N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
+          WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
+            ADDRESS_IN    <= apbi.pwdata(abits-1 DOWNTO 0);
+            LOAD_ADDRESSN <= '0';
+          WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
+            DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
+            WEN     <= '0';
+              
             WHEN OTHERS =>
               NULL;
           END CASE;
         ELSE
+          LOAD_ADDRESSN <= '1';
+          WEN           <= '1';
           IF r.ctrl = '1' THEN
             r.ctrl <= '0';
           END IF;
@@ -393,5 +470,38 @@ BEGIN
   END PROCESS;
 
   HK_sel <= HK_sel_s;
-  
+
+  -----------------------------------------------------------------------------
+  -- DAC
+  -----------------------------------------------------------------------------
+  cal : lfr_cal_driver
+    GENERIC MAP(
+      tech      => tech,
+      PRESZ     => PRESZ,
+      CPTSZ     => CPTSZ,
+      datawidth => datawidth,
+      abits     => abits
+      )
+    PORT MAP(
+      clk           => clk25MHz,
+      rstn          => resetn,
+      
+      pre           => pre,
+      N             => N,
+      Reload        => Reload,
+      DATA_IN       => DATA_IN,
+      WEN           => WEN,
+      LOAD_ADDRESSN => LOAD_ADDRESSN,
+      ADDRESS_IN    => ADDRESS_IN,
+      ADDRESS_OUT   => ADDRESS_OUT,
+      INTERLEAVED   => INTERLEAVED,
+      DAC_CFG       => DAC_CFG,
+      
+      SYNC          => DAC_SYNC,
+      DOUT          => DAC_SDO,
+      SCLK          => DAC_SCK,
+      SMPCLK        => OPEN --DAC_SMPCLK
+      );
+
+  DAC_CAL_EN <= DAC_CAL_EN_s;
 END Behavioral;
\ No newline at end of file
diff --git a/lib/lpp/lfr_management/lpp_lfr_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd
--- a/lib/lpp/lfr_management/lpp_lfr_management.vhd
+++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd
@@ -31,6 +31,7 @@ PACKAGE lpp_lfr_management IS
 
   COMPONENT apb_lfr_management
     GENERIC (
+      tech             : INTEGER;
       pindex           : INTEGER;
       paddr            : INTEGER;
       pmask            : INTEGER;
@@ -46,6 +47,10 @@ PACKAGE lpp_lfr_management IS
       HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
       HK_val        : IN  STD_LOGIC;
       HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      DAC_SDO    : OUT STD_LOGIC;
+      DAC_SCK    : OUT STD_LOGIC;
+      DAC_SYNC   : OUT STD_LOGIC;
+      DAC_CAL_EN : OUT STD_LOGIC;
       coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
       LFR_soft_rstn : OUT STD_LOGIC);
diff --git a/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
--- a/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
+++ b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
@@ -11,5 +11,10 @@ PACKAGE lpp_lfr_management_apbreg_pkg IS
   CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
   CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
   CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2        : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
+  CONSTANT ADDR_LFR_MANAGMENT_DAC_CONTROL      : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
+  CONSTANT ADDR_LFR_MANAGMENT_DAC_PRE          : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
+  CONSTANT ADDR_LFR_MANAGMENT_DAC_N            : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
+  CONSTANT ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT  : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
+  CONSTANT ADDR_LFR_MANAGMENT_DAC_DATA_IN      : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
   
 END lpp_lfr_management_apbreg_pkg;
diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd
--- a/lib/lpp/lpp_amba/apb_devices_list.vhd
+++ b/lib/lpp/lpp_amba/apb_devices_list.vhd
@@ -39,7 +39,7 @@ PACKAGE apb_devices_list IS
   CONSTANT LPP_LFR             : amba_device_type := 16#19#;
   CONSTANT LPP_CLKSETTING      : amba_device_type := 16#20#;
   CONSTANT LPP_LFR_HK_DEVICE   : amba_device_type := 16#21#;
-  
+  CONSTANT LPP_LFR_MANAGEMENT  : amba_device_type := 16#22#;
   CONSTANT LPP_DEBUG_DMA       : amba_device_type := 16#A0#;
   CONSTANT LPP_DEBUG_LFR       : amba_device_type := 16#A1#;
 
diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/APB_DAC.vhd
+++ /dev/null
@@ -1,143 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                        Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-use lpp.general_purpose.all;
-use lpp.lpp_cna.all;
-
---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
-
-entity APB_DAC is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8;
-    Nmax     : integer := 7);
-  port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
-    DataIN  : in std_logic_vector(15 downto 0);
-    Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
-    Readn   : out std_logic;
-    SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
-    SCLK    : out std_logic;           --! Horloge systeme du convertisseur
-    CLK_VAR : out std_logic;
-    DATA    : out std_logic            --! Donn�e num�rique s�rialis�
-    );
-end entity;
-
---! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
---! et les sorties seront cabl�es vers le convertisseur. 
-
-architecture ar_APB_DAC of APB_DAC is
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-signal clkdiv   : std_logic;
-signal clkvar    : std_logic;
-signal enable   : std_logic;
-signal Ready    : std_logic;
-signal N        : integer range 0 to Nmax;
-
-type DAC_ctrlr_Reg is record
-     DAC_Cfg  : std_logic_vector(0 downto 0);
-     CLK_Cfg  : std_logic_vector(2 downto 0);
-end record;
-
-signal Rec : DAC_ctrlr_Reg;
-signal Rdata     : std_logic_vector(31 downto 0);
-
-begin
-
-enable <= Rec.DAC_Cfg(0);
-
-N <= to_integer(unsigned(Rec.CLK_Cfg));
-
-    CLK0 : Clock_Divider
-        generic map (308)        --clkdiv = 80KHz
-        port map (clk,rst,clkdiv);
-
-    CLKSET : ClkSetting
-        generic map(Nmax)
-        port map(clkdiv,rst,N,clkvar);
-
-    CONV0 : DacDriver
---        generic map (cpt_serial)
-        port map(clk,rst,clkvar,enable,DataIN,SYNC,SCLK,Readn,Data);
-
- CLK_VAR <=  clkvar;
-
-    process(rst,clk)
-    begin
-        if(rst='0')then
-            Rec.CLK_Cfg <=  (others => '0');
-
-        elsif(clk'event and clk='1')then 
-        
-
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                        Rec.DAC_Cfg(0) <= apbi.pwdata(0);
-                        Rec.CLK_Cfg    <= apbi.pwdata(6 downto 4);
-                    when others =>
-                        null;
-                end case;
-            end if;
-
-    --APB Read OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                        Rdata(31 downto 7) <= (others => '0');
-                        Rdata(6 downto 4)  <= Rec.CLK_Cfg;
-                        Rdata(3 downto 1) <= (others => '0');
-                        Rdata(0 downto 0)  <= Rec.DAC_Cfg;
-                    when others =>
-                        Rdata <= (others => '0');
-                end case;
-            end if;
-
-        end if;
-        apbo.pconfig <= pconfig;
-    end process;
-
-apbo.prdata     <=   Rdata when apbi.penable = '1';
-Cal_EN <= enable;
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/APB_LFR_CAL.vhd b/lib/lpp/lpp_cna/APB_LFR_CAL.vhd
--- a/lib/lpp/lpp_cna/APB_LFR_CAL.vhd
+++ b/lib/lpp/lpp_cna/APB_LFR_CAL.vhd
@@ -19,163 +19,165 @@
 --                        Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@member.fsf.org
 ------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.lpp_cna.all;
-use lpp.apb_devices_list.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+USE grlib.devices.ALL;
+LIBRARY lpp;
+USE lpp.lpp_amba.ALL;
+USE lpp.lpp_cna.ALL;
+USE lpp.apb_devices_list.ALL;
 
-entity apb_lfr_cal is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    tech     : integer := 0;
-    PRESZ    : integer := 8;
-    CPTSZ    : integer := 16;
-    datawidth : integer := 18;
-    dacresolution : integer := 12;
-    abits     : integer := 8
+ENTITY apb_lfr_cal IS
+  GENERIC (
+    pindex        : INTEGER := 0;
+    paddr         : INTEGER := 0;
+    pmask         : INTEGER := 16#fff#;
+    tech          : INTEGER := 0;
+    PRESZ         : INTEGER := 8;
+    CPTSZ         : INTEGER := 16;
+    datawidth     : INTEGER := 18;
+    dacresolution : INTEGER := 12;
+    abits         : INTEGER := 8
     );
-  port (
-    rstn    : in  std_logic;
-    clk     : in  std_logic;
-    apbi    : in  apb_slv_in_type;
-    apbo    : out apb_slv_out_type;
-    SDO     : out  std_logic;
-    SCK     : out  std_logic;
-    SYNC    : out  std_logic;
-    SMPCLK  : out  std_logic
+  PORT (
+    rstn   : IN  STD_LOGIC;
+    clk    : IN  STD_LOGIC;
+    apbi   : IN  apb_slv_in_type;
+    apbo   : OUT apb_slv_out_type;
+    SDO    : OUT STD_LOGIC;
+    SCK    : OUT STD_LOGIC;
+    SYNC   : OUT STD_LOGIC;
+    SMPCLK : OUT STD_LOGIC
     );
-end entity;
+END ENTITY;
 
 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
 --! et les sorties seront cabl�es vers le convertisseur.
 
-architecture ar_apb_lfr_cal of apb_lfr_cal is
+ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
 
-constant REVISION : integer := 1;
+  CONSTANT REVISION : INTEGER := 1;
 
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
+  CONSTANT pconfig : apb_config_type := (
+    0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
+    1 => apb_iobar(paddr, pmask));
 
-signal pre             : STD_LOGIC_VECTOR(PRESZ-1 downto 0);
-signal N               : STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
-signal Reload          : std_logic;
-signal DATA_IN         : STD_LOGIC_VECTOR(datawidth-1 downto 0);
-signal WEN             : STD_LOGIC;
-signal LOAD_ADDRESSN   : STD_LOGIC;
-signal ADDRESS_IN      : STD_LOGIC_VECTOR(abits-1 downto 0);
-signal ADDRESS_OUT     : STD_LOGIC_VECTOR(abits-1 downto 0);
-signal INTERLEAVED     : STD_LOGIC;
-signal DAC_CFG         : STD_LOGIC_VECTOR(3 downto 0);
-signal Rdata           : std_logic_vector(31 downto 0);
+  SIGNAL pre           : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
+  SIGNAL N             : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
+  SIGNAL Reload        : STD_LOGIC;
+  SIGNAL DATA_IN       : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
+  SIGNAL WEN           : STD_LOGIC;
+  SIGNAL LOAD_ADDRESSN : STD_LOGIC;
+  SIGNAL ADDRESS_IN    : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL ADDRESS_OUT   : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL INTERLEAVED   : STD_LOGIC;
+  SIGNAL DAC_CFG       : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL Rdata         : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
-begin
+BEGIN
 
-cal: lfr_cal_driver
-    generic map(
-        tech      => tech,
-        PRESZ     => PRESZ,
-        CPTSZ     => CPTSZ,
-        datawidth => datawidth,
-        abits     => abits
-     )
-    Port map(
-        clk             => clk,
-        rstn            => rstn,
-        pre             => pre,
-        N               => N,
-        Reload          => Reload,
-        DATA_IN         => DATA_IN,
-        WEN             => WEN,
-        LOAD_ADDRESSN   => LOAD_ADDRESSN,
-        ADDRESS_IN      => ADDRESS_IN,
-        ADDRESS_OUT     => ADDRESS_OUT,
-        INTERLEAVED     => INTERLEAVED,
-        DAC_CFG         => DAC_CFG,
-        SYNC            => SYNC,
-        DOUT            => SDO,
-        SCLK            => SCK,
-        SMPCLK          => SMPCLK
-              );
+  cal : lfr_cal_driver
+    GENERIC MAP(
+      tech      => tech,
+      PRESZ     => PRESZ,
+      CPTSZ     => CPTSZ,
+      datawidth => datawidth,
+      abits     => abits
+      )
+    PORT MAP(
+      clk           => clk,
+      rstn          => rstn,
+      
+      pre           => pre,
+      N             => N,
+      Reload        => Reload,
+      DATA_IN       => DATA_IN,
+      WEN           => WEN,
+      LOAD_ADDRESSN => LOAD_ADDRESSN,
+      ADDRESS_IN    => ADDRESS_IN,
+      ADDRESS_OUT   => ADDRESS_OUT,
+      INTERLEAVED   => INTERLEAVED,
+      DAC_CFG       => DAC_CFG,
+      
+      SYNC          => SYNC,
+      DOUT          => SDO,
+      SCLK          => SCK,
+      SMPCLK        => SMPCLK           -- OPEN
+      );
 
-    process(rstn,clk)
-    begin
-        if(rstn='0')then
-           pre           <= (others=>'1');
-           N             <= (others=>'1');
-           Reload        <= '1';
-           DATA_IN       <= (others=>'0');
-           WEN           <= '1';
-           LOAD_ADDRESSN <= '1';
-           ADDRESS_IN    <= (others=>'1');
-           INTERLEAVED   <= '0';
-           DAC_CFG       <= (others=>'0');
-           Rdata         <= (others=>'0');
-        elsif(clk'event and clk='1')then 
-        
+  PROCESS(rstn, clk)
+  BEGIN
+    IF(rstn = '0')then
+      pre           <= (OTHERS => '1');
+      N             <= (OTHERS => '1');
+      Reload        <= '1';
+      DATA_IN       <= (OTHERS => '0');
+      WEN           <= '1';
+      LOAD_ADDRESSN <= '1';
+      ADDRESS_IN    <= (OTHERS => '1');
+      INTERLEAVED   <= '0';
+      DAC_CFG       <= (OTHERS => '0');
+      Rdata         <= (OTHERS => '0');
+    ELSIF(clk'EVENT AND clk = '1')then
+
 
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                        DAC_CFG     <= apbi.pwdata(3 downto 0);
-                        Reload      <= apbi.pwdata(4);
-                        INTERLEAVED <= apbi.pwdata(5);
-                    when "000001" =>
-                         pre        <= apbi.pwdata(PRESZ-1 downto 0);
-                    when "000010" =>
-                         N          <= apbi.pwdata(CPTSZ-1 downto 0);
-                    when "000011" =>
-                         ADDRESS_IN <= apbi.pwdata(abits-1 downto 0);
-                         LOAD_ADDRESSN <= '0';
-                    when "000100" =>
-                         DATA_IN    <= apbi.pwdata(datawidth-1 downto 0);
-                         WEN        <= '0';
-                    when others =>
-                        null;
-                end case;
-            else
-                LOAD_ADDRESSN <= '1';
-                WEN           <= '1';
-            end if;
+      --APB Write OP
+      IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
+        CASE apbi.paddr(abits-1 DOWNTO 2) IS
+          WHEN "000000" =>
+            DAC_CFG     <= apbi.pwdata(3 DOWNTO 0);
+            Reload      <= apbi.pwdata(4);
+            INTERLEAVED <= apbi.pwdata(5);
+          WHEN "000001" =>
+            pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
+          WHEN "000010" =>
+            N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
+          WHEN "000011" =>
+            ADDRESS_IN    <= apbi.pwdata(abits-1 DOWNTO 0);
+            LOAD_ADDRESSN <= '0';
+          WHEN "000100" =>
+            DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
+            WEN     <= '0';
+          WHEN OTHERS =>
+            NULL;
+        END CASE;
+      ELSE
+        LOAD_ADDRESSN <= '1';
+        WEN           <= '1';
+      END IF;
 
-    --APB Read OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                         Rdata(3 downto 0)  <= DAC_CFG;
-                         Rdata(4)           <= Reload;
-                         Rdata(5)           <= INTERLEAVED;
-                         Rdata(31 downto 6) <= (others => '0');
-                    when "000001" =>
-                         Rdata(PRESZ-1 downto 0)  <= pre;
-                         Rdata(31 downto PRESZ)   <= (others => '0');
-                    when "000010" =>
-                         Rdata(CPTSZ-1 downto 0)  <= N;
-                         Rdata(31 downto CPTSZ)   <= (others => '0');
-                    when "000011" =>
-                         Rdata(abits-1 downto 0)  <= ADDRESS_OUT;
-                         Rdata(31 downto abits)   <= (others => '0');
-                    when "000100" =>
-                         Rdata(datawidth-1 downto 0)  <= DATA_IN;
-                         Rdata(31 downto datawidth)   <= (others => '0');
-                    when others =>
-                         Rdata <= (others => '0');
-                end case;
-            end if;
+      --APB Read OP
+      IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
+        CASE apbi.paddr(abits-1 DOWNTO 2) IS
+          WHEN "000000" =>
+            Rdata(3 DOWNTO 0)  <= DAC_CFG;
+            Rdata(4)           <= Reload;
+            Rdata(5)           <= INTERLEAVED;
+            Rdata(31 DOWNTO 6) <= (OTHERS => '0');
+          WHEN "000001" =>
+            Rdata(PRESZ-1 DOWNTO 0) <= pre;
+            Rdata(31 DOWNTO PRESZ)  <= (OTHERS => '0');
+          WHEN "000010" =>
+            Rdata(CPTSZ-1 DOWNTO 0) <= N;
+            Rdata(31 DOWNTO CPTSZ)  <= (OTHERS => '0');
+          WHEN "000011" =>
+            Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
+            Rdata(31 DOWNTO abits)  <= (OTHERS => '0');
+          WHEN "000100" =>
+            Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
+            Rdata(31 DOWNTO datawidth)  <= (OTHERS => '0');
+          WHEN OTHERS =>
+            Rdata <= (OTHERS => '0');
+        END CASE;
+      END IF;
 
-        end if;
-        apbo.pconfig <= pconfig;
-    end process;
+    END IF;
+    apbo.pconfig <= pconfig;
+  END PROCESS;
 
-apbo.prdata     <=   Rdata when apbi.penable = '1';
-end architecture ar_apb_lfr_cal;
\ No newline at end of file
+  apbo.prdata <= Rdata WHEN apbi.penable = '1';
+END ARCHITECTURE ar_apb_lfr_cal;
diff --git a/lib/lpp/lpp_cna/ClkSetting.vhd b/lib/lpp/lpp_cna/ClkSetting.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/ClkSetting.vhd
+++ /dev/null
@@ -1,59 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_arith.all; 
-use IEEE.std_logic_unsigned.all;
-
---! Programme qui va permetre de g�n�rer une horloge systeme (sclk) parametrable
-
-entity ClkSetting is
-generic(Nmax    : integer := 7);   
-port( 
-    clk, rst   : in std_logic;   --! Horloge et Reset globale
-    N          : in integer range 0 to Nmax;
-    sclk       : out std_logic   --! Horloge Systeme g�n�r�e
-);
-end entity;
-
---! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
-architecture ar_ClkSetting of ClkSetting is
-
-signal clockint : std_logic_vector(Nmax downto 0);
-
-begin 
-    process (clk,rst)
-        begin
-        if(rst = '0') then
-            clockint <= (others => '0');
-        
-        elsif (clk' event and clk='1') then
-
-            clockint <= clockint + 1;
-
-        end if;
-    end process;
-
-sclk <= clk when N=0 else clockint(N-1);
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/DacDriver.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library lpp;
-use lpp.lpp_cna.all;
-
---! Programme du Convertisseur Num�rique/Analogique
-
-entity DacDriver is
---generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
-  port(
-    clk         : in std_logic;                        --! Horloge du composant
-    rst         : in std_logic;                        --! Reset general du composant
-    SysClk      : in std_logic;
-    enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-    Data_IN     : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
-    SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
-    SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-    Readn       : out std_logic;
---    Ready       : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
-    Data        : out std_logic                        --! Donn�e num�rique s�rialis�
-    );
-end entity;
-
-
-architecture ar_DacDriver of DacDriver is
-
---signal s_SCLK      : std_logic;
-signal Send    : std_logic;
-signal Sended : std_logic;
-
-begin
-
---SystemCLK : entity work.Clock_Divider
---    generic map (cpt_serial)
---    port map (clk,rst,s_SCLK);
-
-
-Signal_sync : Gene_SYNC
-    port map (SysClk,rst,clk,enable,Sended,Send,Readn,SYNC);
-
-
-Serial : serialize
-    port map (clk,rst,clk,Data_IN,Send,Sended,Data);
-
---RenGEN : entity work.ReadFifo_GEN
---    port map (clk,rst,Send,Readn);
-
-SCLK        <= clk;
---Ready <= s_Rdy;
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/Gene_SYNC.vhd b/lib/lpp/lpp_cna/Gene_SYNC.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/Gene_SYNC.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---! Programme qui va permettre de g�n�rer le signal SYNC
-
-entity Gene_SYNC is
-  port(
-    SysClk,raz : in std_logic;     --! Horloge systeme et Reset du composant
-    SCLK : in std_logic;
-    enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-    sended : in std_logic;
-    send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
-    Readn : out std_logic;
-    SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
-    );
-end Gene_SYNC;
-
-
-architecture ar_Gene_SYNC of Gene_SYNC is
-
---signal count : integer;
-signal SysClk_reg : std_logic;
-
-type etat is (e0,e1,e2,e3);
-signal ect : etat;
-
-begin 
-    process (SCLK,raz)
-    begin
-        if(raz='0')then
-            ect <= e0;
-            SYNC <= '1';
-            Readn <= '1';
-----            count <= 14;  
-            Send <= '0';
-        
-        elsif(SCLK' event and SCLK='1')then 
-            SysClk_reg <= SysClk;
-               
-            if(enable='1')then
-                
-                case ect is
-                    when e0 => 
-                        if(SysClk_reg='0' and SysClk='1')then
---                            SYNC <= '0';
-                            Readn <= '0';
-                            Send <= '1';
-                            ect <= e1;
-                        end if;
-                
-                    when e1 =>
-                        Readn <= '1';
---                        SYNC <= '0';
-                        send <= '0';
-                        ect <= e2;
-
-                    when e2 =>
-                        SYNC <= '0';
-                        ect <= e3;
-
-                    when e3 =>
-                        if(sended='1')then
-                            SYNC <= '1';                            
-                            ect <= e0;
-                        end if;
-                        
---                        if(count=15)then
---                            SYNC <= '1';
---                            count <= count+1;
---                        if(Ready='1')then
-----                            count <= 0;
---                            SYNC <= '1';
---                            
---                            ect <= e0;
-----                            count <= count+1;
---                            Send <= '0';                           
---                        end if;
-
-                end case;
-            end if;
-      	end if;
-    end process;
-end ar_Gene_SYNC;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
+++ /dev/null
@@ -1,67 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity ReadFifo_GEN is
-  port(
-    clk,raz : in std_logic;                      --! Horloge et Reset du composant
-    SYNC : in std_logic;
-    Readn : out std_logic
-    );
-end entity;
-
-
-architecture ar_ReadFifo_GEN of ReadFifo_GEN is
-
-type etat is (eX,e0);
-signal ect      : etat;
-
-signal SYNC_reg : std_logic;
-
-begin
-    process(clk,raz)
-        begin
-        if(raz='0')then           
-            ect         <= eX;
-            Readn  <= '1';           
-
-        elsif(clk'event and clk='1')then
-            SYNC_reg <= SYNC;
-          
-            case ect is
-                when eX =>                     
-                    if (SYNC_reg='0' and  SYNC='1') then 
-                        Readn    <= '0';                   
-                        ect     <= e0;
-                    end if;
-
-                when e0 =>
-                    Readn <= '1';                    
-                    ect <= eX;
-
-            end case;
-        end if;
-    end process;
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/Serialize.vhd b/lib/lpp/lpp_cna/Serialize.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/Serialize.vhd
+++ /dev/null
@@ -1,124 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
---! Programme qui permet de s�rialiser un vecteur
-
-entity Serialize is
-  port(
-    clk,raz : in std_logic;                      --! Horloge et Reset du composant
-    sclk    : in std_logic;                      --! Horloge Systeme
-    vectin  : in std_logic_vector(15 downto 0);  --! Vecteur d'entr�e
-    send    : in std_logic;                      --! Flag, Une nouvelle donn�e est pr�sente
-    sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
-    Data    : out std_logic                      --! Donn�e num�rique s�rialis�
-    );
-end Serialize;
-
-
-architecture ar_Serialize of Serialize is
-
-type etat is (chargemT,serialize);
-signal ect      : etat;
-
-signal vector_int   : std_logic_vector(16 downto 0);
---signal vectin_reg   : std_logic_vector(15 downto 0);
---signal load         : std_logic;
-signal send_reg         : std_logic;
-
-signal N            : integer range 0 to 16;
-signal CPT_ended    : std_logic:='0';
-
-begin
-    process(clk,raz)
-        begin
-        if(raz='0')then           
-            ect         <= chargemT;
---            vectin_reg  <= (others=> '0');
---            load        <= '0';
-            sended      <= '1';            
-
-        elsif(clk'event and clk='1')then 
-            
---            vectin_reg <= vectin;
-          
-            case ect is
-                when chargemT =>                     
-                    if (send='1') then 
-                        sended  <= '0'; 
---                        load    <= '1';                   
-                        ect     <= serialize;                                               
-                    end if;
-                
-                when serialize => 
---                    load <= '0';
-                    if(N=14)then
-                        sended <= '1';
-                    end if;
-                                        
-                    if(CPT_ended='1')then 
-                        ect     <= chargemT;
---                        sended  <= '1';                        
-                    end if;
-
---                when attente =>
---                    if(send='0')then
---                        ect <= chargemT;
---                    end if;
-
-            end case;
-        end if;
-    end process;
-
-    process(sclk,raz)
-        begin
-        if (raz='0')then
-            vector_int <= (others=> '0');
-            N <= 16;
---        elsif(send='1')then
---            vector_int <= vectin & '0';
---            N <= 0;
-        elsif(sclk'event and sclk='1')then
-            send_reg <= send;
-            
-            
-            if(send_reg='1' and send='0')then
-                vector_int <= vectin & '0';
-            elsif(send='1')then
-                N <= 0;
-            elsif (CPT_ended='0') then
-                vector_int <= vector_int(15 downto 0) & '0'; 
-                N <= N+1;
-            end if; 
-        end if;
-    end process;
-
-CPT_ended   <=  '1' when N = 16 else '0';
-
-with ect select
-    Data <=  vector_int(16) when serialize,
-            '0' when others;
-     
-end ar_Serialize;
-            
diff --git a/lib/lpp/lpp_cna/lfr_cal_driver.vhd b/lib/lpp/lpp_cna/lfr_cal_driver.vhd
--- a/lib/lpp/lpp_cna/lfr_cal_driver.vhd
+++ b/lib/lpp/lpp_cna/lfr_cal_driver.vhd
@@ -19,128 +19,128 @@
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@member.fsf.org
 ------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
 LIBRARY techmap;
 USE techmap.gencomp.ALL;
 
-library lpp;
-use lpp.lpp_cna.all;
+LIBRARY lpp;
+USE lpp.lpp_cna.ALL;
 
 
-entity lfr_cal_driver is
-    generic(
-        tech   :  integer := 0;
-        PRESZ  :  integer range 1 to 32:=4;
-        PREMAX :  integer := 16#FFFFFF#;
-        CPTSZ  :  integer range 1 to 32:=16;
-        datawidth     : integer := 18;
-        abits         : integer := 8
-     );
-    Port ( 
-        clk             : in  STD_LOGIC;
-        rstn            : in  STD_LOGIC;
-        pre             : in  STD_LOGIC_VECTOR(PRESZ-1 downto 0);
-        N               : in  STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
-        Reload          : in  std_logic;
-        DATA_IN         : in  STD_LOGIC_VECTOR(datawidth-1 downto 0);
-        WEN             : in  STD_LOGIC;
-        LOAD_ADDRESSN   : IN  STD_LOGIC;
-        ADDRESS_IN      : IN  STD_LOGIC_VECTOR(abits-1 downto 0);
-        ADDRESS_OUT     : OUT STD_LOGIC_VECTOR(abits-1 downto 0);
-        INTERLEAVED     : IN  STD_LOGIC;
-        DAC_CFG         : IN  STD_LOGIC_VECTOR(3 downto 0);
-        SYNC            : out STD_LOGIC;
-        DOUT            : out STD_LOGIC;
-        SCLK            : out STD_LOGIC;
-        SMPCLK          : out STD_lOGIC
-              );
-end lfr_cal_driver;
-
-architecture Behavioral of lfr_cal_driver is
-constant dacresolution   : integer := 12;
-signal  RAM_DATA_IN      :  STD_LOGIC_VECTOR(datawidth-1 downto 0);
-signal  RAM_WEN          :  STD_LOGIC;
-signal  RAM_WADDR        :  STD_LOGIC_VECTOR(abits-1 downto 0);
-signal  RAM_DATA_OUT     :  STD_LOGIC_VECTOR(datawidth-1 downto 0);
-signal  RAM_RADDR        :  STD_LOGIC_VECTOR(abits-1 downto 0);
-signal  RAM_REN          :  STD_LOGIC;
-signal  DAC_DATA         :  STD_LOGIC_VECTOR(dacresolution-1 downto 0);
-signal  SMP_CLK          :  STD_LOGIC;
-signal  DAC_INPUT        :  STD_LOGIC_VECTOR(15 downto 0);
-
-begin
-
-ADDRESS_OUT <= RAM_WADDR;
-DAC_INPUT   <= DAC_CFG &  DAC_DATA;
-SMPCLK      <= SMP_CLK;
+ENTITY lfr_cal_driver IS
+  GENERIC(
+    tech      : INTEGER               := 0;
+    PRESZ     : INTEGER RANGE 1 TO 32 := 4;
+    PREMAX    : INTEGER               := 16#FFFFFF#;
+    CPTSZ     : INTEGER RANGE 1 TO 32 := 16;
+    datawidth : INTEGER               := 18;
+    abits     : INTEGER               := 8
+    );
+  PORT (
+    clk           : IN  STD_LOGIC;
+    rstn          : IN  STD_LOGIC;
+    pre           : IN  STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
+    N             : IN  STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
+    Reload        : IN  STD_LOGIC;
+    DATA_IN       : IN  STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
+    WEN           : IN  STD_LOGIC;
+    LOAD_ADDRESSN : IN  STD_LOGIC;
+    ADDRESS_IN    : IN  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+    ADDRESS_OUT   : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+    INTERLEAVED   : IN  STD_LOGIC;
+    DAC_CFG       : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    SYNC          : OUT STD_LOGIC;
+    DOUT          : OUT STD_LOGIC;
+    SCLK          : OUT STD_LOGIC;
+    SMPCLK        : OUT STD_LOGIC
+    );
+END lfr_cal_driver;
 
-dac_drv: SPI_DAC_DRIVER
-    Generic map(
-        datawidth     => 16,
-        MSBFIRST      => 1
-    )
-    Port map(
-        clk        => clk,
-        rstn       => rstn,
-        DATA       =>  DAC_INPUT,
-        SMP_CLK    => SMP_CLK,
-        SYNC       => SYNC,
-        DOUT       => DOUT,
-        SCLK       => SCLK
-         );
+ARCHITECTURE Behavioral OF lfr_cal_driver IS
+  CONSTANT dacresolution : INTEGER := 12;
+  SIGNAL   RAM_DATA_IN   : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
+  SIGNAL   RAM_WEN       : STD_LOGIC;
+  SIGNAL   RAM_WADDR     : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL   RAM_DATA_OUT  : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
+  SIGNAL   RAM_RADDR     : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
+  SIGNAL   RAM_REN       : STD_LOGIC;
+  SIGNAL   DAC_DATA      : STD_LOGIC_VECTOR(dacresolution-1 DOWNTO 0);
+  SIGNAL   SMP_CLK       : STD_LOGIC;
+  SIGNAL   DAC_INPUT     : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+BEGIN
+
+  ADDRESS_OUT <= RAM_WADDR;
+  DAC_INPUT   <= DAC_CFG & DAC_DATA;
+  SMPCLK      <= SMP_CLK;
 
-freqGen: dynamic_freq_div 
-    generic map(
-        PRESZ  => PRESZ,
-        PREMAX => PREMAX,
-        CPTSZ     => CPTSZ
-     )
-    Port map( clk => clk,
-           rstn => rstn,
-           pre => pre,
-           N => N,
-           Reload => Reload,
-           clk_out => SMP_CLK
-           );
-           
-         
-ramWr: RAM_WRITER
-    Generic map(
-        datawidth     => datawidth,
-        abits         => abits
-    )
-    Port map( 
-        clk            => clk,
-        rstn           => rstn,
-        DATA_IN        => DATA_IN,
-        DATA_OUT       => RAM_DATA_IN,
-        WEN_IN         => WEN,
-        WEN_OUT        => RAM_WEN,
-        LOAD_ADDRESSN  => LOAD_ADDRESSN,
-        ADDRESS_IN     => ADDRESS_IN,
-        ADDRESS_OUT    => RAM_WADDR
-   );
-   
-ramRd: RAM_READER 
-    Generic map(
-        datawidth     => datawidth,
-        dacresolution => dacresolution,
-        abits         => abits
-    )
-    Port map( 
-        clk         => clk,
-        rstn        => rstn,
-        DATA_IN     => RAM_DATA_OUT,
-        ADDRESS     => RAM_RADDR,
-        REN         => RAM_REN,
-        DATA_OUT    => DAC_DATA,
-        SMP_CLK     => SMP_CLK,
-        INTERLEAVED => INTERLEAVED
+  dac_drv : SPI_DAC_DRIVER
+    GENERIC MAP(
+      datawidth => 16,
+      MSBFIRST  => 1
+      )
+    PORT MAP(
+      clk     => clk,
+      rstn    => rstn,
+      DATA    => DAC_INPUT,
+      SMP_CLK => SMP_CLK,
+      SYNC    => SYNC,
+      DOUT    => DOUT,
+      SCLK    => SCLK
+      );
+
+  freqGen : dynamic_freq_div
+    GENERIC MAP(
+      PRESZ  => PRESZ,
+      PREMAX => PREMAX,
+      CPTSZ  => CPTSZ
+      )
+    PORT MAP(clk      => clk,
+              rstn    => rstn,
+              pre     => pre,
+              N       => N,
+              Reload  => Reload,
+              clk_out => SMP_CLK
               );
 
-SRAM : syncram_2p
-      GENERIC MAP(tech, abits, datawidth)
-      PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
+
+  ramWr : RAM_WRITER
+    GENERIC MAP(
+      datawidth => datawidth,
+      abits     => abits
+      )
+    PORT MAP(
+      clk           => clk,
+      rstn          => rstn,
+      DATA_IN       => DATA_IN,
+      DATA_OUT      => RAM_DATA_IN,
+      WEN_IN        => WEN,
+      WEN_OUT       => RAM_WEN,
+      LOAD_ADDRESSN => LOAD_ADDRESSN,
+      ADDRESS_IN    => ADDRESS_IN,
+      ADDRESS_OUT   => RAM_WADDR
+      );
 
-end Behavioral;
+  ramRd : RAM_READER
+    GENERIC MAP(
+      datawidth     => datawidth,
+      dacresolution => dacresolution,
+      abits         => abits
+      )
+    PORT MAP(
+      clk         => clk,
+      rstn        => rstn,
+      DATA_IN     => RAM_DATA_OUT,
+      ADDRESS     => RAM_RADDR,
+      REN         => RAM_REN,
+      DATA_OUT    => DAC_DATA,
+      SMP_CLK     => SMP_CLK,
+      INTERLEAVED => INTERLEAVED
+      );
+
+  SRAM : syncram_2p
+    GENERIC MAP(tech, abits, datawidth)
+    PORT MAP(clk, RAM_REN, RAM_RADDR, RAM_DATA_OUT, clk, RAM_WEN, RAM_WADDR, RAM_DATA_IN);
+
+END Behavioral;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/vhdlsyn.txt b/lib/lpp/lpp_cna/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_cna/vhdlsyn.txt
@@ -0,0 +1,7 @@
+lpp_cna.vhd
+APB_LFR_CAL.vhd
+RAM_READER.vhd
+RAM_WRITER.vhd
+SPI_DAC_DRIVER.vhd
+dynamic_freq_div.vhd
+lfr_cal_driver.vhd