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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.iir_filter.all;
31 use lpp.general_purpose.all;
32 use lpp.lpp_amba.all;
33 use lpp.apb_devices_list.all;
34
35 entity APB_IIR_CEL is
36 generic (
37 tech : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
42 abits : integer := 8;
43 Sample_SZ : integer := 16;
44 ChanelsCount : integer := 1;
45 Coef_SZ : integer := 9;
46 CoefCntPerCel: integer := 6;
47 Cels_count : integer := 5;
48 virgPos : integer := 3;
49 Mem_use : integer := use_RAM
50 );
51 port (
52 rst : in std_logic;
53 clk : in std_logic;
54 apbi : in apb_slv_in_type;
55 apbo : out apb_slv_out_type;
56 sample_clk : in std_logic;
57 sample_clk_out : out std_logic;
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
60 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
61 );
62 end;
63
64
65 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
66
67 constant REVISION : integer := 1;
68
69 constant pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
71 1 => apb_iobar(paddr, pmask));
72
73
74
75 type FILTERreg is record
76 regin : in_IIR_CEL_reg;
77 regout : out_IIR_CEL_reg;
78 end record;
79
80 signal Rdata : std_logic_vector(31 downto 0);
81 signal r : FILTERreg;
82 signal filter_reset : std_logic:='0';
83 signal smp_cnt : integer :=0;
84 signal sample_clk_out_R : std_logic;
85 signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
86
87 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
88 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
89
90 type CoefsRegT is record
91 numCoefs : CoefTblT;
92 denCoefs : CoefTblT;
93 end record;
94
95 signal CoefsReg : CoefsRegT;
96 signal CoefsReg_d : CoefsRegT;
97
98
99 begin
100
101 filter_reset <= rst and r.regin.config(0);
102 sample_clk_out <= sample_clk_out_R;
103 --
104 filter : IIR_CEL_FILTER
105 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
106 port map(
107 reset => filter_reset,
108 clk => clk,
109 sample_clk => sample_clk,
110 regs_in => r.regin,
111 regs_out => r.regout,
112 sample_in => sample_in,
113 sample_out => sample_out,
114 coefs => RawCoefs
115 );
116
117 process(rst,sample_clk)
118 begin
119 if rst = '0' then
120 smp_cnt <= 0;
121 sample_clk_out_R <= '0';
122 elsif sample_clk'event and sample_clk = '1' then
123 if smp_cnt = 1 then
124 smp_cnt <= 0;
125 sample_clk_out_R <= not sample_clk_out_R;
126 else
127 smp_cnt <= smp_cnt +1;
128 end if;
129 end if;
130 end process;
131
132
133 coefsConnectL0: for z in 0 to Cels_count-1 generate
134 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
135 RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
136 RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
137 end generate;
138 end generate;
139
140
141 process(rst,clk)
142 begin
143 if rst = '0' then
144 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
145 coefsRstL0: for z in 0 to Cels_count-1 loop
146 coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
147 CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
148 CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
149 end loop;
150 end loop;
151 elsif clk'event and clk = '1' then
152 CoefsReg_d <= CoefsReg;
153
154 --APB Write OP
155 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
156 if apbi.paddr(7 downto 2) = "000000" then
157 r.regin.config(0) <= apbi.pwdata(0);
158 elsif apbi.paddr(7 downto 2) = "000001" then
159 r.regin.virgPos <= apbi.pwdata(4 downto 0);
160 else
161 for i in 0 to Cels_count-1 loop
162 for j in 0 to (CoefCntPerCel/2) - 1 loop
163 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
164 CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
165 CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
166 end if;
167 end loop;
168 end loop;
169 end if;
170 end if;
171
172 --APB READ OP
173 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
174 if apbi.paddr(7 downto 2) = "000000" then
175 Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
176 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
177 Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
178 Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
179 elsif apbi.paddr(7 downto 2) = "000001" then
180 Rdata(4 downto 0) <= r.regin.virgPos;
181 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
182 Rdata(7 downto 5) <= (others => '0');
183 Rdata(31 downto 16) <= (others => '0');
184 else
185 for i in 0 to Cels_count-1 loop
186 for j in 0 to (CoefCntPerCel/2) - 1 loop
187 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
188 Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
189 Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
190 end if;
191 end loop;
192 end loop;
193 end if;
194 end if;
195 end if;
196 apbo.pconfig <= pconfig;
197 end process;
198
199 apbo.prdata <= Rdata when apbi.penable = '1' ;
200
201 -- pragma translate_off
202 bootmsg : report_version
203 generic map ("apb IIR filter" & tost(pindex) &
204 ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
205 ", irq " & tost(pirq));
206 -- pragma translate_on
207
208
209
210
211 end ar_APB_IIR_CEL;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
30 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
31 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
32
33 entity FILTER is
34 generic(Smpl_SZ : integer := 16;
35 ChanelsCNT : integer := 3
36 );
37 port(
38
39 reset : in std_logic;
40 clk : in std_logic;
41 sample_clk : in std_logic;
42 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
43 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
44 );
45 end entity;
46
47
48
49
50
51 architecture ar_FILTER of FILTER is
52
53
54
55
56 signal ALU_ctrl : std_logic_vector(3 downto 0);
57 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
58 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
59 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
60
61 begin
62
63 --==============================================================
64 --=========================A L U================================
65 --==============================================================
66 ALU1 : entity ALU
67 generic map(
68 Arith_en => 1,
69 Logic_en => 0,
70 Input_SZ_1 => Smpl_SZ,
71 Input_SZ_2 => Coef_SZ
72
73 )
74 port map(
75 clk => clk,
76 reset => reset,
77 ctrl => ALU_ctrl,
78 OP1 => Sample,
79 OP2 => Coef,
80 RES => ALU_OUT
81 );
82 --==============================================================
83
84 --==============================================================
85 --===============F I L T E R C O N T R O L E R================
86 --==============================================================
87 filterctrlr1 : FilterCTRLR
88 port map(
89 reset => reset,
90 clk => clk,
91 sample_clk => sample_clk,
92 ALU_Ctrl => ALU_ctrl,
93 sample_in => sample_Tbl,
94 coef => Coef,
95 sample => Sample
96 );
97 --==============================================================
98
99 chanelCut : for i in 0 to ChanelsCNT-1 generate
100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
101 end generate;
102
103
104
105
106 end ar_FILTER;
107
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29
30 --TODO am�liorer la flexibilit� de la config de la RAM.
31
32 entity FILTER_RAM_CTRLR is
33 port(
34 reset : in std_logic;
35 clk : in std_logic;
36 run : in std_logic;
37 GO_0 : in std_logic;
38 B_A : in std_logic;
39 writeForce : in std_logic;
40 next_blk : in std_logic;
41 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
42 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
43 );
44 end FILTER_RAM_CTRLR;
45
46
47 architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
48
49 signal WD : std_logic_vector(35 downto 0);
50 signal WD_D : std_logic_vector(35 downto 0);
51 signal RD : std_logic_vector(35 downto 0);
52 signal WEN, REN : std_logic;
53 signal WADDR_back : std_logic_vector(7 downto 0);
54 signal WADDR_back_D: std_logic_vector(7 downto 0);
55 signal RADDR : std_logic_vector(7 downto 0);
56 signal WADDR : std_logic_vector(7 downto 0);
57 signal WADDR_D : std_logic_vector(7 downto 0);
58 signal run_D : std_logic;
59 signal run_D_inv : std_logic;
60 signal run_inv : std_logic;
61 signal next_blk_D : std_logic;
62 signal MUX2_inst1_sel : std_logic;
63
64
65 begin
66
67 sample_out <= RD(Smpl_SZ-1 downto 0);
68
69 MUX2_inst1_sel <= run_D and not next_blk;
70 run_D_inv <= not run_D;
71 run_inv <= not run;
72 WEN <= run_D_inv and not writeForce;
73 REN <= run_inv ;--and not next_blk;
74
75
76 --==============================================================
77 --=========================R A M================================
78 --==============================================================
79 memRAM : if Mem_use = use_RAM generate
80 RAMblk :RAM
81 port map(
82 WD => WD_D,
83 RD => RD,
84 WEN => WEN,
85 REN => REN,
86 WADDR => WADDR,
87 RADDR => RADDR,
88 RWCLK => clk,
89 RESET => reset
90 ) ;
91 end generate;
92
93 memCEL : if Mem_use = use_CEL generate
94 RAMblk :RAM_CEL
95 port map(
96 WD => WD_D,
97 RD => RD,
98 WEN => WEN,
99 REN => REN,
100 WADDR => WADDR,
101 RADDR => RADDR,
102 RWCLK => clk,
103 RESET => reset
104 ) ;
105 end generate;
106 --==============================================================
107 --==============================================================
108
109
110 ADDRcntr_inst : ADDRcntr
111 port map(
112 clk => clk,
113 reset => reset,
114 count => run,
115 clr => GO_0,
116 Q => RADDR
117 );
118
119
120
121 MUX2_inst1 :MUX2
122 generic map(Input_SZ => Smpl_SZ)
123 port map(
124 sel => MUX2_inst1_sel,
125 IN1 => sample_in,
126 IN2 => RD(Smpl_SZ-1 downto 0),
127 RES => WD(Smpl_SZ-1 downto 0)
128 );
129
130
131 MUX2_inst2 :MUX2
132 generic map(Input_SZ => 8)
133 port map(
134 sel => next_blk_D,
135 IN1 => WADDR_D,
136 IN2 => WADDR_back_D,
137 RES => WADDR
138 );
139
140
141 next_blkRreg :REG
142 generic map(size => 1)
143 port map(
144 reset => reset,
145 clk => clk,
146 D(0) => next_blk,
147 Q(0) => next_blk_D
148 );
149
150 WADDR_backreg :REG
151 generic map(size => 8)
152 port map(
153 reset => reset,
154 clk => B_A,
155 D => RADDR,
156 Q => WADDR_back
157 );
158
159 WADDR_backreg2 :REG
160 generic map(size => 8)
161 port map(
162 reset => reset,
163 clk => B_A,
164 D => WADDR_back,
165 Q => WADDR_back_D
166 );
167
168 WDRreg :REG
169 generic map(size => Smpl_SZ)
170 port map(
171 reset => reset,
172 clk => clk,
173 D => WD(Smpl_SZ-1 downto 0),
174 Q => WD_D(Smpl_SZ-1 downto 0)
175 );
176
177 RunRreg :REG
178 generic map(size => 1)
179 port map(
180 reset => reset,
181 clk => clk,
182 D(0) => run,
183 Q(0) => run_D
184 );
185
186
187
188 ADDRreg :REG
189 generic map(size => 8)
190 port map(
191 reset => reset,
192 clk => clk,
193 D => RADDR,
194 Q => WADDR_D
195 );
196
197
198
199 end ar_FILTER_RAM_CTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26
27 package FILTERcfg is
28
29
30
31
32 --===========================================================|
33 --========F I L T E R C O N F I G V A L U E S=============|
34 --===========================================================|
35 --____________________________
36 --Bus Width and chanels number|
37 --____________________________|
38 constant ChanelsCNT : integer := 6;
39 constant Smpl_SZ : integer := 16;
40 constant Coef_SZ : integer := 9;
41 constant Scalefac_SZ: integer := 3;
42 constant Cels_count : integer := 5;
43
44 constant Mem_use : integer := 1;
45
46
47
48 --============================================================
49 -- create each initial values for each coefs ============
50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 --============================================================
52 --constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
53 --constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
54 --constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
55 --constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
56 --constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
57 --constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
58 --constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
59 --
60 --constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
61 --constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
62 --constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
63 --constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
64 --constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
65 --
66 --
67 --constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
68 --constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
69 --constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
70 --
71 --constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
72 --constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
73 --constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
74 --
75 --constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
76 --constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
77 --constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
78 --
79 --constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
80 --constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
81 --constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
82 --
83 --constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
84 --constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
85 --constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
86 --
87 --constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
88 --constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
89 --constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
90 --
91 --constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
92 --constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
93 --constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
94 --
95 --
96 --constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
97 --constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
98 --constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
99 --
100 --constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
101 --constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
102 --constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
103 --
104 --constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
105 --constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
106 --constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
107 --
108 --constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
109 --constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
110 --constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
111 --
112 --constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
113 --constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
114 --constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
115 --
116 --constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
117 --constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
118 --constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
119 --constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
120 --constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
121 --constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
122 --
123 --
124 --constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
125 --constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
126 --constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
127 --constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
128 --constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
129 --constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
130 --constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
131 --
132 --constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
133 --constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
134 --constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
135 --constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
136 --constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
137 --constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
138 --constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
139 --
140 --
141 --
142 --constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
143 --constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
144 --constant virgPos : integer := 7;
145 --
146 --
147 --
148 --
149 --
150 --
151 --
152 --signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
153 --signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
154 --
155 --
156 --signal sample_Tbl : samplT;
157
158
159 end;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29
30 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
31
32 entity FilterCTRLR is
33 port(
34 reset : in std_logic;
35 clk : in std_logic;
36 sample_clk : in std_logic;
37 ALU_Ctrl : out std_logic_vector(3 downto 0);
38 sample_in : in samplT;
39 coef : out std_logic_vector(Coef_SZ-1 downto 0);
40 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
41 );
42 end FilterCTRLR;
43
44
45 architecture ar_FilterCTRLR of FilterCTRLR is
46
47 constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
48 constant DENCoefsCnt : integer:= DenominatorCoefs'high;
49
50 signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
51 signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
52
53 signal chanelCnt : integer range 0 to 15:=0;
54
55 signal WD : std_logic_vector(35 downto 0);
56 signal WD_D : std_logic_vector(35 downto 0);
57 signal RD : std_logic_vector(35 downto 0);
58 signal WEN, REN,WEN_D : std_logic;
59 signal WADDR_back : std_logic_vector(7 downto 0);
60 signal ADDR : std_logic_vector(7 downto 0);
61 signal ADDR_D : std_logic_vector(7 downto 0);
62 signal clk_inv : std_logic;
63
64 type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
65 signal in_Rotate_Buff : Rotate_BuffT;
66 signal out_Rotate_Buff : Rotate_BuffT;
67
68 signal sample_clk_old : std_logic;
69
70 type stateT is (waiting,computeNUM,computeDEN,NextChanel);
71 signal state : stateT;
72
73 begin
74 clk_inv <= not clk;
75
76 process(clk,reset)
77 begin
78 if reset = '0' then
79 state <= waiting;
80 WEN <= '1';
81 REN <= '1';
82 ADDR <= (others => '0');
83 WD <= (others => '0');
84 NcoefCnt <= 0;
85 DcoefCnt <= 0;
86 chanelCnt <= 0;
87 ALU_Ctrl <= clr_mac;
88 sample_clk_old <= '0';
89 coef <= (others => '0');
90 sample <= (others => '0');
91 rst:for i in 0 to ChanelsCNT-1 loop
92 in_Rotate_Buff(i) <= (others => '0');
93 end loop;
94 elsif clk'event and clk = '1' then
95
96 sample_clk_old <= sample_clk;
97
98 --=================================================================
99 --===============DATA processing===================================
100 --=================================================================
101 case state is
102 when waiting=>
103
104 if sample_clk_old = '0' and sample_clk = '1' then
105 ALU_Ctrl <= MAC_op;
106 sample <= in_Rotate_Buff(0);
107 coef <= std_logic_vector(NumeratorCoefs(0));
108 else
109 ALU_Ctrl <= clr_mac;
110 loadinput: for i in 0 to ChanelsCNT-1 loop
111 in_Rotate_Buff(i) <= sample_in(i);
112 end loop;
113 end if;
114
115 when computeNUM=>
116 ALU_Ctrl <= MAC_op;
117 sample <= RD(Smpl_SZ-1 downto 0);
118 coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
119
120 when computeDEN=>
121 ALU_Ctrl <= MAC_op;
122 sample <= RD(Smpl_SZ-1 downto 0);
123 coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
124
125 when NextChanel=>
126 rotate : for i in 0 to ChanelsCNT-2 loop
127 in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
128 end loop;
129 rotatetoo: if ChanelsCNT > 1 then
130 sample <= in_Rotate_Buff(1);
131 coef <= std_logic_vector(NumeratorCoefs(0));
132 end if;
133 end case;
134
135 --=================================================================
136 --===============RAM read write====================================
137 --=================================================================
138 case state is
139 when waiting=>
140 if sample_clk_old = '0' and sample_clk = '1' then
141 REN <= '0';
142 else
143 REN <= '1';
144 end if;
145 ADDR <= (others => '0');
146 WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
147 WEN <= '1';
148
149 when computeNUM=>
150 WD <= RD;
151 REN <= '0';
152 WEN <= '0';
153 ADDR <= std_logic_vector(unsigned(ADDR)+1);
154 when computeDEN=>
155 WD <= RD;
156 REN <= '0';
157 WEN <= '0';
158 ADDR <= std_logic_vector(unsigned(ADDR)+1);
159 when NextChanel=>
160 REN <= '1';
161 WEN <= '1';
162 end case;
163 --=================================================================
164
165
166 --=================================================================
167 --===============FSM Management====================================
168 --=================================================================
169 case state is
170 when waiting=>
171 if sample_clk_old = '0' and sample_clk = '1' then
172 state <= computeNUM;
173 end if;
174 DcoefCnt <= 0;
175 NcoefCnt <= 1;
176 chanelCnt<= 0;
177 when computeNUM=>
178 if NcoefCnt = NumCoefsCnt then
179 state <= computeDEN;
180 NcoefCnt <= 1;
181 else
182 NcoefCnt <= NcoefCnt+1;
183 end if;
184 when computeDEN=>
185 if DcoefCnt = DENCoefsCnt then
186 state <= NextChanel;
187 DcoefCnt <= 0;
188 else
189 DcoefCnt <= DcoefCnt+1;
190 end if;
191 when NextChanel=>
192 if chanelCnt = (ChanelsCNT-1) then
193 state <= waiting;
194 else
195 chanelCnt<= chanelCnt+1;
196 state <= computeNUM;
197 end if;
198 end case;
199 --=================================================================
200
201 end if;
202 end process;
203
204 ADDRreg : REG
205 generic map(size => 8)
206 port map(
207 reset => reset,
208 clk => clk,
209 D => ADDR,
210 Q => ADDR_D
211 );
212
213 WDreg :REG
214 generic map(size => 36)
215 port map(
216 reset => reset,
217 clk => clk,
218 D => WD,
219 Q => WD_D
220 );
221
222 WRreg :REG
223 generic map(size => 1)
224 port map(
225 reset => reset,
226 clk => clk,
227 D(0) => WEN,
228 Q(0) => WEN_D
229 );
230 --==============================================================
231 --=========================R A M================================
232 --==============================================================
233 memRAM : if Mem_use = use_RAM generate
234 RAMblk :RAM
235 port map(
236 WD => WD_D,
237 RD => RD,
238 WEN => WEN_D,
239 REN => REN,
240 WADDR => ADDR_D,
241 RADDR => ADDR,
242 RWCLK => clk_inv,
243 RESET => reset
244 ) ;
245 end generate;
246
247 memCEL : if Mem_use = use_CEL generate
248 RAMblk :RAM
249 port map(
250 WD => WD_D,
251 RD => RD,
252 WEN => WEN_D,
253 REN => REN,
254 WADDR => ADDR_D,
255 RADDR => ADDR,
256 RWCLK => clk_inv,
257 RESET => reset
258 ) ;
259 end generate;
260
261 --==============================================================
262
263
264
265 end ar_FilterCTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 library IEEE;
24 use IEEE.numeric_std.all;
25 use IEEE.std_logic_1164.all;
26 library lpp;
27 use lpp.iir_filter.all;
28 use lpp.general_purpose.all;
29
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31
32 entity IIR_CEL_CTRLR is
33 generic(
34 tech : integer := 0;
35 Sample_SZ : integer := 16;
36 ChanelsCount : integer := 1;
37 Coef_SZ : integer := 9;
38 CoefCntPerCel: integer := 6;
39 Cels_count : integer := 5;
40 Mem_use : integer := use_RAM
41 );
42 port(
43 reset : in std_logic;
44 clk : in std_logic;
45 sample_clk : in std_logic;
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
48 virg_pos : in integer;
49 coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0)
50 );
51 end IIR_CEL_CTRLR;
52
53
54
55
56 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
57
58 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
59
60 signal smpl_clk_old : std_logic := '0';
61 signal WD_sel : std_logic := '0';
62 signal Read : std_logic := '0';
63 signal SVG_ADDR : std_logic := '0';
64 signal count : std_logic := '0';
65 signal Write : std_logic := '0';
66 signal WADDR_sel : std_logic := '0';
67 signal GO_0 : std_logic := '0';
68
69 signal RAM_sample_in : sampleVect;
70 signal RAM_sample_in_bk: sampleVect;
71 signal RAM_sample_out : sampleVect;
72 signal ALU_ctrl : std_logic_vector(3 downto 0);
73 signal ALU_sample_in : sampleVect;
74 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
75 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
76 signal curentCel : integer range 0 to Cels_count-1 := 0;
77 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
78
79
80 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
81
82 signal sample_in_BUFF : sampleBuffT;
83 signal sample_out_BUFF : sampleBuffT;
84
85 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
86 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
87
88 type CoefsRegT is record
89 numCoefs : CoefTblT;
90 denCoefs : CoefTblT;
91 end record;
92
93 signal CoefsReg : CoefsRegT;
94
95 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
96
97 signal IIR_CEL_STATE : fsmIIR_CEL_T;
98
99 begin
100
101
102 --coefsConnectL0: for z in 0 to Cels_count-1 generate
103 -- coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
104 -- coefsConnectL2: for x in 0 to Coef_SZ-1 generate
105 -- CoefsReg.numCoefs(z)(y)(x) <= coefs(x + (((2*y))*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
106 -- CoefsReg.denCoefs(z)(y)(x) <= coefs(x + (((2*y)+1)*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
107 -- end generate;
108 -- end generate;
109 --end generate;
110
111 coefsConnectL0: for z in 0 to Cels_count-1 generate
112 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
113 CoefsReg.numCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
114 CoefsReg.denCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
115 end generate;
116 end generate;
117
118
119
120
121 RAM_CTRLR2inst : RAM_CTRLR2
122 generic map(tech,Sample_SZ,Mem_use)
123 port map(
124 reset => reset,
125 clk => clk,
126 WD_sel => WD_sel,
127 Read => Read,
128 WADDR_sel => WADDR_sel,
129 count => count,
130 SVG_ADDR => SVG_ADDR,
131 Write => Write,
132 GO_0 => GO_0,
133 sample_in => RAM_sample_in,
134 sample_out => RAM_sample_out
135 );
136
137
138
139 ALU_inst :ALU
140 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
141 port map(
142 clk => clk,
143 reset => reset,
144 ctrl => ALU_ctrl,
145 OP1 => ALU_sample_in,
146 OP2 => ALU_coef_in,
147 RES => ALU_out
148 );
149
150
151
152
153
154
155 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
156 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
157 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
158 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
159 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
160 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
161 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
162
163 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
164
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166
167
168
169
170
171 process(clk,reset)
172 variable result : std_logic_vector(Sample_SZ-1 downto 0);
173
174 begin
175
176 if reset = '0' then
177
178 smpl_clk_old <= '0';
179 RAM_sample_in <= (others=> '0');
180 ALU_ctrl <= IDLE;
181 ALU_sample_in <= (others=> '0');
182 ALU_Coef_in <= (others=> '0');
183 RAM_sample_in_bk<= (others=> '0');
184 curentCel <= 0;
185 curentChan <= 0;
186 IIR_CEL_STATE <= waiting;
187 resetL0 : for i in 0 to ChanelsCount-1 loop
188 sample_in_BUFF(i) <= (others => '0');
189 sample_out_BUFF(i) <= (others => '0');
190 resetL1: for j in 0 to Sample_SZ-1 loop
191 sample_out(i,j) <= '0';
192 end loop;
193 end loop;
194
195 elsif clk'event and clk = '1' then
196
197 smpl_clk_old <= sample_clk;
198
199 case IIR_CEL_STATE is
200
201 when waiting =>
202 if sample_clk = '1' and smpl_clk_old = '0' then
203 IIR_CEL_STATE <= pipe1;
204 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
205 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
206
207 else
208 ALU_ctrl <= IDLE;
209 smplConnectL0: for i in 0 to ChanelsCount-1 loop
210 smplConnectL1: for j in 0 to Sample_SZ-1 loop
211 sample_in_BUFF(i)(j) <= sample_in(i,j);
212 sample_out(i,j) <= sample_out_BUFF(i)(j);
213 end loop;
214 end loop;
215 end if;
216 curentCel <= 0;
217 curentChan <= 0;
218
219 when pipe1 =>
220 IIR_CEL_STATE <= computeb1;
221 ALU_ctrl <= MAC_op;
222 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
223
224 when computeb1 =>
225
226 ALU_ctrl <= MAC_op;
227 ALU_sample_in <= RAM_sample_out;
228 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
229 IIR_CEL_STATE <= computeb2;
230 RAM_sample_in <= RAM_sample_in_bk;
231 when computeb2 =>
232 ALU_sample_in <= RAM_sample_out;
233 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
234 IIR_CEL_STATE <= computea1;
235
236
237 when computea1 =>
238 ALU_sample_in <= RAM_sample_out;
239 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
240 IIR_CEL_STATE <= computea2;
241
242
243 when computea2 =>
244 ALU_sample_in <= RAM_sample_out;
245 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
246 IIR_CEL_STATE <= next_cel;
247
248
249 when next_cel =>
250 ALU_ctrl <= clr_mac;
251 IIR_CEL_STATE <= pipe2;
252
253 when pipe2 =>
254 IIR_CEL_STATE <= pipe3;
255
256
257 when pipe3 =>
258
259 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
260
261 sample_out_BUFF(0) <= result;
262 RAM_sample_in_bk <= result;
263 RAM_sample_in <= result;
264 if curentCel = Cels_count-1 then
265 IIR_CEL_STATE <= next_chan;
266 curentCel <= 0;
267 else
268 curentCel <= curentCel + 1;
269 IIR_CEL_STATE <= pipe1;
270 ALU_sample_in <= result;
271 end if;
272 when next_chan =>
273
274 rotate : for i in 1 to ChanelsCount-1 loop
275 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
276 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
277 end loop;
278 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
279 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
280
281 if curentChan = (ChanelsCount-1) then
282 IIR_CEL_STATE <= waiting;
283 ALU_ctrl <= clr_mac;
284 elsif ChanelsCount>1 then
285 curentChan <= curentChan + 1;
286 IIR_CEL_STATE <= pipe1;
287 ALU_sample_in <= sample_in_BUFF(1);
288 RAM_sample_in <= sample_in_BUFF(1);
289 end if;
290 end case;
291
292 end if;
293 end process;
294
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298
299
300 end ar_IIR_CEL_CTRLR;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.general_purpose.all;
28
29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30
31 entity IIR_CEL_FILTER is
32 generic(
33 tech : integer := 0;
34 Sample_SZ : integer := 16;
35 ChanelsCount : integer := 1;
36 Coef_SZ : integer := 9;
37 CoefCntPerCel: integer := 6;
38 Cels_count : integer := 5;
39 Mem_use : integer := use_RAM);
40 port(
41 reset : in std_logic;
42 clk : in std_logic;
43 sample_clk : in std_logic;
44 regs_in : in in_IIR_CEL_reg;
45 regs_out : in out_IIR_CEL_reg;
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
48 coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0)
49
50 );
51 end IIR_CEL_FILTER;
52
53
54
55
56 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
57
58 signal virg_pos : integer;
59 begin
60
61 virg_pos <= to_integer(unsigned(regs_in.virgPos));
62
63 CTRLR : IIR_CEL_CTRLR
64 generic map (tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
65 port map(
66 reset => reset,
67 clk => clk,
68 sample_clk => sample_clk,
69 sample_in => sample_in,
70 sample_out => sample_out,
71 virg_pos => virg_pos,
72 coefs => coefs
73 );
74
75
76
77
78
79 end ar_IIR_CEL_FILTER;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM;
33
34
35 architecture DEF_ARCH of RAM is
36 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
37 signal RAMarray : RAMarrayT:=(others => X"000000000");
38 signal RD_int : std_logic_vector(35 downto 0);
39
40 begin
41
42 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
43
44
45 process(RWclk,reset)
46 begin
47 if reset = '0' then
48 RD <= (X"000000000");
49 rst:for i in 0 to 255 loop
50 RAMarray(i) <= (others => '0');
51 end loop;
52
53 elsif RWclk'event and RWclk = '1' then
54 if REN = '0' then
55 RD <= RD_int;
56 end if;
57
58 if WEN = '0' then
59 RAMarray(to_integer(unsigned(WADDR))) <= WD;
60 end if;
61
62 end if;
63 end process;
64 end DEF_ARCH;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM_CEL;
33
34
35
36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"000000000");
39 signal RD_int : std_logic_vector(35 downto 0);
40
41 begin
42
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44
45
46 process(RWclk,reset)
47 begin
48 if reset = '0' then
49 RD <= (X"000000000");
50 rst:for i in 0 to 255 loop
51 RAMarray(i) <= (others => '0');
52 end loop;
53
54 elsif RWclk'event and RWclk = '1' then
55 if REN = '0' then
56 RD <= RD_int;
57 end if;
58
59 if WEN = '0' then
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 end if;
62
63 end if;
64 end process;
65 end ar_RAM_CEL;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
29 library techmap;
30 use techmap.gencomp.all;
31
32 --TODO amliorer la flexibilit de la config de la RAM.
33
34 entity RAM_CTRLR2 is
35 generic(
36 tech : integer := 0;
37 Input_SZ_1 : integer := 16;
38 Mem_use : integer := use_RAM
39
40 );
41 port(
42 reset : in std_logic;
43 clk : in std_logic;
44 WD_sel : in std_logic;
45 Read : in std_logic;
46 WADDR_sel : in std_logic;
47 count : in std_logic;
48 SVG_ADDR : in std_logic;
49 Write : in std_logic;
50 GO_0 : in std_logic;
51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
53 );
54 end RAM_CTRLR2;
55
56
57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
58
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
62 signal WEN, REN : std_logic;
63 signal WADDR_back : std_logic_vector(7 downto 0);
64 signal WADDR_back_D: std_logic_vector(7 downto 0);
65 signal RADDR : std_logic_vector(7 downto 0);
66 signal WADDR : std_logic_vector(7 downto 0);
67 signal WADDR_D : std_logic_vector(7 downto 0);
68
69
70
71 begin
72
73 sample_out <= RD(Input_SZ_1-1 downto 0);
74
75
76 WEN <= not Write;
77 REN <= not read;
78
79
80 --==============================================================
81 --=========================R A M================================
82 --==============================================================
83 --memRAM : if Mem_use = use_RAM generate
84 --RAMblk :RAM
85 -- port map(
86 -- WD => WD_D,
87 -- RD => RD,
88 -- WEN => WEN,
89 -- REN => REN,
90 -- WADDR => WADDR,
91 -- RADDR => RADDR,
92 -- RWCLK => clk,
93 -- RESET => reset
94 -- ) ;
95 --end generate;
96
97 --memCEL : if Mem_use = use_CEL generate
98 --RAMblk :RAM_CEL
99 -- port map(
100 -- WD => WD_D,
101 -- RD => RD,
102 -- WEN => WEN,
103 -- REN => REN,
104 -- WADDR => WADDR,
105 -- RADDR => RADDR,
106 -- RWCLK => clk,
107 -- RESET => reset
108 -- ) ;
109 --end generate;
110
111 SRAM : syncram_2p
112 generic map(tech,8,Input_SZ_1)
113 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
114 --==============================================================
115 --==============================================================
116
117
118 ADDRcntr_inst : ADDRcntr
119 port map(
120 clk => clk,
121 reset => reset,
122 count => count,
123 clr => GO_0,
124 Q => RADDR
125 );
126
127
128
129 MUX2_inst1 :MUX2
130 generic map(Input_SZ => Input_SZ_1)
131 port map(
132 sel => WD_sel,
133 IN1 => sample_in,
134 IN2 => RD(Input_SZ_1-1 downto 0),
135 RES => WD(Input_SZ_1-1 downto 0)
136 );
137
138
139 MUX2_inst2 :MUX2
140 generic map(Input_SZ => 8)
141 port map(
142 sel => WADDR_sel,
143 IN1 => WADDR_D,
144 IN2 => WADDR_back_D,
145 RES => WADDR
146 );
147
148
149
150
151 WADDR_backreg :REG
152 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
153 port map(
154 reset => reset,
155 clk => SVG_ADDR,
156 D => RADDR,
157 Q => WADDR_back
158 );
159
160 WADDR_backreg2 :REG
161 generic map(size => 8)
162 port map(
163 reset => reset,
164 clk => SVG_ADDR,
165 D => WADDR_back,
166 Q => WADDR_back_D
167 );
168
169 WDRreg :REG
170 generic map(size => Input_SZ_1)
171 port map(
172 reset => reset,
173 clk => clk,
174 D => WD(Input_SZ_1-1 downto 0),
175 Q => WD_D(Input_SZ_1-1 downto 0)
176 );
177
178
179
180
181 ADDRreg :REG
182 generic map(size => 8)
183 port map(
184 reset => reset,
185 clk => clk,
186 D => RADDR,
187 Q => WADDR_D
188 );
189
190
191
192 end ar_RAM_CTRLR2;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26
27
28 entity TestbenshMAC is
29 end TestbenshMAC;
30
31
32
33
34 architecture ar_TestbenshMAC of TestbenshMAC is
35
36
37
38 constant OP1sz : integer := 16;
39 constant OP2sz : integer := 12;
40 --IDLE =00 MAC =01 MULT =10 ADD =11
41 constant IDLE : std_logic_vector(1 downto 0) := "00";
42 constant MAC : std_logic_vector(1 downto 0) := "01";
43 constant MULT : std_logic_vector(1 downto 0) := "10";
44 constant ADD : std_logic_vector(1 downto 0) := "11";
45
46 signal clk : std_logic:='0';
47 signal reset : std_logic:='0';
48 signal clrMAC : std_logic:='0';
49 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
50 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
51 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
52 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
53
54
55
56
57 begin
58
59
60 MAC1 : entity LPP_IIR_FILTER.MAC
61 generic map(
62 Input_SZ_A => OP1sz,
63 Input_SZ_B => OP2sz
64
65 )
66 port map(
67 clk => clk,
68 reset => reset,
69 clr_MAC => clrMAC,
70 MAC_MUL_ADD => MAC_MUL_ADD,
71 OP1 => Operand1,
72 OP2 => Operand2,
73 RES => Resultat
74 );
75
76 clk <= not clk after 25 ns;
77
78 process
79 begin
80 wait for 40 ns;
81 reset <= '1';
82 wait for 11 ns;
83 Operand1 <= X"0001";
84 Operand2 <= X"001";
85 MAC_MUL_ADD <= ADD;
86 wait for 50 ns;
87 Operand1 <= X"0001";
88 Operand2 <= X"100";
89 wait for 50 ns;
90 Operand1 <= X"0001";
91 Operand2 <= X"001";
92 MAC_MUL_ADD <= MULT;
93 wait for 50 ns;
94 Operand1 <= X"0002";
95 Operand2 <= X"002";
96 wait for 50 ns;
97 clrMAC <= '1';
98 wait for 50 ns;
99 clrMAC <= '0';
100 Operand1 <= X"0001";
101 Operand2 <= X"003";
102 MAC_MUL_ADD <= MAC;
103 wait;
104 end process;
105 end ar_TestbenshMAC;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29
30
31
32
33 package iir_filter is
34
35
36 --===========================================================|
37 --================A L U C O N T R O L======================|
38 --===========================================================|
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44
45 --____
46 --RAM |
47 --____|
48 constant use_RAM : integer := 1;
49 constant use_CEL : integer := 0;
50
51
52 --===========================================================|
53 --=============C O E F S ====================================|
54 --===========================================================|
55 -- create a specific type of data for coefs to avoid errors |
56 --===========================================================|
57
58 type scaleValT is array(natural range <>) of integer;
59
60 type samplT is array(natural range <>,natural range <>) of std_logic;
61
62 type in_IIR_CEL_reg is record
63 config : std_logic_vector(31 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
65 end record;
66
67 type out_IIR_CEL_reg is record
68 config : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
70 end record;
71
72
73
74 component APB_IIR_CEL is
75 generic (
76 tech : integer := 0;
77 pindex : integer := 0;
78 paddr : integer := 0;
79 pmask : integer := 16#fff#;
80 pirq : integer := 0;
81 abits : integer := 8;
82 Sample_SZ : integer := 16;
83 ChanelsCount : integer := 1;
84 Coef_SZ : integer := 9;
85 CoefCntPerCel: integer := 6;
86 Cels_count : integer := 5;
87 virgPos : integer := 3;
88 Mem_use : integer := use_RAM
89 );
90 port (
91 rst : in std_logic;
92 clk : in std_logic;
93 apbi : in apb_slv_in_type;
94 apbo : out apb_slv_out_type;
95 sample_clk : in std_logic;
96 sample_clk_out : out std_logic;
97 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
98 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
99 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
100 );
101 end component;
102
103
104 --component FILTER is
105 --generic(Smpl_SZ : integer := 16;
106 -- ChanelsCNT : integer := 3
107 --);
108 --port(
109 --
110 -- reset : in std_logic;
111 -- clk : in std_logic;
112 -- sample_clk : in std_logic;
113 -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
114 -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
115 --);
116 --end component;
117
118
119
120 --component FilterCTRLR is
121 --port(
122 -- reset : in std_logic;
123 -- clk : in std_logic;
124 -- sample_clk : in std_logic;
125 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
126 -- sample_in : in samplT;
127 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
128 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
129 --);
130 --end component;
131
132
133 --component FILTER_RAM_CTRLR is
134 --port(
135 -- reset : in std_logic;
136 -- clk : in std_logic;
137 -- run : in std_logic;
138 -- GO_0 : in std_logic;
139 -- B_A : in std_logic;
140 -- writeForce : in std_logic;
141 -- next_blk : in std_logic;
142 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
143 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
144 --);
145 --end component;
146
147
148 component IIR_CEL_CTRLR is
149 generic(
150 tech : integer := 0;
151 Sample_SZ : integer := 16;
152 ChanelsCount : integer := 1;
153 Coef_SZ : integer := 9;
154 CoefCntPerCel: integer := 3;
155 Cels_count : integer := 5;
156 Mem_use : integer := use_RAM
157 );
158 port(
159 reset : in std_logic;
160 clk : in std_logic;
161 sample_clk : in std_logic;
162 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
163 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
164 virg_pos : in integer;
165 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
166 );
167 end component;
168
169
170 component RAM is
171 port( WD : in std_logic_vector(35 downto 0); RD : out
172 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
173 WADDR : in std_logic_vector(7 downto 0); RADDR : in
174 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
175 ) ;
176 end component;
177
178
179 component RAM_CEL is
180 port( WD : in std_logic_vector(35 downto 0); RD : out
181 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
182 WADDR : in std_logic_vector(7 downto 0); RADDR : in
183 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
184 ) ;
185 end component;
186
187 component IIR_CEL_FILTER is
188 generic(
189 tech : integer := 0;
190 Sample_SZ : integer := 16;
191 ChanelsCount : integer := 1;
192 Coef_SZ : integer := 9;
193 CoefCntPerCel: integer := 3;
194 Cels_count : integer := 5;
195 Mem_use : integer := use_RAM);
196 port(
197 reset : in std_logic;
198 clk : in std_logic;
199 sample_clk : in std_logic;
200 regs_in : in in_IIR_CEL_reg;
201 regs_out : in out_IIR_CEL_reg;
202 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
203 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
204 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
205
206 );
207 end component;
208
209
210 component RAM_CTRLR2 is
211 generic(
212 tech : integer := 0;
213 Input_SZ_1 : integer := 16;
214 Mem_use : integer := use_RAM
215 );
216 port(
217 reset : in std_logic;
218 clk : in std_logic;
219 WD_sel : in std_logic;
220 Read : in std_logic;
221 WADDR_sel : in std_logic;
222 count : in std_logic;
223 SVG_ADDR : in std_logic;
224 Write : in std_logic;
225 GO_0 : in std_logic;
226 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
227 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
228 );
229 end component;
230
231
232 end;
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@@ -0,0 +1,155
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity Driver_FFT is
27 generic(
28 Data_sz : integer range 1 to 32 := 16
29 );
30 port(
31 clk : in std_logic;
32 rstn : in std_logic;
33 Load : in std_logic;
34 Empty : in std_logic_vector(4 downto 0);
35 Full : in std_logic_vector(4 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
37 Valid : out std_logic;
38 Read : out std_logic_vector(4 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
41 );
42 end entity;
43
44
45 architecture ar_Driver of Driver_FFT is
46
47 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
49
50 signal FifoCpt : integer;
51 --signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
52
53 signal sEmpty : std_logic;
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56
57 begin
58
59 process(clk,rstn)
60 begin
61 if(rstn='0')then
62 ect <= eX;
63 Read <= (others => '1');
64 Valid <= '0';
65 FifoCpt <= 1;
66
67 elsif(clk'event and clk='1')then
68
69 case ect is
70
71 when eX =>
72 if(sFull='1')then
73 ect <= e0;
74 end if;
75
76 when e0 =>
77 Valid <= '0';
78 if(Load='1' and sEmpty='0')then
79 Read(FifoCpt-1) <= '0';
80 ect <= e2;
81 -- ect <= e1;
82 elsif(sEmpty='1')then
83 if(FifoCpt=6)then
84 FifoCpt <= 1;
85 else
86 FifoCpt <= FifoCpt+1;
87 end if;
88 ect <= eX;
89 end if;
90
91 when e1 =>
92 null;
93 -- DataTmp <= sData;
94 -- ect <= e2;
95
96 when e2 =>
97 Read(FifoCpt-1) <= '1';
98 Data_re <= sData;
99 Data_im <= (others => '0');
100 -- Data_re <= DataTmp;
101 -- Data_im <= sData;
102 Valid <= '1';
103 ect <= e0;
104
105
106 end case;
107 end if;
108 end process;
109
110 with FifoCpt select
111 sFull <= Full(0) when 1,
112 Full(1) when 2,
113 Full(2) when 3,
114 Full(3) when 4,
115 Full(4) when 5,
116 '1' when others;
117
118 with FifoCpt select
119 sEmpty <= Empty(0) when 1,
120 Empty(1) when 2,
121 Empty(2) when 3,
122 Empty(3) when 4,
123 Empty(4) when 5,
124 '1' when others;
125
126 with FifoCpt select
127 sData <= DATA(Data_sz-1 downto 0) when 1,
128 DATA((2*Data_sz)-1 downto Data_sz) when 2,
129 DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
130 DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
131 DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
132 (others => '0') when others;
133
134 end architecture;
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
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@@ -0,0 +1,129
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity Linker_FFT is
27 generic(
28 Data_sz : integer range 1 to 32 := 8
29 );
30 port(
31 clk : in std_logic;
32 rstn : in std_logic;
33 Ready : in std_logic;
34 Valid : in std_logic;
35 Full : in std_logic_vector(4 downto 0);
36 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Read : out std_logic;
39 Write : out std_logic_vector(4 downto 0);
40 ReUse : out std_logic_vector(4 downto 0);
41 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 );
43 end entity;
44
45
46 architecture ar_Linker of Linker_FFT is
47
48 type etat is (eX,e0,e1,e2,e3);
49 signal ect : etat;
50
51 signal FifoCpt : integer;
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56 signal sReady : std_logic;
57
58 begin
59
60 process(clk,rstn)
61 begin
62 if(rstn='0')then
63 ect <= e0;
64 Read <= '0';
65 Write <= (others => '1');
66 Reuse <= (others => '0');
67 FifoCpt <= 1;
68 sDATA <= (others => '0');
69
70 elsif(clk'event and clk='1')then
71 sReady <= Ready;
72
73 case ect is
74
75 when e0 =>
76 Write(FifoCpt-1) <= '1';
77 if(sReady='0' and Ready='1' and sfull='0')then
78 Read <= '1';
79 ect <= e1;
80 end if;
81
82 when e1 =>
83 Read <= '0';
84 if(Valid='1' and sfull='0')then
85 DataTmp <= Data_im;
86 sDATA <= Data_re;
87 Write(FifoCpt-1) <= '0';
88 ect <= e2;
89 elsif(sfull='1')then
90 ReUse(FifoCpt-1) <= '1';
91 ect <= eX;
92 end if;
93
94 when e2 =>
95 sDATA <= DataTmp;
96 ect <= e3;
97
98 when e3 =>
99 Write(FifoCpt-1) <= '1';
100 if(Ready='1' and sfull='0')then
101 Read <= '1';
102 ect <= e1;
103 end if;
104
105 when eX =>
106 if(FifoCpt=5)then
107 FifoCpt <= 1;
108 else
109 FifoCpt <= FifoCpt+1;
110 end if;
111 ect <= e0;
112
113 end case;
114 end if;
115 end process;
116
117 DATA <= sData & sData & sData & sData & sData;
118
119 with FifoCpt select
120 sFull <= Full(0) when 1,
121 Full(1) when 2,
122 Full(2) when 3,
123 Full(3) when 4,
124 Full(4) when 5,
125 '1' when others;
126
127
128 end architecture;
129
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@@ -0,0 +1,83
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity WriteGen_ADC is
27 port(
28 clk : in std_logic;
29 rstn : in std_logic;
30 SmplCLK : in std_logic;
31 DataReady : in std_logic;
32 Full : in std_logic_vector(4 downto 0);
33 ReUse : out std_logic_vector(4 downto 0);
34 Write : out std_logic_vector(4 downto 0)
35 );
36 end entity;
37
38
39 architecture ar_WG of WriteGen_ADC is
40
41 type etat is (e0,e1,eX);
42 signal ect : etat;
43
44 signal ReUse_reg : std_logic_vector(4 downto 0);
45
46 begin
47
48 process(clk,rstn)
49 begin
50 if(rstn='0')then
51 ect <= e0;
52 ReUse_reg <= (others => '0');
53 write <= (others => '1');
54
55 elsif(clk'event and clk='1')then
56 ReUse_reg <= Full or ReUse_reg;
57
58 case ect is
59
60 when e0 =>
61 if(DataReady='0' and SmplCLK='1')then
62 ect <= e1;
63 end if;
64
65 when e1 =>
66 if(DataReady='1')then
67 Write <= Full;
68 ect <= eX;
69 end if;
70
71 when eX =>
72 write <= (others => '1');
73 ect <= e0;
74
75 end case;
76 end if;
77 end process;
78
79
80 ReUse <= ReUse_reg;
81
82 end architecture;
83
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@@ -0,0 +1,77
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 --library lpp;
26 --use lpp.lpp_memory.all;
27 --library techmap;
28 --use techmap.gencomp.all;
29
30 entity lppFIFOx5 is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Enable_ReUse : std_logic := '0'
35 );
36 port(
37 rst : in std_logic;
38 wclk : in std_logic;
39 rclk : in std_logic;
40 ReUse : in std_logic_vector(4 downto 0);
41 wen : in std_logic_vector(4 downto 0);
42 ren : in std_logic_vector(4 downto 0);
43 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
44 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
45 full : out std_logic_vector(4 downto 0);
46 empty : out std_logic_vector(4 downto 0)
47 );
48 end entity;
49
50
51 architecture ar_lppFIFOx5 of lppFIFOx5 is
52
53 begin
54
55 fifoB1 : entity work.lpp_fifo
56 generic map (tech,Enable_ReUse,Data_sz,8)
57 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
58
59 fifoB2 : entity work.lpp_fifo
60 generic map (tech,Enable_ReUse,Data_sz,8)
61 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
62
63 fifoB3 : entity work.lpp_fifo
64 generic map (tech,Enable_ReUse,Data_sz,8)
65 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
66
67 fifoE1 : entity work.lpp_fifo
68 generic map (tech,Enable_ReUse,Data_sz,8)
69 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
70
71 fifoE2 : entity work.lpp_fifo
72 generic map (tech,Enable_ReUse,Data_sz,8)
73 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
74
75
76 end architecture;
77
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@@ -87,7 +87,7 component Flag_Extremum is
87 end component;
87 end component;
88
88
89
89
90 component Linker_FFT_FIFO is
90 component Linker_FFT is
91 generic(
91 generic(
92 Data_sz : integer range 1 to 32 := 16
92 Data_sz : integer range 1 to 32 := 16
93 );
93 );
@@ -106,6 +106,25 port(
106 );
106 );
107 end component;
107 end component;
108
108
109
110 component Driver_FFT is
111 generic(
112 Data_sz : integer range 1 to 32 := 16
113 );
114 port(
115 clk : in std_logic;
116 rstn : in std_logic;
117 Load : in std_logic;
118 Empty : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 Valid : out std_logic;
122 Read : out std_logic_vector(4 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 );
126 end component;
127
109 --==============================================================|
128 --==============================================================|
110 --================== IP VHDL de la FFT actel ===================|
129 --================== IP VHDL de la FFT actel ===================|
111 --================ non partag� dans la VHD_Lib =================|
130 --================ non partag� dans la VHD_Lib =================|
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@@ -25,7 +25,6 library lpp;
25 use lpp.lpp_ad_conv.all;
25 use lpp.lpp_ad_conv.all;
26 use lpp.general_purpose.Clk_divider;
26 use lpp.general_purpose.Clk_divider;
27
27
28
29 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
28 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
30 --!
29 --!
31 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
30 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
@@ -37,8 +36,9 generic(
37 );
36 );
38 Port(
37 Port(
39 clk : in STD_LOGIC; --! System clock
38 clk : in STD_LOGIC; --! System clock
40 reset : in STD_LOGIC; --! System reset
39 rstn : in STD_LOGIC; --! System reset
41 smplClk : in STD_LOGIC; --! Sampling clock
40 enable : in std_logic; --! Negative enable
41 smplClk : in STD_LOGIC; --! Sampling clock
42 DataReady : out std_logic; --! New sample available
42 DataReady : out std_logic; --! New sample available
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
@@ -52,13 +52,15 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
52
52
53 signal i : integer range 0 to convTrigger :=0;
53 signal i : integer range 0 to convTrigger :=0;
54 signal clk_int : std_logic;
54 signal clk_int : std_logic;
55 signal clk_int_inv : std_logic;
55 signal smplClk_reg : std_logic;
56 signal smplClk_reg : std_logic;
56 signal cnv_int : std_logic;
57 signal cnv_int : std_logic;
58 signal reset : std_logic;
57
59
58 begin
60 begin
59
61
60 clkdiv: if clkkHz>=66000 generate
62 clkdiv: if clkkHz>=66000 generate
61 clkdivider: Clk_divider
63 clkdivider: entity work.Clk_divider
62 generic map(clkkHz*1000,60000000)
64 generic map(clkkHz*1000,60000000)
63 Port map( clk ,reset,clk_int);
65 Port map( clk ,reset,clk_int);
64 end generate;
66 end generate;
@@ -67,9 +69,11 clknodiv: if clkkHz<66000 generate
67 nodiv: clk_int <= clk;
69 nodiv: clk_int <= clk;
68 end generate;
70 end generate;
69
71
72 clk_int_inv <= not clk_int;
73
70 AD_out.CNV <= cnv_int;
74 AD_out.CNV <= cnv_int;
71 AD_out.SCK <= clk_int;
75 AD_out.SCK <= clk_int;
72
76 reset <= rstn and enable;
73
77
74 sckgen: process(clk,reset)
78 sckgen: process(clk,reset)
75 begin
79 begin
@@ -95,9 +99,9 end process;
95
99
96
100
97
101
98 spidrvr: AD7688_spi_if
102 spidrvr: entity work.AD7688_spi_if
99 generic map(ChanelCount)
103 generic map(ChanelCount)
100 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout);
104 Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
101
105
102
106
103
107
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@@ -1,78 +1,78
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
23 use IEEE.STD_LOGIC_1164.ALL;
24 library lpp;
24 library lpp;
25 use lpp.lpp_ad_conv.all;
25 use lpp.lpp_ad_conv.all;
26 use lpp.general_purpose.Clk_divider;
26 use lpp.general_purpose.Clk_divider;
27
27
28 entity AD7688_spi_if is
28 entity AD7688_spi_if is
29 generic(ChanelCount : integer);
29 generic(ChanelCount : integer);
30 Port( clk : in STD_LOGIC;
30 Port( clk : in STD_LOGIC;
31 reset : in STD_LOGIC;
31 reset : in STD_LOGIC;
32 cnv : in STD_LOGIC;
32 cnv : in STD_LOGIC;
33 DataReady: out std_logic;
33 DataReady : out std_logic;
34 sdi : in AD7688_in(ChanelCount-1 downto 0);
34 sdi : in AD7688_in(ChanelCount-1 downto 0);
35 smpout : out Samples_out(ChanelCount-1 downto 0)
35 smpout : out Samples_out(ChanelCount-1 downto 0)
36 );
36 );
37 end AD7688_spi_if;
37 end AD7688_spi_if;
38
38
39 architecture ar_AD7688_spi_if of AD7688_spi_if is
39 architecture ar_AD7688_spi_if of AD7688_spi_if is
40
40
41 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
41 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
42 signal i : integer range 0 to 15 :=0;
42 signal i : integer range 0 to 16 :=0;
43 signal cnv_reg : std_logic := '0';
43 signal cnv_reg : std_logic := '0';
44
44
45 begin
45 begin
46
46
47
47
48
48
49 process(clk,reset)
49 process(clk,reset)
50 begin
50 begin
51 if reset = '0' then
51 if reset = '0' then
52 for l in 0 to ChanelCount-1 loop
52 for l in 0 to ChanelCount-1 loop
53 shift_reg(l) <= (others => '0');
53 shift_reg(l) <= (others => '0');
54 end loop;
54 end loop;
55 i <= 0;
55 i <= 0;
56 cnv_reg <= '0';
56 cnv_reg <= '0';
57 elsif clk'event and clk = '1' then
57 elsif clk'event and clk = '1' then
58 if cnv = '0' and cnv_reg = '0' then
58 if cnv = '0' and cnv_reg = '0' then
59 if i = 15 then
59 if i = 16 then
60 i <= 0;
60 i <= 0;
61 cnv_reg <= '1';
61 cnv_reg <= '1';
62 else
62 else
63 DataReady <= '0';
63 DataReady <= '0';
64 i <= i+1;
64 i <= i+1;
65 for l in 0 to ChanelCount-1 loop
65 for l in 0 to ChanelCount-1 loop
66 shift_reg(l)(0) <= sdi(l).SDI;
66 shift_reg(l)(0) <= sdi(l).SDI;
67 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0);
67 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0);
68 end loop;
68 end loop;
69 end if;
69 end if;
70 else
70 else
71 cnv_reg <= not cnv;
71 cnv_reg <= not cnv;
72 smpout <= shift_reg;
72 smpout <= shift_reg;
73 DataReady <= '1';
73 DataReady <= '1';
74 end if;
74 end if;
75 end if;
75 end if;
76 end process;
76 end process;
77
77
78 end ar_AD7688_spi_if;
78 end ar_AD7688_spi_if;
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@@ -54,7 +54,8 package lpp_ad_conv is
54 generic(ChanelCount : integer;
54 generic(ChanelCount : integer;
55 clkkHz : integer);
55 clkkHz : integer);
56 Port ( clk : in STD_LOGIC;
56 Port ( clk : in STD_LOGIC;
57 reset : in STD_LOGIC;
57 rstn : in STD_LOGIC;
58 enable : in std_logic;
58 smplClk: in STD_LOGIC;
59 smplClk: in STD_LOGIC;
59 DataReady : out std_logic;
60 DataReady : out std_logic;
60 smpout : out Samples_out(ChanelCount-1 downto 0);
61 smpout : out Samples_out(ChanelCount-1 downto 0);
@@ -68,7 +69,7 component AD7688_spi_if is
68 Port( clk : in STD_LOGIC;
69 Port( clk : in STD_LOGIC;
69 reset : in STD_LOGIC;
70 reset : in STD_LOGIC;
70 cnv : in STD_LOGIC;
71 cnv : in STD_LOGIC;
71 DataReady: out std_logic;
72 DataReady: out std_logic;
72 sdi : in AD7688_in(ChanelCount-1 downto 0);
73 sdi : in AD7688_in(ChanelCount-1 downto 0);
73 smpout : out Samples_out(ChanelCount-1 downto 0)
74 smpout : out Samples_out(ChanelCount-1 downto 0)
74 );
75 );
@@ -100,7 +101,7 component ADS7886_drvr is
100 clkkHz : integer);
101 clkkHz : integer);
101 Port (
102 Port (
102 clk : in STD_LOGIC;
103 clk : in STD_LOGIC;
103 reset : in STD_LOGIC;
104 reset : in STD_LOGIC;
104 smplClk : in STD_LOGIC;
105 smplClk : in STD_LOGIC;
105 DataReady : out std_logic;
106 DataReady : out std_logic;
106 smpout : out Samples_out(ChanelCount-1 downto 0);
107 smpout : out Samples_out(ChanelCount-1 downto 0);
@@ -109,6 +110,17 component ADS7886_drvr is
109 );
110 );
110 end component;
111 end component;
111
112
113 component WriteGen_ADC is
114 port(
115 clk : in std_logic;
116 rstn : in std_logic;
117 SmplCLK : in std_logic;
118 DataReady : in std_logic;
119 Full : in std_logic_vector(4 downto 0);
120 ReUse : out std_logic_vector(4 downto 0);
121 Write : out std_logic_vector(4 downto 0)
122 );
123 end component;
112
124
113 end lpp_ad_conv;
125 end lpp_ad_conv;
114
126
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@@ -14,7 +14,7
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
@@ -54,7 +54,8 generic (
54 clk : in std_logic; --! Horloge du composant
54 clk : in std_logic; --! Horloge du composant
55 rst : in std_logic; --! Reset general du composant
55 rst : in std_logic; --! Reset general du composant
56 rclk : in std_logic;
56 rclk : in std_logic;
57 wclk : in std_logic;
57 wclk : in std_logic;
58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
58 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
59 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
60 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
@@ -103,7 +104,8 signal sRDATA : fifodatabus;
103 signal sWDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
104 signal sWADDR : fifoaddressbus;
105 signal sWADDR : fifoaddressbus;
105 signal sRADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
106 signal ReUse : std_logic_vector(FifoCnt-1 downto 0); --27/01/12
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
107
109
108 type state_t is (idle,Read);
110 type state_t is (idle,Read);
109 signal fiforeadfsmst : state_t;
111 signal fiforeadfsmst : state_t;
@@ -118,6 +120,7 FIFO_ID(23 downto 16) <= std_logic_vecto
118 Write : if W /= 0 generate
120 Write : if W /= 0 generate
119 FIFO_ID(4) <= '1';
121 FIFO_ID(4) <= '1';
120 sWen <= sWen_APB;
122 sWen <= sWen_APB;
123 sReUse <= sReUse_APB;
121 sWclk <= clk;
124 sWclk <= clk;
122 Wrapb: for i in 0 to FifoCnt-1 generate
125 Wrapb: for i in 0 to FifoCnt-1 generate
123 sWDATA(i) <= Rec(i).FIFO_Wdata;
126 sWDATA(i) <= Rec(i).FIFO_Wdata;
@@ -127,6 +130,7 end generate;
127 Writeext : if W = 0 generate
130 Writeext : if W = 0 generate
128 FIFO_ID(4) <= '0';
131 FIFO_ID(4) <= '0';
129 sWen <= WEN;
132 sWen <= WEN;
133 sReUse <= ReUse;
130 sWclk <= Wclk;
134 sWclk <= Wclk;
131 Wrext: for i in 0 to FifoCnt-1 generate
135 Wrext: for i in 0 to FifoCnt-1 generate
132 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
136 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
@@ -156,7 +160,7 ctrlregs: for i in 0 to FifoCnt-1 genera
156 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
160 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
157 Rec(i).FIFO_Ctrl(16) <= sFull(i);
161 Rec(i).FIFO_Ctrl(16) <= sFull(i);
158 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
162 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
159 ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
163 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
160 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
164 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
161 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
165 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
162 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
166 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
@@ -170,7 +174,7 Full <= sFull;
170 fifos: for i in 0 to FifoCnt-1 generate
174 fifos: for i in 0 to FifoCnt-1 generate
171 FIFO0 : lpp_fifo
175 FIFO0 : lpp_fifo
172 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
176 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
173 port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
177 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
174 end generate;
178 end generate;
175
179
176 process(rst,clk)
180 process(rst,clk)
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@@ -55,7 +55,8 generic (
55 clk : in std_logic; --! Horloge du composant
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
57 rclk : in std_logic;
58 wclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
@@ -94,7 +95,7 port(
94 end component;
95 end component;
95
96
96
97
97 component SM_5lppFIFO is
98 component lppFIFOx5 is
98 generic(
99 generic(
99 tech : integer := 0;
100 tech : integer := 0;
100 Data_sz : integer range 1 to 32 := 16;
101 Data_sz : integer range 1 to 32 := 16;
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