# HG changeset patch # User martin # Date 2012-06-12 11:57:22 # Node ID 0de5e600d49ba4b23d9aebd65fc3209c5fc7d88e # Parent 5dd8398817e7daa8e41a5a622c36746ae4b2c7ad update ADC diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd @@ -0,0 +1,212 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.iir_filter.all; +use lpp.general_purpose.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; + +entity APB_IIR_CEL is + generic ( + tech : integer := 0; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 6; + Cels_count : integer := 5; + virgPos : integer := 3; + Mem_use : integer := use_RAM + ); + port ( + rst : in std_logic; + clk : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + sample_clk : in std_logic; + sample_clk_out : out std_logic; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') + ); +end; + + +architecture AR_APB_IIR_CEL of APB_IIR_CEL is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + + + +type FILTERreg is record + regin : in_IIR_CEL_reg; + regout : out_IIR_CEL_reg; +end record; + +signal Rdata : std_logic_vector(31 downto 0); +signal r : FILTERreg; +signal filter_reset : std_logic:='0'; +signal smp_cnt : integer :=0; +signal sample_clk_out_R : std_logic; +signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0); + +type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); +type CoefTblT is array(0 to Cels_count-1) of CoefCelT; + +type CoefsRegT is record + numCoefs : CoefTblT; + denCoefs : CoefTblT; +end record; + +signal CoefsReg : CoefsRegT; +signal CoefsReg_d : CoefsRegT; + + +begin + +filter_reset <= rst and r.regin.config(0); +sample_clk_out <= sample_clk_out_R; +-- +filter : IIR_CEL_FILTER +generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) +port map( + reset => filter_reset, + clk => clk, + sample_clk => sample_clk, + regs_in => r.regin, + regs_out => r.regout, + sample_in => sample_in, + sample_out => sample_out, + coefs => RawCoefs + ); + +process(rst,sample_clk) +begin +if rst = '0' then + smp_cnt <= 0; + sample_clk_out_R <= '0'; +elsif sample_clk'event and sample_clk = '1' then + if smp_cnt = 1 then + smp_cnt <= 0; + sample_clk_out_R <= not sample_clk_out_R; + else + smp_cnt <= smp_cnt +1; + end if; +end if; +end process; + + +coefsConnectL0: for z in 0 to Cels_count-1 generate + coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate + RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0); + RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0); + end generate; +end generate; + + +process(rst,clk) +begin + if rst = '0' then + r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); +coefsRstL0: for z in 0 to Cels_count-1 loop + coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop + CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); + CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); + end loop; +end loop; + elsif clk'event and clk = '1' then + CoefsReg_d <= CoefsReg; + +--APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + if apbi.paddr(7 downto 2) = "000000" then + r.regin.config(0) <= apbi.pwdata(0); + elsif apbi.paddr(7 downto 2) = "000001" then + r.regin.virgPos <= apbi.pwdata(4 downto 0); + else + for i in 0 to Cels_count-1 loop + for j in 0 to (CoefCntPerCel/2) - 1 loop + if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then + CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0); + CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16); + end if; + end loop; + end loop; + end if; + end if; + +--APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + if apbi.paddr(7 downto 2) = "000000" then + Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8)); + Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8)); + Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8)); + Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8)); + elsif apbi.paddr(7 downto 2) = "000001" then + Rdata(4 downto 0) <= r.regin.virgPos; + Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8)); + Rdata(7 downto 5) <= (others => '0'); + Rdata(31 downto 16) <= (others => '0'); + else + for i in 0 to Cels_count-1 loop + for j in 0 to (CoefCntPerCel/2) - 1 loop + if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then + Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j); + Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j); + end if; + end loop; + end loop; + end if; + end if; + end if; + apbo.pconfig <= pconfig; +end process; + +apbo.prdata <= Rdata when apbi.penable = '1' ; + +-- pragma translate_off + bootmsg : report_version + generic map ("apb IIR filter" & tost(pindex) & + ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) & + ", irq " & tost(pirq)); +-- pragma translate_on + + + + +end ar_APB_IIR_CEL; + diff --git a/lib/lpp/dsp/iir_filter/FILTER.vhd b/lib/lpp/dsp/iir_filter/FILTER.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/FILTER.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.FILTERcfg.all; +use lpp.general_purpose.all; +--Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs) +--exemple 26MHz sys clock and 6 chanels @ 110ksmps/s +--Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs + +entity FILTER is +generic(Smpl_SZ : integer := 16; + ChanelsCNT : integer := 3 +); +port( + + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); + Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) +); +end entity; + + + + + +architecture ar_FILTER of FILTER is + + + + +signal ALU_ctrl : std_logic_vector(3 downto 0); +signal Sample : std_logic_vector(Smpl_SZ-1 downto 0); +signal Coef : std_logic_vector(Coef_SZ-1 downto 0); +signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0); + +begin + +--============================================================== +--=========================A L U================================ +--============================================================== +ALU1 : entity ALU +generic map( + Arith_en => 1, + Logic_en => 0, + Input_SZ_1 => Smpl_SZ, + Input_SZ_2 => Coef_SZ + +) +port map( + clk => clk, + reset => reset, + ctrl => ALU_ctrl, + OP1 => Sample, + OP2 => Coef, + RES => ALU_OUT +); +--============================================================== + +--============================================================== +--===============F I L T E R C O N T R O L E R================ +--============================================================== +filterctrlr1 : FilterCTRLR +port map( + reset => reset, + clk => clk, + sample_clk => sample_clk, + ALU_Ctrl => ALU_ctrl, + sample_in => sample_Tbl, + coef => Coef, + sample => Sample +); +--============================================================== + +chanelCut : for i in 0 to ChanelsCNT-1 generate + sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ); +end generate; + + + + +end ar_FILTER; + diff --git a/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd b/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd @@ -0,0 +1,228 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.FILTERcfg.all; +use lpp.general_purpose.all; + +--TODO am�liorer la flexibilit� de la config de la RAM. + +entity FILTER_RAM_CTRLR is +port( + reset : in std_logic; + clk : in std_logic; + run : in std_logic; + GO_0 : in std_logic; + B_A : in std_logic; + writeForce : in std_logic; + next_blk : in std_logic; + sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); + sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) +); +end FILTER_RAM_CTRLR; + + +architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is + +signal WD : std_logic_vector(35 downto 0); +signal WD_D : std_logic_vector(35 downto 0); +signal RD : std_logic_vector(35 downto 0); +signal WEN, REN : std_logic; +signal WADDR_back : std_logic_vector(7 downto 0); +signal WADDR_back_D: std_logic_vector(7 downto 0); +signal RADDR : std_logic_vector(7 downto 0); +signal WADDR : std_logic_vector(7 downto 0); +signal WADDR_D : std_logic_vector(7 downto 0); +signal run_D : std_logic; +signal run_D_inv : std_logic; +signal run_inv : std_logic; +signal next_blk_D : std_logic; +signal MUX2_inst1_sel : std_logic; + + +begin + +sample_out <= RD(Smpl_SZ-1 downto 0); + +MUX2_inst1_sel <= run_D and not next_blk; +run_D_inv <= not run_D; +run_inv <= not run; +WEN <= run_D_inv and not writeForce; +REN <= run_inv ;--and not next_blk; + + +--============================================================== +--=========================R A M================================ +--============================================================== +memRAM : if Mem_use = use_RAM generate +RAMblk :RAM + port map( + WD => WD_D, + RD => RD, + WEN => WEN, + REN => REN, + WADDR => WADDR, + RADDR => RADDR, + RWCLK => clk, + RESET => reset + ) ; +end generate; + +memCEL : if Mem_use = use_CEL generate +RAMblk :RAM_CEL + port map( + WD => WD_D, + RD => RD, + WEN => WEN, + REN => REN, + WADDR => WADDR, + RADDR => RADDR, + RWCLK => clk, + RESET => reset + ) ; +end generate; +--============================================================== +--============================================================== + + +ADDRcntr_inst : ADDRcntr +port map( + clk => clk, + reset => reset, + count => run, + clr => GO_0, + Q => RADDR +); + + + +MUX2_inst1 :MUX2 +generic map(Input_SZ => Smpl_SZ) +port map( + sel => MUX2_inst1_sel, + IN1 => sample_in, + IN2 => RD(Smpl_SZ-1 downto 0), + RES => WD(Smpl_SZ-1 downto 0) +); + + +MUX2_inst2 :MUX2 +generic map(Input_SZ => 8) +port map( + sel => next_blk_D, + IN1 => WADDR_D, + IN2 => WADDR_back_D, + RES => WADDR +); + + +next_blkRreg :REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => next_blk, + Q(0) => next_blk_D +); + +WADDR_backreg :REG +generic map(size => 8) +port map( + reset => reset, + clk => B_A, + D => RADDR, + Q => WADDR_back +); + +WADDR_backreg2 :REG +generic map(size => 8) +port map( + reset => reset, + clk => B_A, + D => WADDR_back, + Q => WADDR_back_D +); + +WDRreg :REG +generic map(size => Smpl_SZ) +port map( + reset => reset, + clk => clk, + D => WD(Smpl_SZ-1 downto 0), + Q => WD_D(Smpl_SZ-1 downto 0) +); + +RunRreg :REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => run, + Q(0) => run_D +); + + + +ADDRreg :REG +generic map(size => 8) +port map( + reset => reset, + clk => clk, + D => RADDR, + Q => WADDR_D +); + + + +end ar_FILTER_RAM_CTRLR; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd @@ -0,0 +1,196 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + + +package FILTERcfg is + + + + +--===========================================================| +--========F I L T E R C O N F I G V A L U E S=============| +--===========================================================| +--____________________________ +--Bus Width and chanels number| +--____________________________| +constant ChanelsCNT : integer := 6; +constant Smpl_SZ : integer := 16; +constant Coef_SZ : integer := 9; +constant Scalefac_SZ: integer := 3; +constant Cels_count : integer := 5; + +constant Mem_use : integer := 1; + + + +--============================================================ +-- create each initial values for each coefs ============ +--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! +--============================================================ +--constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ)); +--constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); +--constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); +--constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); +--constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); +--constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); +--constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); +-- +--constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); +--constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ)); +--constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); +--constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ)); +-- +-- +--constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); +--constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ)); +--constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); +-- +--constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); +--constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ)); +--constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); +-- +--constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); +--constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ)); +--constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); +-- +--constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); +--constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ)); +--constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); +-- +--constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); +--constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ)); +--constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); +-- +--constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); +--constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); +--constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); +-- +--constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); +--constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); +--constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); +-- +-- +--constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ)); +--constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ)); +-- +--constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ)); +--constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); +-- +--constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ)); +--constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ)); +-- +--constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ)); +--constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ)); +-- +--constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ)); +--constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ)); +-- +--constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); +--constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); +--constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); +--constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); +--constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); +-- +-- +--constant celb0 : coef_celT := (b0_0,b0_1,b0_2); +--constant celb1 : coef_celT := (b1_0,b1_1,b1_2); +--constant celb2 : coef_celT := (b2_0,b2_1,b2_2); +--constant celb3 : coef_celT := (b3_0,b3_1,b3_2); +--constant celb4 : coef_celT := (b4_0,b4_1,b4_2); +--constant celb5 : coef_celT := (b5_0,b5_1,b5_2); +--constant celb6 : coef_celT := (b6_0,b6_1,b6_2); +-- +--constant cela0 : coef_celT := (a0_0,a0_1,a0_2); +--constant cela1 : coef_celT := (a1_0,a1_1,a1_2); +--constant cela2 : coef_celT := (a2_0,a2_1,a2_2); +--constant cela3 : coef_celT := (a3_0,a3_1,a3_2); +--constant cela4 : coef_celT := (a4_0,a4_1,a4_2); +--constant cela5 : coef_celT := (a5_0,a5_1,a5_2); +--constant cela6 : coef_celT := (a6_0,a6_1,a6_2); +-- +-- +-- +--constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4); +--constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4); +--constant virgPos : integer := 7; +-- +-- +-- +-- +-- +-- +-- +--signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6); +--signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4); +-- +-- +--signal sample_Tbl : samplT; + + +end; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd b/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd @@ -0,0 +1,265 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.FILTERcfg.all; +use lpp.general_purpose.all; + +--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre + +entity FilterCTRLR is +port( + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + ALU_Ctrl : out std_logic_vector(3 downto 0); + sample_in : in samplT; + coef : out std_logic_vector(Coef_SZ-1 downto 0); + sample : out std_logic_vector(Smpl_SZ-1 downto 0) +); +end FilterCTRLR; + + +architecture ar_FilterCTRLR of FilterCTRLR is + +constant NUMCoefsCnt : integer:= NumeratorCoefs'high; +constant DENCoefsCnt : integer:= DenominatorCoefs'high; + +signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0; +signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0; + +signal chanelCnt : integer range 0 to 15:=0; + +signal WD : std_logic_vector(35 downto 0); +signal WD_D : std_logic_vector(35 downto 0); +signal RD : std_logic_vector(35 downto 0); +signal WEN, REN,WEN_D : std_logic; +signal WADDR_back : std_logic_vector(7 downto 0); +signal ADDR : std_logic_vector(7 downto 0); +signal ADDR_D : std_logic_vector(7 downto 0); +signal clk_inv : std_logic; + +type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0); +signal in_Rotate_Buff : Rotate_BuffT; +signal out_Rotate_Buff : Rotate_BuffT; + +signal sample_clk_old : std_logic; + +type stateT is (waiting,computeNUM,computeDEN,NextChanel); +signal state : stateT; + +begin +clk_inv <= not clk; + +process(clk,reset) +begin +if reset = '0' then + state <= waiting; + WEN <= '1'; + REN <= '1'; + ADDR <= (others => '0'); + WD <= (others => '0'); + NcoefCnt <= 0; + DcoefCnt <= 0; + chanelCnt <= 0; + ALU_Ctrl <= clr_mac; + sample_clk_old <= '0'; + coef <= (others => '0'); + sample <= (others => '0'); +rst:for i in 0 to ChanelsCNT-1 loop + in_Rotate_Buff(i) <= (others => '0'); + end loop; +elsif clk'event and clk = '1' then + + sample_clk_old <= sample_clk; + +--================================================================= +--===============DATA processing=================================== +--================================================================= + case state is + when waiting=> + + if sample_clk_old = '0' and sample_clk = '1' then + ALU_Ctrl <= MAC_op; + sample <= in_Rotate_Buff(0); + coef <= std_logic_vector(NumeratorCoefs(0)); + else + ALU_Ctrl <= clr_mac; +loadinput: for i in 0 to ChanelsCNT-1 loop + in_Rotate_Buff(i) <= sample_in(i); + end loop; + end if; + + when computeNUM=> + ALU_Ctrl <= MAC_op; + sample <= RD(Smpl_SZ-1 downto 0); + coef <= std_logic_vector(NumeratorCoefs(NcoefCnt)); + + when computeDEN=> + ALU_Ctrl <= MAC_op; + sample <= RD(Smpl_SZ-1 downto 0); + coef <= std_logic_vector(DenominatorCoefs(DcoefCnt)); + + when NextChanel=> +rotate : for i in 0 to ChanelsCNT-2 loop + in_Rotate_Buff(i) <= in_Rotate_Buff(i+1); + end loop; +rotatetoo: if ChanelsCNT > 1 then + sample <= in_Rotate_Buff(1); + coef <= std_logic_vector(NumeratorCoefs(0)); + end if; + end case; + +--================================================================= +--===============RAM read write==================================== +--================================================================= + case state is + when waiting=> + if sample_clk_old = '0' and sample_clk = '1' then + REN <= '0'; + else + REN <= '1'; + end if; + ADDR <= (others => '0'); + WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0); + WEN <= '1'; + + when computeNUM=> + WD <= RD; + REN <= '0'; + WEN <= '0'; + ADDR <= std_logic_vector(unsigned(ADDR)+1); + when computeDEN=> + WD <= RD; + REN <= '0'; + WEN <= '0'; + ADDR <= std_logic_vector(unsigned(ADDR)+1); + when NextChanel=> + REN <= '1'; + WEN <= '1'; + end case; +--================================================================= + + +--================================================================= +--===============FSM Management==================================== +--================================================================= + case state is + when waiting=> + if sample_clk_old = '0' and sample_clk = '1' then + state <= computeNUM; + end if; + DcoefCnt <= 0; + NcoefCnt <= 1; + chanelCnt<= 0; + when computeNUM=> + if NcoefCnt = NumCoefsCnt then + state <= computeDEN; + NcoefCnt <= 1; + else + NcoefCnt <= NcoefCnt+1; + end if; + when computeDEN=> + if DcoefCnt = DENCoefsCnt then + state <= NextChanel; + DcoefCnt <= 0; + else + DcoefCnt <= DcoefCnt+1; + end if; + when NextChanel=> + if chanelCnt = (ChanelsCNT-1) then + state <= waiting; + else + chanelCnt<= chanelCnt+1; + state <= computeNUM; + end if; + end case; +--================================================================= + +end if; +end process; + +ADDRreg : REG +generic map(size => 8) +port map( + reset => reset, + clk => clk, + D => ADDR, + Q => ADDR_D +); + +WDreg :REG +generic map(size => 36) +port map( + reset => reset, + clk => clk, + D => WD, + Q => WD_D +); + +WRreg :REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => WEN, + Q(0) => WEN_D +); +--============================================================== +--=========================R A M================================ +--============================================================== +memRAM : if Mem_use = use_RAM generate +RAMblk :RAM + port map( + WD => WD_D, + RD => RD, + WEN => WEN_D, + REN => REN, + WADDR => ADDR_D, + RADDR => ADDR, + RWCLK => clk_inv, + RESET => reset + ) ; +end generate; + +memCEL : if Mem_use = use_CEL generate +RAMblk :RAM + port map( + WD => WD_D, + RD => RD, + WEN => WEN_D, + REN => REN, + WADDR => ADDR_D, + RADDR => ADDR, + RWCLK => clk_inv, + RESET => reset + ) ; +end generate; + +--============================================================== + + + +end ar_FilterCTRLR; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd @@ -0,0 +1,337 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.general_purpose.all; + +--TODO amliorer la gestion de la RAM et de la flexibilit du filtre + +entity IIR_CEL_CTRLR is +generic( + tech : integer := 0; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 6; + Cels_count : integer := 5; + Mem_use : integer := use_RAM +); +port( + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + virg_pos : in integer; + coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0) +); +end IIR_CEL_CTRLR; + + + + +architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is + +subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0); + +signal smpl_clk_old : std_logic := '0'; +signal WD_sel : std_logic := '0'; +signal Read : std_logic := '0'; +signal SVG_ADDR : std_logic := '0'; +signal count : std_logic := '0'; +signal Write : std_logic := '0'; +signal WADDR_sel : std_logic := '0'; +signal GO_0 : std_logic := '0'; + +signal RAM_sample_in : sampleVect; +signal RAM_sample_in_bk: sampleVect; +signal RAM_sample_out : sampleVect; +signal ALU_ctrl : std_logic_vector(3 downto 0); +signal ALU_sample_in : sampleVect; +signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0); +signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0); +signal curentCel : integer range 0 to Cels_count-1 := 0; +signal curentChan : integer range 0 to ChanelsCount-1 := 0; + + +type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect; + +signal sample_in_BUFF : sampleBuffT; +signal sample_out_BUFF : sampleBuffT; + +type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0); +type CoefTblT is array(0 to Cels_count-1) of CoefCelT; + +type CoefsRegT is record + numCoefs : CoefTblT; + denCoefs : CoefTblT; +end record; + +signal CoefsReg : CoefsRegT; + +type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan); + +signal IIR_CEL_STATE : fsmIIR_CEL_T; + +begin + + +--coefsConnectL0: for z in 0 to Cels_count-1 generate +-- coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate +-- coefsConnectL2: for x in 0 to Coef_SZ-1 generate +-- CoefsReg.numCoefs(z)(y)(x) <= coefs(x + (((2*y))*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel)); +-- CoefsReg.denCoefs(z)(y)(x) <= coefs(x + (((2*y)+1)*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel)); +-- end generate; +-- end generate; +--end generate; + +coefsConnectL0: for z in 0 to Cels_count-1 generate + coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate + CoefsReg.numCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ); + CoefsReg.denCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)); + end generate; +end generate; + + + + +RAM_CTRLR2inst : RAM_CTRLR2 +generic map(tech,Sample_SZ,Mem_use) +port map( + reset => reset, + clk => clk, + WD_sel => WD_sel, + Read => Read, + WADDR_sel => WADDR_sel, + count => count, + SVG_ADDR => SVG_ADDR, + Write => Write, + GO_0 => GO_0, + sample_in => RAM_sample_in, + sample_out => RAM_sample_out +); + + + +ALU_inst :ALU +generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) +port map( + clk => clk, + reset => reset, + ctrl => ALU_ctrl, + OP1 => ALU_sample_in, + OP2 => ALU_coef_in, + RES => ALU_out +); + + + + + + +WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1'; +Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; +WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0'; +count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0'; +SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0'; +--Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0'; +Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; + +GO_0 <= '1' when IIR_CEL_STATE = waiting else '0'; + + + + + + + +process(clk,reset) +variable result : std_logic_vector(Sample_SZ-1 downto 0); + +begin + +if reset = '0' then + + smpl_clk_old <= '0'; + RAM_sample_in <= (others=> '0'); + ALU_ctrl <= IDLE; + ALU_sample_in <= (others=> '0'); + ALU_Coef_in <= (others=> '0'); + RAM_sample_in_bk<= (others=> '0'); + curentCel <= 0; + curentChan <= 0; + IIR_CEL_STATE <= waiting; +resetL0 : for i in 0 to ChanelsCount-1 loop + sample_in_BUFF(i) <= (others => '0'); + sample_out_BUFF(i) <= (others => '0'); + resetL1: for j in 0 to Sample_SZ-1 loop + sample_out(i,j) <= '0'; + end loop; + end loop; + +elsif clk'event and clk = '1' then + + smpl_clk_old <= sample_clk; + + case IIR_CEL_STATE is + + when waiting => + if sample_clk = '1' and smpl_clk_old = '0' then + IIR_CEL_STATE <= pipe1; + RAM_sample_in <= std_logic_vector(sample_in_BUFF(0)); + ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); + + else + ALU_ctrl <= IDLE; + smplConnectL0: for i in 0 to ChanelsCount-1 loop + smplConnectL1: for j in 0 to Sample_SZ-1 loop + sample_in_BUFF(i)(j) <= sample_in(i,j); + sample_out(i,j) <= sample_out_BUFF(i)(j); + end loop; + end loop; + end if; + curentCel <= 0; + curentChan <= 0; + + when pipe1 => + IIR_CEL_STATE <= computeb1; + ALU_ctrl <= MAC_op; + ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); + + when computeb1 => + + ALU_ctrl <= MAC_op; + ALU_sample_in <= RAM_sample_out; + ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); + IIR_CEL_STATE <= computeb2; + RAM_sample_in <= RAM_sample_in_bk; + when computeb2 => + ALU_sample_in <= RAM_sample_out; + ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2)); + IIR_CEL_STATE <= computea1; + + + when computea1 => + ALU_sample_in <= RAM_sample_out; + ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1)); + IIR_CEL_STATE <= computea2; + + + when computea2 => + ALU_sample_in <= RAM_sample_out; + ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2)); + IIR_CEL_STATE <= next_cel; + + + when next_cel => + ALU_ctrl <= clr_mac; + IIR_CEL_STATE <= pipe2; + + when pipe2 => + IIR_CEL_STATE <= pipe3; + + + when pipe3 => + + result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos); + + sample_out_BUFF(0) <= result; + RAM_sample_in_bk <= result; + RAM_sample_in <= result; + if curentCel = Cels_count-1 then + IIR_CEL_STATE <= next_chan; + curentCel <= 0; + else + curentCel <= curentCel + 1; + IIR_CEL_STATE <= pipe1; + ALU_sample_in <= result; + end if; + when next_chan => + +rotate : for i in 1 to ChanelsCount-1 loop + sample_in_BUFF(i-1) <= sample_in_BUFF(i); + sample_out_BUFF(i-1) <= sample_out_BUFF(i); + end loop; + sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0); + sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0); + + if curentChan = (ChanelsCount-1) then + IIR_CEL_STATE <= waiting; + ALU_ctrl <= clr_mac; + elsif ChanelsCount>1 then + curentChan <= curentChan + 1; + IIR_CEL_STATE <= pipe1; + ALU_sample_in <= sample_in_BUFF(1); + RAM_sample_in <= sample_in_BUFF(1); + end if; + end case; + +end if; +end process; + + + + + + +end ar_IIR_CEL_CTRLR; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd @@ -0,0 +1,97 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.general_purpose.all; + +--TODO amliorer la gestion de la RAM et de la flexibilit du filtre + +entity IIR_CEL_FILTER is +generic( + tech : integer := 0; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 6; + Cels_count : integer := 5; + Mem_use : integer := use_RAM); +port( + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + regs_in : in in_IIR_CEL_reg; + regs_out : in out_IIR_CEL_reg; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0) + +); +end IIR_CEL_FILTER; + + + + +architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is + +signal virg_pos : integer; +begin + +virg_pos <= to_integer(unsigned(regs_in.virgPos)); + +CTRLR : IIR_CEL_CTRLR +generic map (tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) +port map( + reset => reset, + clk => clk, + sample_clk => sample_clk, + sample_in => sample_in, + sample_out => sample_out, + virg_pos => virg_pos, + coefs => coefs +); + + + + + +end ar_IIR_CEL_FILTER; + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/RAM.vhd b/lib/lpp/dsp/iir_filter/RAM.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/RAM.vhd @@ -0,0 +1,64 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity RAM is + port( WD : in std_logic_vector(35 downto 0); RD : out + std_logic_vector(35 downto 0);WEN, REN : in std_logic; + WADDR : in std_logic_vector(7 downto 0); RADDR : in + std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic + ) ; +end RAM; + + +architecture DEF_ARCH of RAM is +type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); +signal RAMarray : RAMarrayT:=(others => X"000000000"); +signal RD_int : std_logic_vector(35 downto 0); + +begin + +RD_int <= RAMarray(to_integer(unsigned(RADDR))); + + +process(RWclk,reset) +begin +if reset = '0' then + RD <= (X"000000000"); +rst:for i in 0 to 255 loop + RAMarray(i) <= (others => '0'); + end loop; + +elsif RWclk'event and RWclk = '1' then + if REN = '0' then + RD <= RD_int; + end if; + + if WEN = '0' then + RAMarray(to_integer(unsigned(WADDR))) <= WD; + end if; + +end if; +end process; +end DEF_ARCH; diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity RAM_CEL is + port( WD : in std_logic_vector(35 downto 0); RD : out + std_logic_vector(35 downto 0);WEN, REN : in std_logic; + WADDR : in std_logic_vector(7 downto 0); RADDR : in + std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic + ) ; +end RAM_CEL; + + + +architecture ar_RAM_CEL of RAM_CEL is +type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); +signal RAMarray : RAMarrayT:=(others => X"000000000"); +signal RD_int : std_logic_vector(35 downto 0); + +begin + +RD_int <= RAMarray(to_integer(unsigned(RADDR))); + + +process(RWclk,reset) +begin +if reset = '0' then + RD <= (X"000000000"); +rst:for i in 0 to 255 loop + RAMarray(i) <= (others => '0'); + end loop; + +elsif RWclk'event and RWclk = '1' then + if REN = '0' then + RD <= RD_int; + end if; + + if WEN = '0' then + RAMarray(to_integer(unsigned(WADDR))) <= WD; + end if; + +end if; +end process; +end ar_RAM_CEL; + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd @@ -0,0 +1,221 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.iir_filter.all; +use lpp.FILTERcfg.all; +use lpp.general_purpose.all; +library techmap; +use techmap.gencomp.all; + +--TODO amliorer la flexibilit de la config de la RAM. + +entity RAM_CTRLR2 is +generic( + tech : integer := 0; + Input_SZ_1 : integer := 16; + Mem_use : integer := use_RAM + +); +port( + reset : in std_logic; + clk : in std_logic; + WD_sel : in std_logic; + Read : in std_logic; + WADDR_sel : in std_logic; + count : in std_logic; + SVG_ADDR : in std_logic; + Write : in std_logic; + GO_0 : in std_logic; + sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); + sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) +); +end RAM_CTRLR2; + + +architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is + +signal WD : std_logic_vector(Input_SZ_1-1 downto 0); +signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0); +signal RD : std_logic_vector(Input_SZ_1-1 downto 0); +signal WEN, REN : std_logic; +signal WADDR_back : std_logic_vector(7 downto 0); +signal WADDR_back_D: std_logic_vector(7 downto 0); +signal RADDR : std_logic_vector(7 downto 0); +signal WADDR : std_logic_vector(7 downto 0); +signal WADDR_D : std_logic_vector(7 downto 0); + + + +begin + +sample_out <= RD(Input_SZ_1-1 downto 0); + + +WEN <= not Write; +REN <= not read; + + +--============================================================== +--=========================R A M================================ +--============================================================== +--memRAM : if Mem_use = use_RAM generate +--RAMblk :RAM +-- port map( +-- WD => WD_D, +-- RD => RD, +-- WEN => WEN, +-- REN => REN, +-- WADDR => WADDR, +-- RADDR => RADDR, +-- RWCLK => clk, +-- RESET => reset +-- ) ; +--end generate; + +--memCEL : if Mem_use = use_CEL generate +--RAMblk :RAM_CEL +-- port map( +-- WD => WD_D, +-- RD => RD, +-- WEN => WEN, +-- REN => REN, +-- WADDR => WADDR, +-- RADDR => RADDR, +-- RWCLK => clk, +-- RESET => reset +-- ) ; +--end generate; + + SRAM : syncram_2p + generic map(tech,8,Input_SZ_1) + port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D); +--============================================================== +--============================================================== + + +ADDRcntr_inst : ADDRcntr +port map( + clk => clk, + reset => reset, + count => count, + clr => GO_0, + Q => RADDR +); + + + +MUX2_inst1 :MUX2 +generic map(Input_SZ => Input_SZ_1) +port map( + sel => WD_sel, + IN1 => sample_in, + IN2 => RD(Input_SZ_1-1 downto 0), + RES => WD(Input_SZ_1-1 downto 0) +); + + +MUX2_inst2 :MUX2 +generic map(Input_SZ => 8) +port map( + sel => WADDR_sel, + IN1 => WADDR_D, + IN2 => WADDR_back_D, + RES => WADDR +); + + + + +WADDR_backreg :REG +generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2) +port map( + reset => reset, + clk => SVG_ADDR, + D => RADDR, + Q => WADDR_back +); + +WADDR_backreg2 :REG +generic map(size => 8) +port map( + reset => reset, + clk => SVG_ADDR, + D => WADDR_back, + Q => WADDR_back_D +); + +WDRreg :REG +generic map(size => Input_SZ_1) +port map( + reset => reset, + clk => clk, + D => WD(Input_SZ_1-1 downto 0), + Q => WD_D(Input_SZ_1-1 downto 0) +); + + + + +ADDRreg :REG +generic map(size => 8) +port map( + reset => reset, + clk => clk, + D => RADDR, + Q => WADDR_D +); + + + +end ar_RAM_CTRLR2; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd b/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + + + +entity TestbenshMAC is +end TestbenshMAC; + + + + +architecture ar_TestbenshMAC of TestbenshMAC is + + + +constant OP1sz : integer := 16; +constant OP2sz : integer := 12; +--IDLE =00 MAC =01 MULT =10 ADD =11 +constant IDLE : std_logic_vector(1 downto 0) := "00"; +constant MAC : std_logic_vector(1 downto 0) := "01"; +constant MULT : std_logic_vector(1 downto 0) := "10"; +constant ADD : std_logic_vector(1 downto 0) := "11"; + +signal clk : std_logic:='0'; +signal reset : std_logic:='0'; +signal clrMAC : std_logic:='0'; +signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE; +signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); +signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); +signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); + + + + +begin + + +MAC1 : entity LPP_IIR_FILTER.MAC +generic map( + Input_SZ_A => OP1sz, + Input_SZ_B => OP2sz + +) +port map( + clk => clk, + reset => reset, + clr_MAC => clrMAC, + MAC_MUL_ADD => MAC_MUL_ADD, + OP1 => Operand1, + OP2 => Operand2, + RES => Resultat +); + +clk <= not clk after 25 ns; + +process +begin +wait for 40 ns; +reset <= '1'; +wait for 11 ns; +Operand1 <= X"0001"; +Operand2 <= X"001"; +MAC_MUL_ADD <= ADD; +wait for 50 ns; +Operand1 <= X"0001"; +Operand2 <= X"100"; +wait for 50 ns; +Operand1 <= X"0001"; +Operand2 <= X"001"; +MAC_MUL_ADD <= MULT; +wait for 50 ns; +Operand1 <= X"0002"; +Operand2 <= X"002"; +wait for 50 ns; +clrMAC <= '1'; +wait for 50 ns; +clrMAC <= '0'; +Operand1 <= X"0001"; +Operand2 <= X"003"; +MAC_MUL_ADD <= MAC; +wait; +end process; +end ar_TestbenshMAC; + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd b/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -0,0 +1,232 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; + + + + +package iir_filter is + + +--===========================================================| +--================A L U C O N T R O L======================| +--===========================================================| +constant IDLE : std_logic_vector(3 downto 0) := "0000"; +constant MAC_op : std_logic_vector(3 downto 0) := "0001"; +constant MULT : std_logic_vector(3 downto 0) := "0010"; +constant ADD : std_logic_vector(3 downto 0) := "0011"; +constant clr_mac : std_logic_vector(3 downto 0) := "0100"; + +--____ +--RAM | +--____| +constant use_RAM : integer := 1; +constant use_CEL : integer := 0; + + +--===========================================================| +--=============C O E F S ====================================| +--===========================================================| +-- create a specific type of data for coefs to avoid errors | +--===========================================================| + +type scaleValT is array(natural range <>) of integer; + +type samplT is array(natural range <>,natural range <>) of std_logic; + +type in_IIR_CEL_reg is record + config : std_logic_vector(31 downto 0); + virgPos : std_logic_vector(4 downto 0); +end record; + +type out_IIR_CEL_reg is record + config : std_logic_vector(31 downto 0); + status : std_logic_vector(31 downto 0); +end record; + + + +component APB_IIR_CEL is + generic ( + tech : integer := 0; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 6; + Cels_count : integer := 5; + virgPos : integer := 3; + Mem_use : integer := use_RAM + ); + port ( + rst : in std_logic; + clk : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + sample_clk : in std_logic; + sample_clk_out : out std_logic; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1') + ); +end component; + + +--component FILTER is +--generic(Smpl_SZ : integer := 16; +-- ChanelsCNT : integer := 3 +--); +--port( +-- +-- reset : in std_logic; +-- clk : in std_logic; +-- sample_clk : in std_logic; +-- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); +-- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) +--); +--end component; + + + +--component FilterCTRLR is +--port( +-- reset : in std_logic; +-- clk : in std_logic; +-- sample_clk : in std_logic; +-- ALU_Ctrl : out std_logic_vector(3 downto 0); +-- sample_in : in samplT; +-- coef : out std_logic_vector(Coef_SZ-1 downto 0); +-- sample : out std_logic_vector(Smpl_SZ-1 downto 0) +--); +--end component; + + +--component FILTER_RAM_CTRLR is +--port( +-- reset : in std_logic; +-- clk : in std_logic; +-- run : in std_logic; +-- GO_0 : in std_logic; +-- B_A : in std_logic; +-- writeForce : in std_logic; +-- next_blk : in std_logic; +-- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); +-- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) +--); +--end component; + + +component IIR_CEL_CTRLR is +generic( + tech : integer := 0; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 3; + Cels_count : integer := 5; + Mem_use : integer := use_RAM +); +port( + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + virg_pos : in integer; + coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) +); +end component; + + +component RAM is + port( WD : in std_logic_vector(35 downto 0); RD : out + std_logic_vector(35 downto 0);WEN, REN : in std_logic; + WADDR : in std_logic_vector(7 downto 0); RADDR : in + std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic + ) ; +end component; + + +component RAM_CEL is + port( WD : in std_logic_vector(35 downto 0); RD : out + std_logic_vector(35 downto 0);WEN, REN : in std_logic; + WADDR : in std_logic_vector(7 downto 0); RADDR : in + std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic + ) ; +end component; + +component IIR_CEL_FILTER is +generic( + tech : integer := 0; + Sample_SZ : integer := 16; + ChanelsCount : integer := 1; + Coef_SZ : integer := 9; + CoefCntPerCel: integer := 3; + Cels_count : integer := 5; + Mem_use : integer := use_RAM); +port( + reset : in std_logic; + clk : in std_logic; + sample_clk : in std_logic; + regs_in : in in_IIR_CEL_reg; + regs_out : in out_IIR_CEL_reg; + sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); + coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) + +); +end component; + + +component RAM_CTRLR2 is +generic( + tech : integer := 0; + Input_SZ_1 : integer := 16; + Mem_use : integer := use_RAM +); +port( + reset : in std_logic; + clk : in std_logic; + WD_sel : in std_logic; + Read : in std_logic; + WADDR_sel : in std_logic; + count : in std_logic; + SVG_ADDR : in std_logic; + Write : in std_logic; + GO_0 : in std_logic; + sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); + sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) +); +end component; + + +end; diff --git a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd @@ -0,0 +1,155 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Driver_FFT is +generic( + Data_sz : integer range 1 to 32 := 16 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Load : in std_logic; + Empty : in std_logic_vector(4 downto 0); + Full : in std_logic_vector(4 downto 0); + DATA : in std_logic_vector((5*Data_sz)-1 downto 0); + Valid : out std_logic; + Read : out std_logic_vector(4 downto 0); + Data_re : out std_logic_vector(Data_sz-1 downto 0); + Data_im : out std_logic_vector(Data_sz-1 downto 0) +); +end entity; + + +architecture ar_Driver of Driver_FFT is + +type etat is (eX,e0,e1,e2); +signal ect : etat; + +signal FifoCpt : integer; +--signal DataTmp : std_logic_vector(Data_sz-1 downto 0); + +signal sEmpty : std_logic; +signal sFull : std_logic; +signal sData : std_logic_vector(Data_sz-1 downto 0); + +begin + + process(clk,rstn) + begin + if(rstn='0')then + ect <= eX; + Read <= (others => '1'); + Valid <= '0'; + FifoCpt <= 1; + + elsif(clk'event and clk='1')then + + case ect is + + when eX => + if(sFull='1')then + ect <= e0; + end if; + + when e0 => + Valid <= '0'; + if(Load='1' and sEmpty='0')then + Read(FifoCpt-1) <= '0'; + ect <= e2; +-- ect <= e1; + elsif(sEmpty='1')then + if(FifoCpt=6)then + FifoCpt <= 1; + else + FifoCpt <= FifoCpt+1; + end if; + ect <= eX; + end if; + + when e1 => + null; +-- DataTmp <= sData; +-- ect <= e2; + + when e2 => + Read(FifoCpt-1) <= '1'; + Data_re <= sData; + Data_im <= (others => '0'); +-- Data_re <= DataTmp; +-- Data_im <= sData; + Valid <= '1'; + ect <= e0; + + + end case; + end if; + end process; + +with FifoCpt select + sFull <= Full(0) when 1, + Full(1) when 2, + Full(2) when 3, + Full(3) when 4, + Full(4) when 5, + '1' when others; + +with FifoCpt select + sEmpty <= Empty(0) when 1, + Empty(1) when 2, + Empty(2) when 3, + Empty(3) when 4, + Empty(4) when 5, + '1' when others; + +with FifoCpt select + sData <= DATA(Data_sz-1 downto 0) when 1, + DATA((2*Data_sz)-1 downto Data_sz) when 2, + DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3, + DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4, + DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5, + (others => '0') when others; + +end architecture; + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Linker_FFT is +generic( + Data_sz : integer range 1 to 32 := 8 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Ready : in std_logic; + Valid : in std_logic; + Full : in std_logic_vector(4 downto 0); + Data_re : in std_logic_vector(Data_sz-1 downto 0); + Data_im : in std_logic_vector(Data_sz-1 downto 0); + Read : out std_logic; + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + DATA : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end entity; + + +architecture ar_Linker of Linker_FFT is + +type etat is (eX,e0,e1,e2,e3); +signal ect : etat; + +signal FifoCpt : integer; +signal DataTmp : std_logic_vector(Data_sz-1 downto 0); + +signal sFull : std_logic; +signal sData : std_logic_vector(Data_sz-1 downto 0); +signal sReady : std_logic; + +begin + + process(clk,rstn) + begin + if(rstn='0')then + ect <= e0; + Read <= '0'; + Write <= (others => '1'); + Reuse <= (others => '0'); + FifoCpt <= 1; + sDATA <= (others => '0'); + + elsif(clk'event and clk='1')then + sReady <= Ready; + + case ect is + + when e0 => + Write(FifoCpt-1) <= '1'; + if(sReady='0' and Ready='1' and sfull='0')then + Read <= '1'; + ect <= e1; + end if; + + when e1 => + Read <= '0'; + if(Valid='1' and sfull='0')then + DataTmp <= Data_im; + sDATA <= Data_re; + Write(FifoCpt-1) <= '0'; + ect <= e2; + elsif(sfull='1')then + ReUse(FifoCpt-1) <= '1'; + ect <= eX; + end if; + + when e2 => + sDATA <= DataTmp; + ect <= e3; + + when e3 => + Write(FifoCpt-1) <= '1'; + if(Ready='1' and sfull='0')then + Read <= '1'; + ect <= e1; + end if; + + when eX => + if(FifoCpt=5)then + FifoCpt <= 1; + else + FifoCpt <= FifoCpt+1; + end if; + ect <= e0; + + end case; + end if; + end process; + +DATA <= sData & sData & sData & sData & sData; + +with FifoCpt select + sFull <= Full(0) when 1, + Full(1) when 2, + Full(2) when 3, + Full(3) when 4, + Full(4) when 5, + '1' when others; + + +end architecture; + diff --git a/lib/lpp/dsp/lpp_fft/Linker_FFT_FIFO.vhd b/lib/lpp/dsp/lpp_fft/Linker_FFT_FIFO.vhd deleted file mode 100644 --- a/lib/lpp/dsp/lpp_fft/Linker_FFT_FIFO.vhd +++ /dev/null @@ -1,131 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity Linker_FFT_FIFO is -generic( - Data_sz : integer range 1 to 32 := 8 - ); -port( - clk : in std_logic; - rstn : in std_logic; - Ready : in std_logic; - Valid : in std_logic; - Full : in std_logic_vector(4 downto 0); - Data_re : in std_logic_vector(Data_sz-1 downto 0); - Data_im : in std_logic_vector(Data_sz-1 downto 0); - Read : out std_logic; - Write : out std_logic_vector(4 downto 0); - ReUse : out std_logic_vector(4 downto 0); - DATA : out std_logic_vector((5*Data_sz)-1 downto 0) -); -end entity; - - -architecture ar_Linker of Linker_FFT_FIFO is - -type etat is (eX,e0,e1,e2,e3); -signal ect : etat; - -signal FifoCpt : integer; -signal DataTmp : std_logic_vector(Data_sz-1 downto 0); - -signal sFull : std_logic; -signal sData : std_logic_vector(Data_sz-1 downto 0); -signal sReady : std_logic; - -begin - - process(clk,rstn) - begin - if(rstn='0')then - ect <= e0; - Read <= '1'; - Write <= (others => '1'); - Reuse <= (others => '0'); - FifoCpt <= 1; - sDATA <= (others => '0'); - - elsif(clk'event and clk='1')then - sReady <= Ready; - - case ect is - - when e0 => - Write(FifoCpt-1) <= '1'; - if(sReady='0' and Ready='1' and sfull='0')then - Read <= '0'; - ect <= e1; - end if; - - when e1 => - Read <= '1'; - if(Valid='1' and sfull='0')then - DataTmp <= Data_im; - sDATA <= Data_re; - Write(FifoCpt-1) <= '0'; - ect <= e2; - elsif(sfull='1')then - ReUse(FifoCpt-1) <= '1'; - ect <= eX; - end if; - - when e2 => - sDATA <= DataTmp; - ect <= e3; - - when e3 => - Write(FifoCpt-1) <= '1'; - if(Ready='1' and sfull='0')then - Read <= '0'; - ect <= e1; - end if; - - when eX => - if(FifoCpt=6)then - FifoCpt <= 1; - else - FifoCpt <= FifoCpt+1; - end if; - ect <= e0; - - end case; - end if; - end process; - -DATA <= sData & sData & sData & sData & sData; - -with FifoCpt select - sFull <= Full(0) when 1, - Full(1) when 2, - Full(2) when 3, - Full(3) when 4, - Full(4) when 5, - '1' when others; - -end architecture; - - - - diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -87,7 +87,7 @@ component Flag_Extremum is end component; -component Linker_FFT_FIFO is +component Linker_FFT is generic( Data_sz : integer range 1 to 32 := 16 ); @@ -106,6 +106,25 @@ port( ); end component; + +component Driver_FFT is +generic( + Data_sz : integer range 1 to 32 := 16 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Load : in std_logic; + Empty : in std_logic_vector(4 downto 0); + Full : in std_logic_vector(4 downto 0); + DATA : in std_logic_vector((5*Data_sz)-1 downto 0); + Valid : out std_logic; + Read : out std_logic_vector(4 downto 0); + Data_re : out std_logic_vector(Data_sz-1 downto 0); + Data_im : out std_logic_vector(Data_sz-1 downto 0) +); +end component; + --==============================================================| --================== IP VHDL de la FFT actel ===================| --================ non partag� dans la VHD_Lib =================| diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd @@ -25,7 +25,6 @@ library lpp; use lpp.lpp_ad_conv.all; use lpp.general_purpose.Clk_divider; - --! \brief AD7688 driver, generates all needed signal to drive this ADC. --! --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr @@ -37,8 +36,9 @@ generic( ); Port( clk : in STD_LOGIC; --! System clock - reset : in STD_LOGIC; --! System reset - smplClk : in STD_LOGIC; --! Sampling clock + rstn : in STD_LOGIC; --! System reset + enable : in std_logic; --! Negative enable + smplClk : in STD_LOGIC; --! Sampling clock DataReady : out std_logic; --! New sample available smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv @@ -52,13 +52,15 @@ constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs signal i : integer range 0 to convTrigger :=0; signal clk_int : std_logic; +signal clk_int_inv : std_logic; signal smplClk_reg : std_logic; signal cnv_int : std_logic; +signal reset : std_logic; begin clkdiv: if clkkHz>=66000 generate - clkdivider: Clk_divider + clkdivider: entity work.Clk_divider generic map(clkkHz*1000,60000000) Port map( clk ,reset,clk_int); end generate; @@ -67,9 +69,11 @@ clknodiv: if clkkHz<66000 generate nodiv: clk_int <= clk; end generate; +clk_int_inv <= not clk_int; + AD_out.CNV <= cnv_int; AD_out.SCK <= clk_int; - +reset <= rstn and enable; sckgen: process(clk,reset) begin @@ -95,9 +99,9 @@ end process; -spidrvr: AD7688_spi_if +spidrvr: entity work.AD7688_spi_if generic map(ChanelCount) - Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout); + Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout); diff --git a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd @@ -1,78 +1,78 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library lpp; -use lpp.lpp_ad_conv.all; -use lpp.general_purpose.Clk_divider; - -entity AD7688_spi_if is - generic(ChanelCount : integer); - Port( clk : in STD_LOGIC; - reset : in STD_LOGIC; - cnv : in STD_LOGIC; - DataReady: out std_logic; - sdi : in AD7688_in(ChanelCount-1 downto 0); - smpout : out Samples_out(ChanelCount-1 downto 0) - ); -end AD7688_spi_if; - -architecture ar_AD7688_spi_if of AD7688_spi_if is - -signal shift_reg : Samples_out(ChanelCount-1 downto 0); -signal i : integer range 0 to 15 :=0; -signal cnv_reg : std_logic := '0'; - -begin - - - -process(clk,reset) -begin - if reset = '0' then - for l in 0 to ChanelCount-1 loop - shift_reg(l) <= (others => '0'); - end loop; - i <= 0; - cnv_reg <= '0'; - elsif clk'event and clk = '1' then - if cnv = '0' and cnv_reg = '0' then - if i = 15 then - i <= 0; - cnv_reg <= '1'; - else - DataReady <= '0'; - i <= i+1; - for l in 0 to ChanelCount-1 loop - shift_reg(l)(0) <= sdi(l).SDI; - shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0); - end loop; - end if; - else - cnv_reg <= not cnv; - smpout <= shift_reg; - DataReady <= '1'; - end if; - end if; -end process; - -end ar_AD7688_spi_if; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.general_purpose.Clk_divider; + +entity AD7688_spi_if is + generic(ChanelCount : integer); + Port( clk : in STD_LOGIC; + reset : in STD_LOGIC; + cnv : in STD_LOGIC; + DataReady : out std_logic; + sdi : in AD7688_in(ChanelCount-1 downto 0); + smpout : out Samples_out(ChanelCount-1 downto 0) + ); +end AD7688_spi_if; + +architecture ar_AD7688_spi_if of AD7688_spi_if is + +signal shift_reg : Samples_out(ChanelCount-1 downto 0); +signal i : integer range 0 to 16 :=0; +signal cnv_reg : std_logic := '0'; + +begin + + + +process(clk,reset) +begin + if reset = '0' then + for l in 0 to ChanelCount-1 loop + shift_reg(l) <= (others => '0'); + end loop; + i <= 0; + cnv_reg <= '0'; + elsif clk'event and clk = '1' then + if cnv = '0' and cnv_reg = '0' then + if i = 16 then + i <= 0; + cnv_reg <= '1'; + else + DataReady <= '0'; + i <= i+1; + for l in 0 to ChanelCount-1 loop + shift_reg(l)(0) <= sdi(l).SDI; + shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0); + end loop; + end if; + else + cnv_reg <= not cnv; + smpout <= shift_reg; + DataReady <= '1'; + end if; + end if; +end process; + +end ar_AD7688_spi_if; diff --git a/lib/lpp/lpp_ad_Conv/WriteGen_ADC.vhd b/lib/lpp/lpp_ad_Conv/WriteGen_ADC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/WriteGen_ADC.vhd @@ -0,0 +1,83 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity WriteGen_ADC is + port( + clk : in std_logic; + rstn : in std_logic; + SmplCLK : in std_logic; + DataReady : in std_logic; + Full : in std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0) + ); +end entity; + + +architecture ar_WG of WriteGen_ADC is + +type etat is (e0,e1,eX); +signal ect : etat; + +signal ReUse_reg : std_logic_vector(4 downto 0); + +begin + + process(clk,rstn) + begin + if(rstn='0')then + ect <= e0; + ReUse_reg <= (others => '0'); + write <= (others => '1'); + + elsif(clk'event and clk='1')then + ReUse_reg <= Full or ReUse_reg; + + case ect is + + when e0 => + if(DataReady='0' and SmplCLK='1')then + ect <= e1; + end if; + + when e1 => + if(DataReady='1')then + Write <= Full; + ect <= eX; + end if; + + when eX => + write <= (others => '1'); + ect <= e0; + + end case; + end if; + end process; + + +ReUse <= ReUse_reg; + +end architecture; + diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -54,7 +54,8 @@ package lpp_ad_conv is generic(ChanelCount : integer; clkkHz : integer); Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; + rstn : in STD_LOGIC; + enable : in std_logic; smplClk: in STD_LOGIC; DataReady : out std_logic; smpout : out Samples_out(ChanelCount-1 downto 0); @@ -68,7 +69,7 @@ component AD7688_spi_if is Port( clk : in STD_LOGIC; reset : in STD_LOGIC; cnv : in STD_LOGIC; - DataReady: out std_logic; + DataReady: out std_logic; sdi : in AD7688_in(ChanelCount-1 downto 0); smpout : out Samples_out(ChanelCount-1 downto 0) ); @@ -100,7 +101,7 @@ component ADS7886_drvr is clkkHz : integer); Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; + reset : in STD_LOGIC; smplClk : in STD_LOGIC; DataReady : out std_logic; smpout : out Samples_out(ChanelCount-1 downto 0); @@ -109,6 +110,17 @@ component ADS7886_drvr is ); end component; +component WriteGen_ADC is + port( + clk : in std_logic; + rstn : in std_logic; + SmplCLK : in std_logic; + DataReady : in std_logic; + Full : in std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0) + ); +end component; end lpp_ad_conv; diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -14,7 +14,7 @@ -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr @@ -54,7 +54,8 @@ generic ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant rclk : in std_logic; - wclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide @@ -103,7 +104,8 @@ signal sRDATA : fifodatabus; signal sWDATA : fifodatabus; signal sWADDR : fifoaddressbus; signal sRADDR : fifoaddressbus; -signal ReUse : std_logic_vector(FifoCnt-1 downto 0); --27/01/12 +signal sReUse : std_logic_vector(FifoCnt-1 downto 0); --05/06/12 +signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); --05/06/12 type state_t is (idle,Read); signal fiforeadfsmst : state_t; @@ -118,6 +120,7 @@ FIFO_ID(23 downto 16) <= std_logic_vecto Write : if W /= 0 generate FIFO_ID(4) <= '1'; sWen <= sWen_APB; + sReUse <= sReUse_APB; sWclk <= clk; Wrapb: for i in 0 to FifoCnt-1 generate sWDATA(i) <= Rec(i).FIFO_Wdata; @@ -127,6 +130,7 @@ end generate; Writeext : if W = 0 generate FIFO_ID(4) <= '0'; sWen <= WEN; + sReUse <= ReUse; sWclk <= Wclk; Wrext: for i in 0 to FifoCnt-1 generate sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); @@ -156,7 +160,7 @@ ctrlregs: for i in 0 to FifoCnt-1 genera WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); Rec(i).FIFO_Ctrl(16) <= sFull(i); --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12 - ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12 + sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); @@ -170,7 +174,7 @@ Full <= sFull; fifos: for i in 0 to FifoCnt-1 generate FIFO0 : lpp_fifo generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); + port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); end generate; process(rst,clk) diff --git a/lib/lpp/lpp_memory/SM_5lppFIFO.vhd b/lib/lpp/lpp_memory/SM_5lppFIFO.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/SM_5lppFIFO.vhd +++ /dev/null @@ -1,103 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_memory.all; -library techmap; -use techmap.gencomp.all; - -entity SM_5lppFIFO is -generic( - tech : integer := apa3; - Data_sz : integer range 1 to 32 := 16; - Addr_sz : integer range 2 to 12 := 8; - Enable_ReUse : std_logic := '0' - ); -port( - rst : in std_logic; - wclk : in std_logic; - rclk : in std_logic; - ReUse : in std_logic_vector(4 downto 0); - wen : in std_logic_vector(4 downto 0); - ren : in std_logic_vector(4 downto 0); - wdata : in std_logic_vector((5*Data_sz)-1 downto 0); - rdata : out std_logic_vector((5*Data_sz)-1 downto 0); - full : out std_logic_vector(4 downto 0); - empty : out std_logic_vector(4 downto 0) -); -end entity; - - -architecture ar_SM_5lppFIFO of SM_5lppFIFO is - -begin - - fifoB1 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open); - - fifoB2 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open); - - fifoB3 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open); - - fifoE1 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open); - - fifoE2 : lpp_fifo - generic map (tech,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open); - - -end architecture; - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_memory/lppFIFOx5.vhd b/lib/lpp/lpp_memory/lppFIFOx5.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lppFIFOx5.vhd @@ -0,0 +1,77 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +--library lpp; +--use lpp.lpp_memory.all; +--library techmap; +--use techmap.gencomp.all; + +entity lppFIFOx5 is +generic( + tech : integer := 0; + Data_sz : integer range 1 to 32 := 8; + Enable_ReUse : std_logic := '0' + ); +port( + rst : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(4 downto 0); + wen : in std_logic_vector(4 downto 0); + ren : in std_logic_vector(4 downto 0); + wdata : in std_logic_vector((5*Data_sz)-1 downto 0); + rdata : out std_logic_vector((5*Data_sz)-1 downto 0); + full : out std_logic_vector(4 downto 0); + empty : out std_logic_vector(4 downto 0) +); +end entity; + + +architecture ar_lppFIFOx5 of lppFIFOx5 is + +begin + + fifoB1 : entity work.lpp_fifo + generic map (tech,Enable_ReUse,Data_sz,8) + port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open); + + fifoB2 : entity work.lpp_fifo + generic map (tech,Enable_ReUse,Data_sz,8) + port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open); + + fifoB3 : entity work.lpp_fifo + generic map (tech,Enable_ReUse,Data_sz,8) + port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open); + + fifoE1 : entity work.lpp_fifo + generic map (tech,Enable_ReUse,Data_sz,8) + port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open); + + fifoE2 : entity work.lpp_fifo + generic map (tech,Enable_ReUse,Data_sz,8) + port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open); + + +end architecture; + diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -55,7 +55,8 @@ generic ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant rclk : in std_logic; - wclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide @@ -94,7 +95,7 @@ port( end component; -component SM_5lppFIFO is +component lppFIFOx5 is generic( tech : integer := 0; Data_sz : integer range 1 to 32 := 16;