HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/LFR-em-WFP_MS/Makefile

Updated LFR EM design....

Updated LFR EM design. Added USES_MBE_PIN generic on Leon3_soc module to set MBE when using IAP's srctrle_0ws and a RAM without MBE.

Alexis Jeandet - - Load All Authors

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        pellion
    
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              r340
            
      VHDLIB=../..

      SCRIPTSDIR=$(VHDLIB)/scripts/

      GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)

      TOP=LFR_em

      BOARD=em-LeonLPP-A3PE3kL-v3-core1

      include $(VHDLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      XSTOPT=

      SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"

      VHDLSYNFILES=LFR-em.vhd

        pellion
    
 - Update files to simulate with questasim...

              r499
            
      VHDLSIMFILES=testbench.vhd

        Alexis Jeandet
    
Updated LFR EM design....

              r651
            
        pellion
    
ADD LPP_CNA (and CAL to LFR-em)

              r531
            
      PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc

        pellion
    
Update SDC constraint for LFR-EM board

              r421
            
        pellion
    
EQM 2.1.67

              r561
            
      SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc

        pellion
    
Update SDC constraint for LFR-EM board

              r421
            
      SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc

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              r340
            
      BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      TECHLIBS = proasic3e

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

        Alexis Jeandet
    
Updated LFR EM design....

              r651
            
      	tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth

        pellion
    
up

              r340
            
      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \

      	./amba_lcd_16x2_ctrlr \

      	./general_purpose/lpp_AMR \

      	./general_purpose/lpp_balise \

      	./general_purpose/lpp_delay \

      	./lpp_bootloader \

        pellion
    
Save

              r399
            
      	./dsp/lpp_fft_rtax \

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              r340
            
      	./lpp_uart \

      	./lpp_usb \

        pellion
    
 - Update files to simulate with questasim...

              r499
            
      	./lpp_sim/CY7C1061DV33 \

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              r340
            
      FILESKIP = i2cmst.vhd \

      	APB_MULTI_DIODE.vhd \

      	APB_MULTI_DIODE.vhd \

      	Top_MatrixSpec.vhd \

        pellion
    
 - Update files to simulate with questasim...

              r499
            
      	APB_FFT.vhd\

      	CoreFFT_simu.vhd \

      	lpp_lfr_apbreg_simu.vhd

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              r340
            
      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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pellion up	r340	VHDLIB=../..
		SCRIPTSDIR=$(VHDLIB)/scripts/
		GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
		TOP=LFR_em
		BOARD=em-LeonLPP-A3PE3kL-v3-core1
		include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
		DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
		QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
		EFFORT=high
		XSTOPT=
		SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
		VHDLSYNFILES=LFR-em.vhd
pellion - Update files to simulate with questasim...	r499	VHDLSIMFILES=testbench.vhd
Alexis Jeandet Updated LFR EM design....	r651
pellion ADD LPP_CNA (and CAL to LFR-em)	r531	PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
pellion Update SDC constraint for LFR-EM board	r421
pellion EQM 2.1.67	r561	SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
pellion Update SDC constraint for LFR-EM board	r421	SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc

pellion up	r340	BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
		CLEAN=soft-clean

		TECHLIBS = proasic3e

		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
Alexis Jeandet Updated LFR EM design....	r651	tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth
pellion up	r340
		DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
		./amba_lcd_16x2_ctrlr \
		./general_purpose/lpp_AMR \
		./general_purpose/lpp_balise \
		./general_purpose/lpp_delay \
		./lpp_bootloader \
pellion Save	r399	./dsp/lpp_fft_rtax \
pellion up	r340	./lpp_uart \
		./lpp_usb \
pellion - Update files to simulate with questasim...	r499	./lpp_sim/CY7C1061DV33 \
pellion up	r340
		FILESKIP = i2cmst.vhd \
		APB_MULTI_DIODE.vhd \
		APB_MULTI_DIODE.vhd \
		Top_MatrixSpec.vhd \
pellion - Update files to simulate with questasim...	r499	APB_FFT.vhd\
		CoreFFT_simu.vhd \
		lpp_lfr_apbreg_simu.vhd
pellion up	r340
		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile

		################## project specific targets ##########################