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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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ENTITY lpp_waveform_fifo_arbiter IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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data_f0_valid : IN STD_LOGIC;
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data_f1_valid : IN STD_LOGIC;
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data_f2_valid : IN STD_LOGIC;
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data_f3_valid : IN STD_LOGIC;
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data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
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---------------------------------------------------------------------------
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ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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---------------------------------------------------------------------------
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time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
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TYPE state_fsm IS (IDLE, T1, T2, D1, D2);
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SIGNAL state : state_fsm;
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SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0);
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SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_ready_to_go : STD_LOGIC;
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SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
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BEGIN
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data_valid_and_ready(0) <= ready(0) AND data_f0_valid;
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data_valid_and_ready(1) <= ready(1) AND data_f1_valid;
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data_valid_and_ready(2) <= ready(2) AND data_f2_valid;
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data_valid_and_ready(3) <= ready(3) AND data_f3_valid;
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data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE
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data_f1 WHEN data_valid_and_ready(1) = '1' ELSE
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data_f2 WHEN data_valid_and_ready(2) = '1' ELSE
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data_f3;
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data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE
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"0010" WHEN data_valid_and_ready(1) = '1' ELSE
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"0100" WHEN data_valid_and_ready(2) = '1' ELSE
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"1000" WHEN data_valid_and_ready(3) = '1' ELSE
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"0000";
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data_ready_to_go <= data_valid_and_ready(0) OR
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data_valid_and_ready(1) OR
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data_valid_and_ready(2) OR
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data_valid_and_ready(3);
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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state <= IDLE;
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data_valid_ack <= (OTHERS => '0');
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data_wen <= (OTHERS => '1');
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time_wen <= (OTHERS => '1');
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data <= (OTHERS => '0');
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data_temp <= (OTHERS => '0');
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time_en_temp <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' THEN
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CASE state IS
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WHEN IDLE =>
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data_valid_ack <= (OTHERS => '0');
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time_wen <= (OTHERS => '1');
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data_wen <= (OTHERS => '1');
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data <= (OTHERS => '0');
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data_temp <= (OTHERS => '0');
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IF data_ready_to_go = '1' THEN
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state <= T1;
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data_valid_ack <= data_valid_selected;
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time_wen <= NOT data_valid_selected;
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time_en_temp <= NOT data_valid_selected;
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data <= data_selected(31 DOWNTO 0);
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data_temp <= data_selected(159 DOWNTO 32);
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END IF;
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WHEN T1 =>
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state <= T2;
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data_valid_ack <= (OTHERS => '0');
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data <= data_temp(31 DOWNTO 0);
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data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
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WHEN T2 =>
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state <= D1;
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time_wen <= (OTHERS => '1');
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data_wen <= time_en_temp;
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data <= data_temp(31 DOWNTO 0);
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data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
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WHEN D1 =>
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state <= D2;
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data <= data_temp(31 DOWNTO 0);
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data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
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WHEN D2 =>
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state <= IDLE;
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data <= data_temp(31 DOWNTO 0);
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data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS;
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END ARCHITECTURE;
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