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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fifo IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
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---------------------------------------------------------------------------
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time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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---------------------------------------------------------------------------
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time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
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SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
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SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
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SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
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SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
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SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL ren : STD_LOGIC;
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SIGNAL wen : STD_LOGIC;
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BEGIN
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SRAM : syncram_2p
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GENERIC MAP(tech, 7, 32)
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PORT MAP(clk, ren, data_addr_r, rdata,
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clk, wen, data_addr_w, wdata);
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ren <= time_mem_ren(3) OR data_mem_ren(3) OR
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time_mem_ren(2) OR data_mem_ren(2) OR
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time_mem_ren(1) OR data_mem_ren(1) OR
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time_mem_ren(0) OR data_mem_ren(0);
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wen <= time_mem_wen(3) OR data_mem_wen(3) OR
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time_mem_wen(2) OR data_mem_wen(2) OR
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time_mem_wen(1) OR data_mem_wen(1) OR
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time_mem_wen(0) OR data_mem_wen(0);
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data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE
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time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE
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time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE
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time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE
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data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
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data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
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data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
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data_mem_addr_r(3);
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data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE
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time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE
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time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE
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time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE
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data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
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data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
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data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
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data_mem_addr_w(3);
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gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE
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lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl
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GENERIC MAP (
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offset => 32*I + 20,
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length => 10,
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enable_ready => '0')
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PORT MAP (
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clk => clk,
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rstn => rstn,
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ren => time_ren(I),
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wen => time_wen(I),
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mem_re => time_mem_ren(I),
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mem_we => time_mem_wen(I),
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mem_addr_ren => time_mem_addr_r(I),
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mem_addr_wen => time_mem_addr_w(I),
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ready => OPEN);
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END GENERATE gen_fifo_ctrl_time;
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gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
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lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
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GENERIC MAP (
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offset => 32*I,
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length => 20,
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enable_ready => '1')
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PORT MAP (
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clk => clk,
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rstn => rstn,
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ren => data_ren(I),
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wen => data_wen(I),
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mem_re => data_mem_ren(I),
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mem_we => data_mem_wen(I),
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mem_addr_ren => data_mem_addr_r(I),
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mem_addr_wen => data_mem_addr_w(I),
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ready => ready(I));
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END GENERATE gen_fifo_ctrl_data;
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END ARCHITECTURE;
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