HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/Validation_FIFO_Shared/run_with_head_reg_lantency_1.do

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

add RTAX post layout constraint

pellion - - Load All Authors

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r543:cacd7252f42c JC


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simu_with_Leon3

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             run_with_head_reg_lantency_1.do
        
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      vcom -quiet  -93  -work work tb_with_head_reg_latency_1.vhd

      vsim work.testbench

      log -r *

      do wave_head_reg_latency_1.do

      run -all

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				vcom -quiet -93 -work work tb_with_head_reg_latency_1.vhd

				vsim work.testbench

				log -r *

				do wave_head_reg_latency_1.do

				run -all