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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.spacewire.ALL; -- PLE
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.lpp_lfr_time_management.ALL;
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USE lpp.lpp_leon3_soc_pkg.ALL;
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ENTITY leon3_soc IS
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GENERIC (
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fabtech : INTEGER := apa3e;
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memtech : INTEGER := apa3e;
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padtech : INTEGER := inferred;
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clktech : INTEGER := inferred;
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disas : INTEGER := 0; -- Enable disassembly to console
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dbguart : INTEGER := 0; -- Print UART on console
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pclow : INTEGER := 2;
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--
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clk_freq : INTEGER := 25000; --kHz
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--
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NB_CPU : INTEGER := 1;
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ENABLE_FPU : INTEGER := 1;
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FPU_NETLIST : INTEGER := 1;
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ENABLE_DSU : INTEGER := 1;
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ENABLE_AHB_UART : INTEGER := 1;
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ENABLE_APB_UART : INTEGER := 1;
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ENABLE_IRQMP : INTEGER := 1;
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ENABLE_GPT : INTEGER := 1;
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--
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NB_AHB_MASTER : INTEGER := 0;
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NB_AHB_SLAVE : INTEGER := 0;
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NB_APB_SLAVE : INTEGER := 0;
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--
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ADDRESS_SIZE : INTEGER := 20
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);
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PORT (
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clk : IN STD_ULOGIC;
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reset : IN STD_ULOGIC;
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errorn : OUT STD_ULOGIC;
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-- UART AHB ---------------------------------------------------------------
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ahbrxd : IN STD_ULOGIC; -- DSU rx data
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ahbtxd : OUT STD_ULOGIC; -- DSU tx data
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-- UART APB ---------------------------------------------------------------
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urxd1 : IN STD_ULOGIC; -- UART1 rx data
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utxd1 : OUT STD_ULOGIC; -- UART1 tx data
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-- RAM --------------------------------------------------------------------
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address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
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data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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nSRAM_BE0 : OUT STD_LOGIC;
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nSRAM_BE1 : OUT STD_LOGIC;
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nSRAM_BE2 : OUT STD_LOGIC;
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nSRAM_BE3 : OUT STD_LOGIC;
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nSRAM_WE : OUT STD_LOGIC;
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nSRAM_CE : OUT STD_LOGIC;
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nSRAM_OE : OUT STD_LOGIC;
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-- APB --------------------------------------------------------------------
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apbi_ext : OUT apb_slv_in_type;
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apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
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-- AHB_Slave --------------------------------------------------------------
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ahbi_s_ext : OUT ahb_slv_in_type;
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ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
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-- AHB_Master -------------------------------------------------------------
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ahbi_m_ext : OUT AHB_Mst_In_Type;
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ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
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);
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END;
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ARCHITECTURE Behavioral OF leon3_soc IS
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-----------------------------------------------------------------------------
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-- CONFIG -------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Clock generator
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constant CFG_CLKMUL : integer := (1);
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constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
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constant CFG_OCLKDIV : integer := (1);
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constant CFG_CLK_NOFB : integer := 0;
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-- LEON3 processor core
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constant CFG_LEON3 : integer := 1;
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constant CFG_NCPU : integer := NB_CPU;
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constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
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constant CFG_V8 : integer := 0;
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constant CFG_MAC : integer := 0;
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constant CFG_SVT : integer := 0;
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constant CFG_RSTADDR : integer := 16#00000#;
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constant CFG_LDDEL : integer := (1);
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constant CFG_NWP : integer := (0);
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constant CFG_PWD : integer := 1*2;
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constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
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-- 1*(8 + 16 * 0) => grfpu-light
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-- 1*(8 + 16 * 1) => netlist
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-- 0*(8 + 16 * 0) => No FPU
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-- 0*(8 + 16 * 1) => No FPU;
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constant CFG_ICEN : integer := 1;
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constant CFG_ISETS : integer := 1;
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constant CFG_ISETSZ : integer := 4;
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constant CFG_ILINE : integer := 4;
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constant CFG_IREPL : integer := 0;
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constant CFG_ILOCK : integer := 0;
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constant CFG_ILRAMEN : integer := 0;
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constant CFG_ILRAMADDR: integer := 16#8E#;
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constant CFG_ILRAMSZ : integer := 1;
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constant CFG_DCEN : integer := 1;
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constant CFG_DSETS : integer := 1;
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constant CFG_DSETSZ : integer := 4;
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constant CFG_DLINE : integer := 4;
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constant CFG_DREPL : integer := 0;
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constant CFG_DLOCK : integer := 0;
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constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
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constant CFG_DLRAMEN : integer := 0;
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constant CFG_DLRAMADDR: integer := 16#8F#;
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constant CFG_DLRAMSZ : integer := 1;
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constant CFG_MMUEN : integer := 0;
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constant CFG_ITLBNUM : integer := 2;
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constant CFG_DTLBNUM : integer := 2;
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constant CFG_TLB_TYPE : integer := 1 + 0*2;
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constant CFG_TLB_REP : integer := 1;
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constant CFG_DSU : integer := ENABLE_DSU;
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constant CFG_ITBSZ : integer := 0;
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constant CFG_ATBSZ : integer := 0;
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-- AMBA settings
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constant CFG_DEFMST : integer := (0);
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constant CFG_RROBIN : integer := 1;
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constant CFG_SPLIT : integer := 0;
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constant CFG_AHBIO : integer := 16#FFF#;
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constant CFG_APBADDR : integer := 16#800#;
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-- DSU UART
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constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
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-- LEON2 memory controller
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constant CFG_MCTRL_SDEN : integer := 0;
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-- UART 1
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constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
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constant CFG_UART1_FIFO : integer := 1;
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-- LEON3 interrupt controller
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constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
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-- Modular timer
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constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
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constant CFG_GPT_NTIM : integer := (2);
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constant CFG_GPT_SW : integer := (8);
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constant CFG_GPT_TW : integer := (32);
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constant CFG_GPT_IRQ : integer := (8);
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constant CFG_GPT_SEPIRQ : integer := 1;
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constant CFG_GPT_WDOGEN : integer := 0;
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constant CFG_GPT_WDOG : integer := 16#0#;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SIGNALs
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-----------------------------------------------------------------------------
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CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
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-- CLK & RST --
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SIGNAL clk2x : STD_ULOGIC;
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SIGNAL clkmn : STD_ULOGIC;
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SIGNAL clkm : STD_ULOGIC;
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SIGNAL rstn : STD_ULOGIC;
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SIGNAL rstraw : STD_ULOGIC;
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SIGNAL pciclk : STD_ULOGIC;
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SIGNAL sdclkl : STD_ULOGIC;
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SIGNAL cgi : clkgen_in_type;
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SIGNAL cgo : clkgen_out_type;
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--- AHB / APB
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
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SIGNAL ahbsi : ahb_slv_in_type;
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SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
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SIGNAL ahbmi : ahb_mst_in_type;
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SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
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--UART
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SIGNAL ahbuarti : uart_in_type;
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SIGNAL ahbuarto : uart_out_type;
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SIGNAL apbuarti : uart_in_type;
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SIGNAL apbuarto : uart_out_type;
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--MEM CTRLR
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SIGNAL memi : memory_in_type;
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SIGNAL memo : memory_out_type;
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SIGNAL wpo : wprot_out_type;
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SIGNAL sdo : sdram_out_type;
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--IRQ
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SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
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SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
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--Timer
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SIGNAL gpti : gptimer_in_type;
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SIGNAL gpto : gptimer_out_type;
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--DSU
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SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
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SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
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SIGNAL dsui : dsu_in_type;
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SIGNAL dsuo : dsu_out_type;
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-----------------------------------------------------------------------------
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SIGNAL nSRAM_CE_s : STD_LOGIC;
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BEGIN
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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cgi.pllctrl <= "00";
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cgi.pllrst <= rstraw;
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rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
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clkgen0 : clkgen -- clock generator
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GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
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PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
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----------------------------------------------------------------------
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--- LEON3 processor / DSU / IRQ ------------------------------------
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----------------------------------------------------------------------
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l3 : IF CFG_LEON3 = 1 GENERATE
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cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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u0 : leon3s -- LEON3 processor
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GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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END GENERATE;
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errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
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dsugen : IF CFG_DSU = 1 GENERATE
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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dsui.break <= '0';
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END GENERATE;
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END GENERATE;
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nodsu : IF CFG_DSU = 0 GENERATE
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ahbso(2) <= ahbs_none;
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dsuo.tstop <= '0';
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dsuo.active <= '0';
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END GENERATE;
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irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
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irqctrl0 : irqmp -- interrupt controller
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GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
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END GENERATE;
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irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
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x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
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irqi(i).irl <= "0000";
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END GENERATE;
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apbo(2) <= apb_none;
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END GENERATE;
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----------------------------------------------------------------------
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--- Memory controllers ---------------------------------------------
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----------------------------------------------------------------------
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memctrlr : mctrl GENERIC MAP (
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hindex => 0,
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pindex => 0,
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paddr => 0,
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srbanks => 1
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)
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PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
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memi.brdyn <= '1';
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memi.bexcn <= '1';
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memi.writen <= '1';
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memi.wrn <= "1111";
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memi.bwidth <= "10";
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bdr : FOR i IN 0 TO 3 GENERATE
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data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
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PORT MAP (
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data(31-i*8 DOWNTO 24-i*8),
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memo.data(31-i*8 DOWNTO 24-i*8),
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memo.bdrive(i),
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memi.data(31-i*8 DOWNTO 24-i*8));
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END GENERATE;
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addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
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PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
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nSRAM_CE_s <= NOT(memo.ramsn(0));
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rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
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oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
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nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
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nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
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nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
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nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
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nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
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----------------------------------------------------------------------
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--- AHB CONTROLLER -------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => 0, nahbm => maxahbmsp, nahbs => 8)
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PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- AHB UART -------------------------------------------------------
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----------------------------------------------------------------------
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dcomgen : IF CFG_AHB_UART = 1 GENERATE
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dcom0 : ahbuart
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GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
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PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
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dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
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dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
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END GENERATE;
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nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
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|
|
|
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----------------------------------------------------------------------
|
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|
--- APB Bridge -----------------------------------------------------
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|
----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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|
GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
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|
PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
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|
|
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----------------------------------------------------------------------
|
|
|
--- GPT Timer ------------------------------------------------------
|
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|
----------------------------------------------------------------------
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gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
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timer0 : gptimer -- timer unit
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GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
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sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
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nbits => CFG_GPT_TW)
|
|
|
PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
|
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|
gpti.dhalt <= dsuo.tstop;
|
|
|
gpti.extclk <= '0';
|
|
|
END GENERATE;
|
|
|
notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
|
|
|
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
|
|
|
uart1 : apbuart -- UART 1
|
|
|
GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
|
|
|
apbuarti.rxd <= urxd1;
|
|
|
apbuarti.extclk <= '0';
|
|
|
utxd1 <= apbuarto.txd;
|
|
|
apbuarti.ctsn <= '0';
|
|
|
END GENERATE;
|
|
|
noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
|
-- AMBA BUS -------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
-- APB --------------------------------------------------------------------
|
|
|
apbi_ext <= apbi;
|
|
|
all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
|
|
|
max_16_apb: IF I + 5 < 16 GENERATE
|
|
|
apbo(I+5)<= apbo_ext(I+5);
|
|
|
END GENERATE max_16_apb;
|
|
|
END GENERATE all_apb;
|
|
|
-- AHB_Slave --------------------------------------------------------------
|
|
|
ahbi_s_ext <= ahbsi;
|
|
|
all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
|
|
|
max_16_ahbs: IF I + 3 < 16 GENERATE
|
|
|
ahbso(I+3) <= ahbo_s_ext(I+3);
|
|
|
END GENERATE max_16_ahbs;
|
|
|
END GENERATE all_ahbs;
|
|
|
-- AHB_Master -------------------------------------------------------------
|
|
|
ahbi_m_ext <= ahbmi;
|
|
|
all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
|
|
|
max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
|
|
|
ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
|
|
|
END GENERATE max_16_ahbm;
|
|
|
END GENERATE all_ahbm;
|
|
|
|
|
|
|
|
|
|
|
|
END Behavioral;
|
|
|
|
