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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_demux.ALL;
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USE lpp.lpp_fft.ALL;
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USE lpp.lpp_matrix.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_top_lfr IS
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GENERIC(
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tech : INTEGER := 0;
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hindex_SpectralMatrix : INTEGER := 2;
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pindex : INTEGER := 4;
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paddr : INTEGER := 4;
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pmask : INTEGER := 16#fff#;
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pirq : INTEGER := 0
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);
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PORT (
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-- ADS7886
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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--
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cnv_clk : IN STD_LOGIC; -- 49 MHz
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cnv_rstn : IN STD_LOGIC;
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--
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clk : IN STD_LOGIC; -- 25 MHz
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rstn : IN STD_LOGIC;
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--
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- AMBA AHB Master Interface
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AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
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AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
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-- Time
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coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
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fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
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);
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END lpp_top_lfr;
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ARCHITECTURE tb OF lpp_top_lfr IS
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-----------------------------------------------------------------------------
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-- f0
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SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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--
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SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- f1
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SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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--
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SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- f2
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SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- f3
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SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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--
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SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- SPECTRAL MATRIX
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-----------------------------------------------------------------------------
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SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
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SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fifo_empty : STD_LOGIC;
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SIGNAL fifo_ren : STD_LOGIC;
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SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_val : STD_LOGIC;
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SIGNAL header_ack : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- APB REG
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-----------------------------------------------------------------------------
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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CONSTANT nb_snapshot_param_size : INTEGER := 11;
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CONSTANT delta_snapshot_size : INTEGER := 16;
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CONSTANT delta_f2_f0_size : INTEGER := 10;
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CONSTANT delta_f2_f1_size : INTEGER := 10;
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SIGNAL waveform_enable_f0 : STD_LOGIC;
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SIGNAL waveform_enable_f1 : STD_LOGIC;
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SIGNAL waveform_enable_f2 : STD_LOGIC;
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SIGNAL waveform_enable_f3 : STD_LOGIC;
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SIGNAL waveform_burst_f0 : STD_LOGIC;
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SIGNAL waveform_burst_f1 : STD_LOGIC;
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SIGNAL waveform_burst_f2 : STD_LOGIC;
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SIGNAL waveform_nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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SIGNAL waveform_delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
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SIGNAL waveform_delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
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SIGNAL waveform_delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
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SIGNAL data_f0_in_valid : STD_LOGIC;
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SIGNAL data_f0_in_valid_r : STD_LOGIC;
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SIGNAL data_f1_in_valid : STD_LOGIC;
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SIGNAL data_f2_in_valid : STD_LOGIC;
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SIGNAL data_f3_in_valid : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- CNA + FILTER
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-----------------------------------------------------------------------------
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lpp_top_acq_1 : lpp_top_acq
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GENERIC MAP (
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tech => tech)
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PORT MAP (
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cnv_run => cnv_run,
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cnv => cnv,
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sck => sck,
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sdo => sdo,
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cnv_clk => cnv_clk,
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cnv_rstn => cnv_rstn,
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clk => clk,
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rstn => rstn,
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sample_f0_wen => sample_f0_wen,
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sample_f0_wdata => sample_f0_wdata,
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sample_f1_wen => sample_f1_wen,
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sample_f1_wdata => sample_f1_wdata,
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sample_f2_wen => sample_f2_wen,
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sample_f2_wdata => sample_f2_wdata,
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sample_f3_wen => sample_f3_wen,
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sample_f3_wdata => sample_f3_wdata);
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-----------------------------------------------------------------------------
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-- FIFO
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-----------------------------------------------------------------------------
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lppFIFO_f0 : lppFIFOxN
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GENERIC MAP (
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tech => tech,
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Data_sz => 16,
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FifoCnt => 5,
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Enable_ReUse => '0')
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PORT MAP (
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rst => rstn,
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wclk => clk,
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rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f0_wen,
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ren => sample_f0_ren,
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wdata => sample_f0_wdata,
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rdata => sample_f0_rdata,
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full => sample_f0_full,
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empty => sample_f0_empty);
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lppFIFO_f1 : lppFIFOxN
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GENERIC MAP (
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tech => tech,
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Data_sz => 16,
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FifoCnt => 5,
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Enable_ReUse => '0')
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PORT MAP (
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rst => rstn,
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wclk => clk,
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rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f1_wen,
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ren => sample_f1_ren,
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wdata => sample_f1_wdata,
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rdata => sample_f1_rdata,
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full => sample_f1_full,
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empty => sample_f1_empty);
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lppFIFO_f2 : lppFIFOxN
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GENERIC MAP (
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tech => tech,
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Data_sz => 16,
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FifoCnt => 5,
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Enable_ReUse => '0')
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PORT MAP (
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rst => rstn,
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wclk => clk,
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rclk => clk,
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ReUse => (OTHERS => '0'),
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wen => sample_f2_wen,
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ren => sample_f2_ren,
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wdata => sample_f2_wdata,
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rdata => sample_f2_rdata,
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full => sample_f2_full,
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empty => sample_f2_empty);
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-----------------------------------------------------------------------------
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-- SPECTRAL MATRIX
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-----------------------------------------------------------------------------
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--sample_f0_ren <= sample_ren(4 DOWNTO 0);
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--sample_f1_ren <= sample_ren(14 DOWNTO 10);
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--sample_f2_ren <= sample_ren(19 DOWNTO 15);
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--Demultiplex_1 : Demultiplex
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-- GENERIC MAP (
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-- Data_sz => 16)
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-- PORT MAP (
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-- clk => clk,
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-- rstn => rstn,
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-- Read => demux_ren,
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-- EmptyF0a => sample_f0_0_empty,
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-- EmptyF0b => sample_f0_0_empty,
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-- EmptyF1 => sample_f1_empty,
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-- EmptyF2 => sample_f3_empty,
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-- DataF0a => sample_f0_0_rdata,
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-- DataF0b => sample_f0_1_rdata,
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-- DataF1 => sample_f1_rdata,
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-- DataF2 => sample_f3_rdata,
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-- Read_DEMUX => sample_ren,
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-- Empty => demux_empty,
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-- Data => demux_data);
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--FFT_1 : FFT
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-- GENERIC MAP (
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-- Data_sz => 16,
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-- NbData => 256)
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-- PORT MAP (
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-- clkm => clk,
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-- rstn => rstn,
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-- FifoIN_Empty => demux_empty,
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-- FifoIN_Data => demux_data,
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-- FifoOUT_Full => fft_fifo_full,
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-- Read => demux_ren,
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-- Write => fft_fifo_wen,
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-- ReUse => fft_fifo_reuse,
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-- Data => fft_fifo_data);
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--lppFIFO_fft : lppFIFOxN
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-- GENERIC MAP (
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-- tech => tech,
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-- Data_sz => 16,
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-- FifoCnt => 5,
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-- Enable_ReUse => '1')
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-- PORT MAP (
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-- rst => rstn,
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-- wclk => clk,
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-- rclk => clk,
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-- ReUse => fft_fifo_reuse,
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-- wen => fft_fifo_wen,
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-- ren => SP_fifo_ren,
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-- wdata => fft_fifo_data,
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-- rdata => SP_fifo_data,
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-- full => fft_fifo_full,
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-- empty => OPEN);
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--MatriceSpectrale_1 : MatriceSpectrale
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-- GENERIC MAP (
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-- Input_SZ => 16,
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-- Result_SZ => 32)
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-- PORT MAP (
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-- clkm => clk,
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-- rstn => rstn,
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-- FifoIN_Full => fft_fifo_full,
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-- FifoOUT_Full => , -- TODO
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-- Data_IN => SP_fifo_data,
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-- ACQ => , -- TODO
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-- FlagError => , -- TODO
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-- Pong => , -- TODO
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-- Write => , -- TODO
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-- Read => SP_fifo_ren,
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-- Data_OUT => ); -- TODO
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-----------------------------------------------------------------------------
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-- DMA SPECTRAL MATRIX
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-----------------------------------------------------------------------------
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lpp_dma_ip_1 : lpp_dma_ip
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GENERIC MAP (
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tech => tech,
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hindex => hindex_SpectralMatrix)
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PORT MAP (
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HCLK => clk,
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HRESETn => rstn,
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AHB_Master_In => AHB_DMA_SpectralMatrix_In,
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AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
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-- Connect to Spectral Matrix --
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fifo_data => fifo_data,
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fifo_empty => fifo_empty,
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fifo_ren => fifo_ren,
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header => header,
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header_val => header_val,
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header_ack => header_ack,
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-- APB REG
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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debug_reg => debug_reg,
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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config_active_interruption_onError => config_active_interruption_onError,
|
|
|
addr_matrix_f0_0 => addr_matrix_f0_0,
|
|
|
addr_matrix_f0_1 => addr_matrix_f0_1,
|
|
|
addr_matrix_f1 => addr_matrix_f1,
|
|
|
addr_matrix_f2 => addr_matrix_f2);
|
|
|
|
|
|
lpp_top_apbreg_1 : lpp_top_apbreg
|
|
|
GENERIC MAP (
|
|
|
pindex => pindex,
|
|
|
paddr => paddr,
|
|
|
pmask => pmask,
|
|
|
pirq => pirq)
|
|
|
PORT MAP (
|
|
|
HCLK => clk,
|
|
|
HRESETn => rstn,
|
|
|
apbi => apbi,
|
|
|
apbo => apbo,
|
|
|
|
|
|
ready_matrix_f0_0 => ready_matrix_f0_0,
|
|
|
ready_matrix_f0_1 => ready_matrix_f0_1,
|
|
|
ready_matrix_f1 => ready_matrix_f1,
|
|
|
ready_matrix_f2 => ready_matrix_f2,
|
|
|
error_anticipating_empty_fifo => error_anticipating_empty_fifo,
|
|
|
error_bad_component_error => error_bad_component_error,
|
|
|
debug_reg => debug_reg,
|
|
|
status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
|
|
|
status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
|
|
|
status_ready_matrix_f1 => status_ready_matrix_f1,
|
|
|
status_ready_matrix_f2 => status_ready_matrix_f2,
|
|
|
status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
|
|
|
status_error_bad_component_error => status_error_bad_component_error,
|
|
|
config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
|
|
|
config_active_interruption_onError => config_active_interruption_onError,
|
|
|
addr_matrix_f0_0 => addr_matrix_f0_0,
|
|
|
addr_matrix_f0_1 => addr_matrix_f0_1,
|
|
|
addr_matrix_f1 => addr_matrix_f1,
|
|
|
addr_matrix_f2 => addr_matrix_f2);
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- WAVEFORM
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
delay_valid_waveform : PROCESS (clk, rstn)
|
|
|
BEGIN
|
|
|
IF rstn = '0' THEN
|
|
|
data_f0_in_valid <= '0';
|
|
|
data_f1_in_valid <= '0';
|
|
|
ELSIF clk'EVENT AND clk = '1' THEN
|
|
|
data_f0_in_valid_r <= NOT sample_f0_wen;
|
|
|
data_f0_in_valid <= NOT data_f0_in_valid_r;
|
|
|
data_f1_in_valid <= NOT sample_f1_wen;
|
|
|
END IF;
|
|
|
END PROCESS delay_valid_waveform;
|
|
|
|
|
|
data_f2_in_valid <= NOT sample_f2_wen;
|
|
|
data_f3_in_valid <= NOT sample_f3_wen;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
lpp_waveform_1 : lpp_waveform
|
|
|
GENERIC MAP (
|
|
|
data_size => 16,
|
|
|
nb_snapshot_param_size => nb_snapshot_param_size,
|
|
|
delta_snapshot_size => delta_snapshot_size,
|
|
|
delta_f2_f0_size => delta_f2_f0_size,
|
|
|
delta_f2_f1_size => delta_f2_f1_size)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
|
|
|
coarse_time_0 => coarse_time(0),
|
|
|
delta_snapshot => waveform_delta_snapshot,
|
|
|
delta_f2_f1 => waveform_delta_f2_f1,
|
|
|
delta_f2_f0 => waveform_delta_f2_f0,
|
|
|
|
|
|
enable_f0 => waveform_enable_f0,
|
|
|
enable_f1 => waveform_enable_f1,
|
|
|
enable_f2 => waveform_enable_f2,
|
|
|
enable_f3 => waveform_enable_f3,
|
|
|
|
|
|
burst_f0 => waveform_burst_f0,
|
|
|
burst_f1 => waveform_burst_f1,
|
|
|
burst_f2 => waveform_burst_f2,
|
|
|
|
|
|
nb_snapshot_param => waveform_nb_snapshot_param,
|
|
|
|
|
|
data_f0_in => sample_f0_wdata,
|
|
|
data_f1_in => sample_f1_wdata,
|
|
|
data_f2_in => sample_f2_wdata,
|
|
|
data_f3_in => sample_f3_wdata,
|
|
|
|
|
|
data_f0_in_valid => data_f0_in_valid,
|
|
|
data_f1_in_valid => data_f1_in_valid,
|
|
|
data_f2_in_valid => data_f2_in_valid,
|
|
|
data_f3_in_valid => data_f3_in_valid);
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
--
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
--DONE : add the irq alert for DMA matrix transfert ending
|
|
|
|
|
|
--TODO : add 5 bit register into APB to control the DATA SHIPING
|
|
|
--TODO : data shiping
|
|
|
|
|
|
--TODO : add Spectral Matrix (FFT + SP)
|
|
|
--TODO : add DMA for WaveForms Picker
|
|
|
--TODO : add APB Reg to control WaveForms Picker
|
|
|
--TODO : add WaveForms Picker
|
|
|
|
|
|
END tb;
|
|
|
|
