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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.general_purpose.ALL;
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ENTITY lpp_waveform_fifo_arbiter_reg IS
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GENERIC(
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data_size : INTEGER;
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data_nb : INTEGER);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
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enable : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
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TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
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SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
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SIGNAL reg_sel : INTEGER := 0;
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SIGNAL reg_sel_s : INTEGER := 0;
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BEGIN
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all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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reg(I) <= 0;
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF run = '0' THEN
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reg(I) <= 0;
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ELSE
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IF sel(I) = '1' THEN
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reg(I) <= reg_sel_s;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_reg;
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reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
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reg(1) WHEN sel(1) = '1' ELSE
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reg(2) WHEN sel(2) = '1' ELSE
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reg(3);
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reg_sel_s <= reg_sel WHEN enable = '0' ELSE
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reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
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0;
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data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size));
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data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size));
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END ARCHITECTURE;
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