HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd

Few fixes....

Few fixes. Whole LFR simulation WIP.

pellion - - Load All Authors

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r463:832e74562224 (LFR-EM) WFP_MS-1-1-34 JC


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        pellion
    
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      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      ------------------------------------------------------------------------------

      --                    Author : Jean-christophe PELLION

      --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr

      ------------------------------------------------------------------------------

      LIBRARY IEEE;

      USE IEEE.std_logic_1164.ALL;

      USE IEEE.numeric_std.ALL;

      LIBRARY lpp;

      USE lpp.lpp_waveform_pkg.ALL;

      USE lpp.general_purpose.ALL;

      ENTITY lpp_waveform_fifo_arbiter_reg IS

        GENERIC(

          data_size : INTEGER;

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          data_nb   : INTEGER);

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        PORT(

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          clk  : IN STD_LOGIC;

          rstn : IN STD_LOGIC;

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          ---------------------------------------------------------------------------

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          run  : IN STD_LOGIC;

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          max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);

          enable : IN STD_LOGIC;

          sel    : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);

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          data   : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);

          data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)

          );

      END ENTITY;

      ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS

        TYPE   Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;

        SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);

        pellion
    
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        SIGNAL reg_sel   : INTEGER := 0;

        SIGNAL reg_sel_s : INTEGER := 0;

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      BEGIN

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        all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE

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          PROCESS (clk, rstn)

          BEGIN  -- PROCESS

            IF rstn = '0' THEN                  -- asynchronous reset (active low)

              reg(I) <= 0;

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            ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge

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              IF run = '0' THEN

                reg(I) <= 0;

              ELSE

                IF sel(I) = '1' THEN

                  reg(I) <= reg_sel_s;

                END IF;

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              END IF;

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            END IF;

          END PROCESS;

        END GENERATE all_reg;

        reg_sel <= reg(0) WHEN sel(0) = '1' ELSE

                   reg(1) WHEN sel(1) = '1' ELSE

                   reg(2) WHEN sel(2) = '1' ELSE

                   reg(3);

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        reg_sel_s <= reg_sel     WHEN enable = '0' ELSE

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                     reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE

                     0;

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        data   <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size));

        data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size));

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      END ARCHITECTURE;

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pellion WaveFormPicker Update...	r232	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		------------------------------------------------------------------------------
		-- Author : Jean-christophe PELLION
		-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
		------------------------------------------------------------------------------
		LIBRARY IEEE;
		USE IEEE.std_logic_1164.ALL;
		USE IEEE.numeric_std.ALL;

		LIBRARY lpp;
		USE lpp.lpp_waveform_pkg.ALL;
		USE lpp.general_purpose.ALL;

		ENTITY lpp_waveform_fifo_arbiter_reg IS
		GENERIC(
		data_size : INTEGER;
pellion new bitstream to test	r443	data_nb : INTEGER);
pellion WaveFormPicker Update...	r232	PORT(
pellion new bitstream to test	r443	clk : IN STD_LOGIC;
		rstn : IN STD_LOGIC;
pellion WaveFormPicker Update...	r232	---------------------------------------------------------------------------
pellion new bitstream to test	r443	run : IN STD_LOGIC;
pellion WaveFormPicker Update...	r232
		max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);

		enable : IN STD_LOGIC;
		sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
pellion new bitstream to test	r443
pellion WaveFormPicker Update...	r232	data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
		data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
		);
		END ENTITY;


		ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS

		TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
		SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);

pellion Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)	r286	SIGNAL reg_sel : INTEGER := 0;
		SIGNAL reg_sel_s : INTEGER := 0;
pellion WaveFormPicker Update...	r232
		BEGIN

pellion new bitstream to test	r443	all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE
pellion WaveFormPicker Update...	r232	PROCESS (clk, rstn)
		BEGIN -- PROCESS
		IF rstn = '0' THEN -- asynchronous reset (active low)
		reg(I) <= 0;
pellion new bitstream to test	r443	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
pellion WaveFormPicker Update...	r232	IF run = '0' THEN
		reg(I) <= 0;
		ELSE
		IF sel(I) = '1' THEN
		reg(I) <= reg_sel_s;
		END IF;
pellion new bitstream to test	r443	END IF;
pellion WaveFormPicker Update...	r232	END IF;
		END PROCESS;
		END GENERATE all_reg;

		reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
		reg(1) WHEN sel(1) = '1' ELSE
		reg(2) WHEN sel(2) = '1' ELSE
		reg(3);

pellion 1.1.34 : idem 1.1.33 avec reset soft pour LFR subsystem	r463	reg_sel_s <= reg_sel WHEN enable = '0' ELSE
pellion WaveFormPicker Update...	r232	reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
		0;

pellion new bitstream to test	r443	data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size));
		data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size));
pellion WaveFormPicker Update...	r232
		END ARCHITECTURE;