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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY lpp_waveform_dma_selectaddress IS
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GENERIC (
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nb_burst_available_size : INTEGER := 11
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);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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run : IN STD_ULOGIC;
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enable : IN STD_LOGIC;
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update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_full : OUT STD_LOGIC;
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status_full_ack : IN STD_LOGIC;
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status_full_err : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS
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TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED);
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SIGNAL state : state_fsm_select_data;
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SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
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SIGNAL update_s : STD_LOGIC;
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SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0);
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BEGIN
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update_s <= update(0) OR update(1);
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addr_data <= address;
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nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1);
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FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
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BEGIN
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IF HRESETn = '0' THEN
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state <= IDLE;
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address <= (OTHERS => '0');
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nb_send <= (OTHERS => '0');
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status_full <= '0';
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status_full_err <= '0';
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update_r <= "00";
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ELSIF HCLK'EVENT AND HCLK = '1' THEN
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update_r <= update;
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CASE state IS
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WHEN IDLE =>
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IF run = '0' THEN
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state <= IDLE;
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address <= (OTHERS => '0');
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nb_send <= (OTHERS => '0');
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status_full <= '0';
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status_full_err <= '0';
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update_r <= "00";
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ELSE
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IF enable = '0' THEN
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state <= UPDATED;
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ELSIF update_s = '1' THEN
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state <= ADD;
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END IF;
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END IF;
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WHEN ADD =>
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IF run = '0' THEN
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state <= IDLE;
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ELSE
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IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
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state <= IDLE;
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IF update_r = "10" THEN
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address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
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nb_send <= nb_send_next;
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ELSIF update_r = "01" THEN
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address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
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END IF;
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ELSE
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state <= FULL;
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nb_send <= (OTHERS => '0');
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status_full <= '1';
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END IF;
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END IF;
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WHEN FULL =>
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IF run = '0' THEN
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state <= IDLE;
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ELSE
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status_full <= '0';
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IF status_full_ack = '1' THEN
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IF update_s = '1' THEN
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status_full_err <= '1';
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END IF;
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state <= UPDATED;
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ELSE
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IF update_s = '1' THEN
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status_full_err <= '1';
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state <= ERR;
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END IF;
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END IF;
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END IF;
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WHEN ERR =>
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IF run = '0' THEN
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state <= IDLE;
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ELSE
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status_full_err <= '0';
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IF status_full_ack = '1' THEN
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state <= UPDATED;
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END IF;
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END IF;
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WHEN UPDATED =>
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IF run = '0' THEN
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state <= IDLE;
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ELSE
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status_full_err <= '0';
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address <= addr_data_reg;
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IF enable = '1' THEN
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state <= IDLE;
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END IF;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS FSM_SELECT_ADDRESS;
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END Behavioral;
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