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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY lpp_fifo_control IS
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GENERIC(
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AddrSz : INTEGER RANGE 2 TO 12 := 8;
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EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
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FULL_THRESHOLD_LIMIT : INTEGER := 5
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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reUse : IN STD_LOGIC;
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run : IN STD_LOGIC;
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--IN
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fifo_r_en : IN STD_LOGIC;
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fifo_w_en : IN STD_LOGIC;
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mem_r_en : OUT STD_LOGIC;
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mem_w_en : OUT STD_LOGIC;
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mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
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mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
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empty : OUT STD_LOGIC;
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full : OUT STD_LOGIC;
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full_almost : OUT STD_LOGIC;
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empty_threshold : OUT STD_LOGIC;
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full_threshold : OUT STD_LOGIC
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);
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END ENTITY;
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ARCHITECTURE beh OF lpp_fifo_control IS
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SIGNAL sFull : STD_LOGIC;
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SIGNAL sFull_s : STD_LOGIC;
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SIGNAL sEmpty_s : STD_LOGIC;
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SIGNAL sEmpty : STD_LOGIC;
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SIGNAL sREN : STD_LOGIC;
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SIGNAL sWEN : STD_LOGIC;
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SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL almost_full_s : STD_LOGIC;
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SIGNAL almost_full_r : STD_LOGIC;
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SIGNAL mem_r_addr_int : INTEGER;
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SIGNAL mem_w_addr_int : INTEGER;
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SIGNAL space_busy : INTEGER;
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SIGNAL space_free : INTEGER;
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CONSTANT length : INTEGER := 2**(AddrSz);
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BEGIN
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mem_r_addr <= Raddr_vect;
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mem_w_addr <= Waddr_vect;
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mem_r_en <= sREN;
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mem_w_en <= sWEN;
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--=============================
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-- Read section
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--=============================
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sREN <= FIFO_R_EN OR sEmpty;
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--sRE <= NOT sREN;
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sEmpty_s <= '0' WHEN ReUse = '1' ELSE
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'1' WHEN sEmpty = '1' AND Fifo_W_En = '1' ELSE
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'1' WHEN sEmpty = '0' AND (Fifo_W_En = '1' AND Fifo_R_en = '0' AND Raddr_vect_s = Waddr_vect) ELSE
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'0';
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Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')THEN
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Raddr_vect <= (OTHERS => '0');
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sempty <= '1';
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ELSIF(clk'EVENT AND clk = '1')THEN
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IF run = '0' THEN
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Raddr_vect <= (OTHERS => '0');
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sempty <= '1';
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ELSE
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sEmpty <= sempty_s;
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IF(sREN = '0' AND sempty = '0')THEN
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Raddr_vect <= Raddr_vect_s;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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--=============================
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-- Write section
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--=============================
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sWEN <= FIFO_W_EN OR sFull;
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-- sWE <= NOT sWEN;
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sFull_s <= '1' WHEN ReUse = '1' ELSE
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'1' WHEN Waddr_vect_s = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
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'1' WHEN sFull = '1' AND FIFO_R_EN = '1' ELSE
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'0';
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almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
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'1' WHEN almost_full_r = '1' AND FIFO_W_EN = FIFO_R_EN ELSE
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'0';
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Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
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PROCESS (clk, rstn)
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BEGIN
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IF(rstn = '0')THEN
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Waddr_vect <= (OTHERS => '0');
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sfull <= '0';
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almost_full_r <= '0';
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ELSIF(clk'EVENT AND clk = '1')THEN
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IF run = '0' THEN
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Waddr_vect <= (OTHERS => '0');
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sfull <= '0';
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almost_full_r <= '0';
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ELSE
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sfull <= sfull_s;
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almost_full_r <= almost_full_s;
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IF(sWEN = '0' AND sfull = '0')THEN
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Waddr_vect <= Waddr_vect_s;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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full_almost <= almost_full_s;
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full <= sFull_s;
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empty <= sEmpty_s;
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-----------------------------------------------------------------------------
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mem_w_addr_int <= to_integer(UNSIGNED(Waddr_vect));
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mem_r_addr_int <= to_integer(UNSIGNED(Raddr_vect));
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space_busy <= length WHEN sFull = '1' ELSE
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length + mem_w_addr_int - mem_r_addr_int WHEN mem_w_addr_int < mem_r_addr_int ELSE
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mem_w_addr_int - mem_r_addr_int;
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space_free <= length - space_busy;
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empty_threshold <= '0' WHEN space_busy > EMPTY_THRESHOLD_LIMIT ELSE '1';
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full_threshold <= '0' WHEN space_free > FULL_THRESHOLD_LIMIT ELSE '1';
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-----------------------------------------------------------------------------
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END ARCHITECTURE;
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