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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_fifo_4_shared_headreg_latency_0 IS
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
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o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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---------------------------------------------------------------------------
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i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
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i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_0 IS
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TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL reg_head_data : REG_HEAD_TYPE;
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SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
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SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
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BEGIN
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--i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
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i_data_ren <= i_data_ren_s;
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o_empty_almost <= i_empty_almost; --TODO
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o_rdata_0 <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ;
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o_rdata_1 <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ;
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o_rdata_2 <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ;
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o_rdata_3 <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ;
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i_data_ren_s(0) <= i_data_ren_s_temp(0);
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i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1';
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i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1';
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i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1';
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each_fifo: FOR I IN 3 DOWNTO 0 GENERATE
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o_empty(I) <= NOT reg_head_full(I);
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-- i_data_ren_pre(I) <= i_data_ren_s(I);
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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reg_head_data(I) <= (OTHERS => '0');
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i_data_ren_pre(I) <= '1';
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reg_head_full(I) <= '0';
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o_data_ren_pre(I) <= '1';
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ELSIF clk'event AND clk = '1' THEN
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o_data_ren_pre(I) <= o_data_ren(I) ;
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IF i_data_ren_pre(I) = '0' THEN
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reg_head_data(I) <= i_rdata;
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END IF;
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i_data_ren_pre(I) <= i_data_ren_s(I);
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-- IF i_data_ren_pre(I) = '0' THEN
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IF i_data_ren_s(I) = '0' THEN
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reg_head_full(I) <= '1';
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-- ELSIF o_data_ren_pre(I) = '0' THEN
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ELSIF o_data_ren(I) = '0' THEN
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reg_head_full(I) <= '0';
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END IF;
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END IF;
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END PROCESS;
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i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE
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'0' WHEN o_data_ren(I) = '0' ELSE
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'0' WHEN reg_head_full(I) = '0' ELSE
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'1';
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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i_empty_reg(I) <= '1';
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ELSIF clk'event AND clk = '1' THEN
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i_empty_reg(I) <= i_empty(I);
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END IF;
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END PROCESS;
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END GENERATE each_fifo;
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END ARCHITECTURE;
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