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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_fifo_4_shared IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
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FULL_THRESHOLD_LIMIT : INTEGER := 5;
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DataSz : INTEGER RANGE 1 TO 32 := 8;
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AddrSz : INTEGER RANGE 3 TO 12 := 8
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
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empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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---------------------------------------------------------------------------
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full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
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full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
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full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE beh OF lpp_fifo_4_shared IS
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SIGNAL full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
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TYPE LPP_TYPE_ADDR_FIFO_SHARED IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(AddrSz-3 DOWNTO 0);
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SIGNAL mem_r_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
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SIGNAL mem_w_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
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SIGNAL mem_r_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
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SIGNAL mem_w_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
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SIGNAL fifo_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL fifo_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL mem_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL mem_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL mem_r_e : STD_LOGIC;
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SIGNAL mem_w_e : STD_LOGIC;
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SIGNAL NB_DATA_IN_FIFO : INTEGER;
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CONSTANT length : INTEGER := 2**(AddrSz-2);
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TYPE INTEGER_ARRAY_4 IS ARRAY (3 DOWNTO 0) OF INTEGER;
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SIGNAL mem_r_addr_v_int : INTEGER_ARRAY_4;
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SIGNAL mem_w_addr_v_int : INTEGER_ARRAY_4;
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SIGNAL space_busy : INTEGER_ARRAY_4;
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SIGNAL space_free : INTEGER_ARRAY_4;
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BEGIN
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-----------------------------------------------------------------------------
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SRAM : syncram_2p
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GENERIC MAP(tech, AddrSz, DataSz)
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PORT MAP(clk, mem_r_e, mem_r_addr, r_data,
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clk, mem_w_e, mem_w_addr, w_data);
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-----------------------------------------------------------------------------
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mem_r_addr <= "00" & mem_r_addr_v(0) WHEN fifo_r_en_v(0) = '0' ELSE
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"01" & mem_r_addr_v(1) WHEN fifo_r_en_v(1) = '0' ELSE
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"10" & mem_r_addr_v(2) WHEN fifo_r_en_v(2) = '0' ELSE
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"11" & mem_r_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
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mem_w_addr <= "00" & mem_w_addr_v(0) WHEN fifo_w_en_v(0) = '0' ELSE
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"01" & mem_w_addr_v(1) WHEN fifo_w_en_v(1) = '0' ELSE
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"10" & mem_w_addr_v(2) WHEN fifo_w_en_v(2) = '0' ELSE
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"11" & mem_w_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
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mem_r_e <= '0' WHEN mem_r_en_v = "1111" ELSE '1';
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mem_w_e <= '0' WHEN mem_w_en_v = "1111" ELSE '1';
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----------------------------------------------------------------------------
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all_fifo : FOR I IN 3 DOWNTO 0 GENERATE
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fifo_r_en_v(I) <= r_en(I);
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fifo_w_en_v(I) <= w_en(I);
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lpp_fifo_control_1 : lpp_fifo_control
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GENERIC MAP (
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AddrSz => AddrSz-2,
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EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT,
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FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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reUse => '0',
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run => run,
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fifo_r_en => fifo_r_en_v(I),
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fifo_w_en => fifo_w_en_v(I),
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mem_r_en => mem_r_en_v(I),
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mem_w_en => mem_w_en_v(I),
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mem_r_addr => mem_r_addr_v(I),
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mem_w_addr => mem_w_addr_v(I),
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empty => empty(I),
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full => full_s(I),
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full_almost => full_almost(I),
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empty_threshold => empty_threshold(I),
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full_threshold => full_threshold(I)
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);
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--full(I) <= full_s(I);
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--mem_w_addr_v_int(I) <= to_integer(UNSIGNED(mem_w_addr_v(I)));
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--mem_r_addr_v_int(I) <= to_integer(UNSIGNED(mem_r_addr_v(I)));
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--space_busy(I) <= length WHEN full_s(I) = '1' ELSE
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-- length + mem_w_addr_v_int(I) - mem_r_addr_v_int(I) WHEN mem_w_addr_v_int(I) < mem_r_addr_v_int(I) ELSE
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-- mem_w_addr_v_int(I) - mem_r_addr_v_int(I);
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--space_free(I) <= length - space_busy(I);
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--empty_threshold(I) <= '0' WHEN space_busy(I) > EMPTY_THRESHOLD_LIMIT ELSE '1';
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--full_threshold(I) <= '0' WHEN space_free(I) > FULL_THRESHOLD_LIMIT ELSE '1';
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END GENERATE all_fifo;
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END ARCHITECTURE;
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