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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.lpp_cna.ALL;
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USE lpp.apb_devices_list.ALL;
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ENTITY apb_lfr_cal IS
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GENERIC (
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pindex : INTEGER := 0;
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paddr : INTEGER := 0;
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pmask : INTEGER := 16#fff#;
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tech : INTEGER := 0;
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PRESZ : INTEGER := 8;
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CPTSZ : INTEGER := 16;
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datawidth : INTEGER := 18;
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dacresolution : INTEGER := 12;
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abits : INTEGER := 8
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);
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PORT (
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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SDO : OUT STD_LOGIC;
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SCK : OUT STD_LOGIC;
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SYNC : OUT STD_LOGIC;
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SMPCLK : OUT STD_LOGIC
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);
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END ENTITY;
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--! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
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--! et les sorties seront cabl�es vers le convertisseur.
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ARCHITECTURE ar_apb_lfr_cal OF apb_lfr_cal IS
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CONSTANT REVISION : INTEGER := 1;
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CONSTANT pconfig : apb_config_type := (
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0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
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1 => apb_iobar(paddr, pmask));
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SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
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SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
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SIGNAL Reload : STD_LOGIC;
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SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
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SIGNAL WEN : STD_LOGIC;
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SIGNAL LOAD_ADDRESSN : STD_LOGIC;
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SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
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SIGNAL INTERLEAVED : STD_LOGIC;
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SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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cal : lfr_cal_driver
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GENERIC MAP(
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tech => tech,
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PRESZ => PRESZ,
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CPTSZ => CPTSZ,
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datawidth => datawidth,
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abits => abits
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)
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PORT MAP(
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clk => clk,
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rstn => rstn,
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pre => pre,
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N => N,
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Reload => Reload,
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DATA_IN => DATA_IN,
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WEN => WEN,
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LOAD_ADDRESSN => LOAD_ADDRESSN,
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ADDRESS_IN => ADDRESS_IN,
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ADDRESS_OUT => ADDRESS_OUT,
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INTERLEAVED => INTERLEAVED,
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DAC_CFG => DAC_CFG,
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SYNC => SYNC,
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DOUT => SDO,
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SCLK => SCK,
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SMPCLK => SMPCLK -- OPEN
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);
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PROCESS(rstn, clk)
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BEGIN
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IF(rstn = '0')then
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pre <= (OTHERS => '1');
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N <= (OTHERS => '1');
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Reload <= '1';
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DATA_IN <= (OTHERS => '0');
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WEN <= '1';
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LOAD_ADDRESSN <= '1';
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ADDRESS_IN <= (OTHERS => '1');
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INTERLEAVED <= '0';
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DAC_CFG <= (OTHERS => '0');
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Rdata <= (OTHERS => '0');
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ELSIF(clk'EVENT AND clk = '1')then
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--APB Write OP
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IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
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CASE apbi.paddr(4 DOWNTO 2) IS
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WHEN "000" =>
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DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
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Reload <= apbi.pwdata(4);
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INTERLEAVED <= apbi.pwdata(5);
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WHEN "001" =>
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pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
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WHEN "010" =>
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N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
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WHEN "011" =>
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ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
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LOAD_ADDRESSN <= '0';
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WHEN "100" =>
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DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
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WEN <= '0';
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WHEN OTHERS =>
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NULL;
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END CASE;
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ELSE
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LOAD_ADDRESSN <= '1';
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WEN <= '1';
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END IF;
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--APB Read OP
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IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
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CASE apbi.paddr(4 DOWNTO 2) IS
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WHEN "000" =>
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Rdata(3 DOWNTO 0) <= DAC_CFG;
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Rdata(4) <= Reload;
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Rdata(5) <= INTERLEAVED;
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Rdata(31 DOWNTO 6) <= (OTHERS => '0');
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WHEN "001" =>
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Rdata(PRESZ-1 DOWNTO 0) <= pre;
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Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
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WHEN "010" =>
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Rdata(CPTSZ-1 DOWNTO 0) <= N;
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Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
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WHEN "011" =>
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Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
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Rdata(31 DOWNTO abits) <= (OTHERS => '0');
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WHEN "100" =>
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Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
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Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
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WHEN OTHERS =>
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Rdata <= (OTHERS => '0');
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END CASE;
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END IF;
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END IF;
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apbo.pconfig <= pconfig;
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END PROCESS;
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apbo.prdata <= Rdata WHEN apbi.penable = '1';
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END ARCHITECTURE ar_apb_lfr_cal;
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